NIS5431MT1TXG - ON SEMICONDUCTOR

July, 2016 − Rev. 5 1Publication Order Number:

NIS5431/D

NIS5431 Series

+3.3 Volt Electronic Fuse

The NIS5431 series is a cost effective, resettable fuse. It is designed

to buffer the load device from excessive input voltage which can

damage sensitive circuits. It also includes an overvoltage clamp circuit

that limits the output voltage during transients but does not shut the

unit down, thereby allowing the load circuit to continue operation.

Features

•Integrated Power Device

•33 mW Typical

•Internal Charge Pump

•Internal Undervoltage Lockout Circuit

•Internal Overvoltage Clamp

•These are Pb−Free Devices and are RoHS Compliant

Typical Applications

•Mother Board

•Hard Drives

•Fan Drives

ORDERING INFORMATION

Device Features Marking Package Shipping†

NIS5431MT1TXG Thermal Latching 31 WDFN10

(Pb−Free) 3000 / Tape & Reel

NIS5431MT1TWG Thermal Latching 31W WDFN10

(Pb−Free) 3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

www.onsemi.com

MARKING DIAGRAM

WDFN10

CASE 522AA

XXX

AYWG

XXX = Specific Device Code

A = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

(Note: Microdot may be in either location)

5.0 AMP, 3.3 VOLT

ELECTRONIC FUSE

Pin Function

1−5 SOURCE

LIMITA

LIMITB

8 Enable/Fault

9 dv/dt

10 GND

11 (flag) VCC

PIN ASSIGNMENTS

(Top View)

GND

dv/dt

En/Flt

ILIMITB

Src

Src ILIMITA

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VIN

VOUT

Enable/Fault

GND

Thermal

Shutdown

Charge

Pump

Current

Limit

dv/dt

Control

Enable

UVLO

dV/dt

ILIMITB

Voltage

Clamp

Figure 1. Block Diagram

ILIMITA

FUNCTIONAL PIN DESCRIPTION

Pin Function Description

1−5 Source This pin is the source of the internal power FET and the output terminal of the fuse.

6 ILIMITA A resistor between this pin and the ILIMITB pin sets the overload and short circuit current limit levels.

7 ILIMITB A resistor between this pin and the ILIMITA pin sets the overload and short circuit current limit levels.

8 Enable/Fault The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the

output of the device by pulling it to ground using an open drain or open collector device. If a thermal

fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that

the device is in thermal shutdown. It can also be connected to another device in this family to cause

a simultaneous shutdown during thermal events.

9 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal ca-

pacitor that allows it to ramp up over a period of 1.4 ms. An external capacitor can be added to this

pin to increase the ramp time. If an additional time delay is not required, this pin should be left open.

10 Ground Negative input voltage to the device. This is used as the internal reference for the IC.

11 (belly pad) VCC Positive input voltage to the device.

MAXIMUM RATINGS

Rating Symbol Value Unit

Input Voltage, operating, steady−state (VCC to GND, Note 1) VIN −0.6 to 14 V

Thermal Resistance, Junction−to−Air

0.1 in2 copper (Note 2)

0.5 in2 copper (Note 2)

JESD51−7 4−layer board

qJA 154

°C/W

Thermal Resistance, Junction−to−Lead (Pin 1) qJL 49 °C/W

Thermal Resistance, Junction−to−Case qJC 20 °C/W

Total Power Dissipation @ TA = 25°C (operating) Pmax 2.5 W

Operating Temperature Range (Notes 3 and 4) TJ−40 to 150 °C

Nonoperating Temperature Range TJ−55 to 155 °C

Lead Temperature, Soldering (10 Sec) TL260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the device.

2. 1 oz copper, double−sided FR4.

3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the

maximum ratings for extended periods of time.

4. Exceeding TJ will thermally destroy the FET. See AND9042/D.

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ELECTRICAL CHARACTERISTICS

(Unless otherwise noted: VCC = 3.3 V, Cin = 2.2 mF, CL = 70 mF, dv/dt pin open, TA = 25°C unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

POWER FET

Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load)

(Note 9) Tdly 200 ms

ON Resistance (Note 5)

TJ = 140°C (Note 6) RDS(on) 25 33

60 50 mW

Off State Output Voltage

(VCC = 8 Vdc, VGS = 0 Vdc, RL = 100 kW) (Note 9) Voff 10 200 mV

Output Capacitance

(VDS = 3.3 VDC, VGS = 0 VDC, RL = R)Cout 230 pF

Continuous Current (TA = 25°C, 0.5 in2 pad) (Note 6)

(TA = 25°C, JESD51−7 4−layer board)

(TA = 80°C, minimum copper)

4.2

5.0

2.3

THERMAL LATCH

Shutdown Temperature (Note 6) TSD 150 175 200 °C

Thermal Hysteresis (Decrease in die temperature for turn on, does not

apply to latching parts) THyst 45 °C

UNDER/OVERVOLTAGE PROTECTION

VOUT Maximum (VCC = 8 V) NIS5431 Vout−clamp 3.6 3.85 4.1 V

Undervoltage Lockout (Turn on, Voltage Going High) VUVLO 1.91 2.35 2.5 V

UVLO Hysteresis (Note 9) VHyst 0.145 V

CURRENT LIMIT

Kelvin Short Circuit Current Limit (Note 7) (RLimit = 10 W)ILIM 1.35 1.90 2.45 A

Overload Current Limit (Note 7) (RLimit = 10 W)ILIM 6.0 A

dv/dt CIRCUIT

Output Voltage Ramp Time (Enable to VOUT = 3.0 V) (Note 9) tslew 0.3 0.6 1.2 ms

Maximum Capacitor Voltage Vmax VCC V

ENABLE/FAULT

Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V

Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V

Logic Level High (Output Enabled) (Note 9) Vin−high 1.96 2.2 2.50 V

High State Maximum Voltage Vin−max 2.51 3.3 5.2 V

Logic Low Sink Current (Venable = 0 V) Iin−low −12 −20 mA

Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak 1.0 mA

Maximum Fanout for Fault Signal (Total number of chips that can be

connected to this pin for simultaneous shutdown) Fan 3.0 Units

TOTAL DEVICE

Bias Current (Operational) (Note 9) IBias 400 750 mA

Bias Current (Shutdown) (Note 9) IBias 80 mA

Minimum Operating Voltage (Notes 6 and 8) Vmin 2.5 V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Pulse test: Pulse width 300 ms, duty cycle 2%.

6. Verified by design.

7. Refer to explanation of short circuit and overload conditions in application note AND8140/D.

8. Device will shut down prior to reaching this level based on actual UVLO trip point.

9. Guaranteed by characterization or design.

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Figure 2. Typical Application Circuit

LOAD

GND

ENABLE

3.3 V

NIS5431

SOURCE

VCC

ENABLE

ILIMITB

dv/dtGND

10 9

ILIMITA 6

Figure 3. Common Thermal Shutdown

SOURCE

VCC

ENABLE

ILIMIT

dv/dt

GND LOAD

ENABLE

LOAD

SOURCE

VCC

ILIMITB ENABLE

dv/dt GND

NIS5431 NISxxxx

ILIMITA

3.3 V 5 V or 12 V

APPLICATION INFORMATION

Basic Operation

This device is a self−protected, resettable, electronic fuse.

It contains circuits to monitor the input voltage, output

voltage, output current and die temperature.

On application of the input voltage, the device will apply

the input voltage to the load based on the restrictions of the

controlling circuits. The dv/dt of the output voltage will be

controlled by the internal dv/dt circuit. The output voltage

will slew from 0 V to the rated output voltage in 0.6 ms,

unless additional capacitance is added to the dv/dt pin.

The device will remain on as long as the temperature does

not exceed the 175°C limit that is programmed into the chip.

The current limit circuit does not shut down the part but will

reduce the conductivity of the FET to maintain a constant

current at the internally set current limit level. The input

overvoltage clamp also does not shutdown the part, but will

limit the output voltage to the Vout−clamp value in the event

that the input exceeds that level.

An internal charge pump provides bias for the gate voltage

of the internal n−channel power FET and also for the current

limit circuit. The remainder of the control circuitry operates

between the input voltage (VCC) and ground.

Application Information

It is recommended to connect an input decoupling

capacitor and an output filtering capacitor to the device to

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attenuate the power supply noise and the possible voltage

spikes caused by inductive loads. The values of these

capacitors depend on the characteristics of the power supply

and the inductance observed by the device at its input and

output, however, minimum values of 1 mF for the input

capacitor and 22 mF for the output capacitor are

recommended for most applications.

Power Limit

Refer to Application Note AND9042/D for ILIMSE

limitations.

Current Limit

The current limit circuit uses a SENSEFET along with a

reference and amplifier to control the peak current in the

device. The SENSEFET allows for a small fraction of the

load current to be measured, which has the advantage of

reducing the losses in the sense resistor as well as increasing

the value and decreasing the power rating of the sense

resistor. Sense resistors are typically in the tens of ohms

range with power ratings of several milliwatts making them

very inexpensive chip resistors.

The current limit circuit has two limiting values, one for

overload events which are defined as the mode of operation

in which the gate is high and the FET is fully enhanced. The

short circuit mode of operation occurs when the device is

actively limiting the current and the gate is at an intermediate

level. For a more detailed description of this circuit please

refer to application note AND8140.

Overvoltage Clamp

The overvoltage clamp consists of an amplifier and

reference. It monitors the output voltage and if the input

voltage exceeds the specified Vout maximum for the device,

the gate drive of the main FET is reduced to limit the output.

This is intended to allow operation through transients while

protecting the load. If an overvoltage condition exists for

many seconds, the device may overheat due to the voltage

drop across the FET combined with the load current. In this

event, the thermal protection circuit would shut down the

device.

Undervoltage Lockout

The undervoltage lockout circuit uses a comparator with

hysteresis to monitor the input voltage. If the input voltage

drops below the specified level, the output switch will be

switched to a high impedance state.

dv/dt Circuit

The dv/dt circuit brings the output voltage up under a

linear, controlled rate regardless of the load impedance

characteristics. An internal ramp generator creates a linear

ramp, and a control circuit forces the output voltage to

follow that ramp, scaled by a factor.

The default ramp time is approximately 0.6 ms. This can

be modified by adding an external capacitor at the dv/dt pin.

This pin includes an internal current source of

approximately 1 mA. Since the current level is very lo w, it i s

important to use a ceramic cap or other low leakage

capacitor. Aluminum electrolytic capacitors are not

recommended for this circuit.

The ramp time from 0 to the nominal output voltage can

be determined by the following equation, where t is in

seconds:

t0−3 +8.25 E5 @Cext

Where:

C is in Farads

t is in Seconds

Any time that the unit shuts down due to a fault, enable

shut−down, or recycling of input power, the timing capacitor

will be discharged and the output voltage will ramp from 0

at turn on.

Enable/Fault

The Enable/Fault Pin is a multi−function, bidirectional

pin that can control the output of the chip as well as send

information to other devices regarding the state of the chip.

When this pin is low, the output of the fuse will be turned off.

When this pin is high the output of the fuse will be

turned−on. If a thermal fault occurs, this pin will be pulled

low to an intermediate level by an internal circuit.

To use as a simple enable pin, an open drain or open

collector device should be connected to this pin. Due to its

tri−state operation, it should not be connected to any type of

logic with an internal pullup device.

If the chip shuts down due to the die temperature reaching

its thermal limit, this pin will be pulled down to an

intermediate level. This signal can be monitored by an

external circuit to communicate that a thermal shutdown has

occurred. If this pin is tied to another device in this family,

a thermal shutdown of one device will cause both devices to

disable their outputs. Both devices will turn on once the fault

is removed for the auto−retry devices.

For the latching thermal device, the outputs will be

enabled after the enable pin has been pulled to ground with

an external switch and then allowed to go high or after the

input power has been recycled. For the auto retry devices,

both devices will restart as soon as the die temperature of the

device in shutdown has been reduced to the lower thermal

limit. The thermal options are listed in the ordering table.

Thermal Protection

The NIS5431 includes an internal temperature sensing

circuit that senses the temperature on the die of the power

FET. If the temperature reaches 175°C, the device will shut

down, and remove power from the load. Output power can

be restored by either recycling the input power or toggling

the enable pin. Power will automatically be reapplied to the

load for auto−retry devices once the die temperature has

been reduced by 45°C.

The thermal limit has been set high intentionally, to

increase the trip time during high power transient events. It

is not recommended to operate this device above 150°C for

extended periods of time.

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TYPICAL CHARACTERISTICS

Figure 4. Current Limit vs. RLimit Figure 5. Overload Current Limit vs. RLimit

over Ambient Temperature

RLimit (W)R

Limit (W)

119865321

Figure 6. Short Circuit Current Limit vs. RLimit

over Ambient Temperature

RLimit (W)

1110876543

ILIM (A)

ILIM(OL) (A)

ILIM(SC) (A)

4 7 10 12

ILIM(OL)

ILIM(SC)

1198653214 71012

125°C

−40°C

25°C

125°C

−40°C

912

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Figure 7. Enable/Fault Signal Levels

DEVICE OPERATIONAL

THERMAL SHUTDOWN

SHUTDOWN, THERMAL RESET

FAULT/ENABLE SIGNAL

GND

0.82V

1.95V

3.3V

Figure 8. Enable/Fault Simplified Circuit

−

Startup

Blanking

Thermal

Shutdown

1.4 V

Thermal Reset

Enable SD

1.95 V

En/Fault

3.3 V

Thermal SD

12 mA

0.58 V

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PACKAGE DIMENSIONS

WDFN10, 3x3, 0.5P

CASE 522AA

ISSUE A

ÍÍÍ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.15 AND 0.30mm FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

SEATING

PLANE

0.15 C

2X 0.15 C

DIM

MIN NOM MAX

MILLIMETERS

0.70 0.75 0.80

A1 0.00 0.03 0.05

A3 0.20 REF

b0.18 0.24 0.30

D3.00 BSC

D2 2.45 2.50 2.55

E3.00 BSC

1.75 1.80 1.85

e0.50 BSC

0.19 TYP

PIN ONE

REFERENCE

0.08 C

0.10 C

10X

A0.10 C

NOTE 3

610X

K10

10X

0.05 C

0.35 0.40 0.45

TOP VIEW

SIDE VIEW

BOTTOM VIEW

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

2.1746

2.6016

1.8508

0.5000 PITCH

0.5651

10X

3.3048

0.3008

10X

DIMENSIONS: MILLIMETERS

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NIS5431/D

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