HRF-AT4521
Preliminary
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Web Site: www.mysoiservices.com Honeywell
Ema il: myso i ser v i ces@ h on eyw ell.com Solid St at e El ect ron i cs C ent er
12001 St ate Hig hway 55
2002 4521W Published J une 2002 Page 1 Plymouth, Minnesota 55441-4799
1-800-323-8295
31.0 dB, DC-4GHz, 5 Bit
Serial Digital Attenuator
Features
• Very Low DC Power Consumption
• Attenuati on In Steps From 1 dB To 31 dB
• Si ngle Or Dual Power Supply V oltages
• Seri al Data Interface
• 50 Ohm Compatible Impedanc e
• Space Sav ing LP CCTM S urfac e Mount P ac k aging
Product Description
The Honeywell HRF-AT4521 is a 5-bit digital
attenuator that is ideal for use in broadband
communication system applications that require
accuracy, speed and low power consumption. The
HRF-AT4521 is manufactured with Honeywell's
patented Silicon On Insulator (SOI) CMOS
manufacturing technology, which provides the
performance of GaAs with the economy and
integration capabiliti es of c onv entional CMOS.
RF Electrical Specifications @ + 25oC
Parameter Test Condition Frequency Minimum Typical Maximum Units
Insert i on Loss DC – 0.5 GHz
2.0 GHz
3.0 GHz
4.0 GHz
1.8
2.8
--
--
dB
dB
dB
dB
1dB Compression VSS = 0V, Input Power DC – 2.0 GHz
24 dBm
1dB Compression VSS = - VDD, Input Power DC – 2.0 GHz
29 dBm
Input IP3 VSS = 0V Two-tone inputs
Up To +5 dBm @ 0 dBm
Attenuation
DC – 2.0 GHz
38 dBm
Input IP3 Vss = - VDD
T wo-t on e in puts U p T o + 5
dBm @ 0 dBm Attenuation
DC – 2.0 GHz
>38 dBm
Return Loss* Any Combination o f Bits DC - 4.0 GHz 11 dB
Attenuation Accuracy All attenuation state s
All att en uation st ates
All att en uation st ates
All att en uation st ates
DC – 1.0 GHz
2.0 GHz
3.0 GHz
4.0 GHz
+/-(0.3 + 3% of programm ed I L)
+/-(0.3 + 3% of programm ed I L)
+/-(0.4 + 4% of programm ed I L)
+/-( 0. 5 + 6% of program m ed IL)
dB
dB
dB
dB
Trise, Tfall*
Ton, Toff (Tpd)
Transients
10% To 90%
50% Cntl To 90%/10%RF
In-Band
TBD
nS
nS
mV
T clock Period (Tprd)* T high / T low = ½ minimum clock period 50 nS
T data set up (Tsup)* Set up to rising edge of clock 5 nS
T data hold (Thld)* Data hold after rising edge of clock 2 nS
T latch set up (Tlsup)* Data set up to falling edge of OE 5 nS
0.01uF Deco upling Capacitors Required On Power S upply Rail s .
*B y desi gn
HRF-AT4521 in LPCC™ Package