MAX1085AESA+ - Hytronics - Datasheet.Live

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX1084/MAX1085 10-bit analog-to-digital convert-

ers (ADCs) combine a high-bandwidth track/hold, a serial

interface with high conversion speed, an internal +2.5V

reference, and low power consumption. The MAX1084

operates from a single +4.5V to +5.5V supply; the

MAX1085 operates from a single +2.7V to +3.6V supply.

The 3-wire serial interface connects directly to

SPI™/QSPI™/MICROWIRE™ devices without external

logic. The devices use an external serial-interface clock to

perform successive-approximation analog-to-digital con-

versions.

Low power combined with ease of use and small pack-

age size make these converters ideal for remote-sensor

and data-acquisition applications, or for other circuits with

demanding power consumption and space requirements.

The MAX1084/MAX1085 are available in 8-pin SO

packages.

These devices are pin-compatible, higher-speed versions

of the MAX1242/MAX1243; for more information, refer to

the respective data sheets.

Applications

Portable Data Logging

Data Acquisition

Medical Instruments

Battery-Powered Instruments

Pen Digitizers

Process Control

Features

♦Single-Supply Operation

+4.5V to +5.5V (MAX1084)

+2.7V to +3.6V (MAX1085)

♦10-Bit Resolution

♦400ksps Sampling Rate (MAX1084)

♦Internal Track/Hold

♦Internal +2.5V Reference

♦Low Power: 2.5mA (400ksps)

♦SPI/QSPI/MICROWIRE 3-Wire Serial Interface

♦Pin-Compatible, High-Speed Upgrade to

MAX1242/MAX1243

♦8-Pin SO Package

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

19-1686; Rev 1; 12/10

PART

MAX1084ACSA+

MAX1084BCSA+

MAX1084AESA+ -40°C to +85°C

0°C to +70°C

TEMP

RANGE

PIN-

PACKAGE

8 SO

Pin Configuration

Ordering Information

INL

(LSB)

±1/2

±1

±1/2

MAX1084BESA+

MAX1085ACSA+

MAX1085BCSA+ 0°C to +70°C

0°C to +70°C

-40°C to +85°C 8 SO

8 SO

±1

±1/2

±1

MAX1085AESA+

MAX1085BESA+ -40°C to +85°C

-40°C to +85°C 8 SO

8 SO

±1/2

±1

AIN T/H

DOUT

OUTPUT

SHIFT

CONTROL

LOGIC

2.5V

REFERENCE

INT

CLOCK

10-BIT

SAR

REF 4

SHDN

SCLK

MAX1084

MAX1085

VDD

GND

Functional Diagram

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

TOP VIEW

SCLK

DOUT

GND

REF

SHDN

AIN

VDD

MAX1084

MAX1085

+Denotes a lead(Pb)-free/RoHS-compliant package.

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS—MAX1084

(VDD = +4.5V to +5.5V, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to GND .............................................................-0.3V to +6V

AIN to GND................................................-0.3V to (VDD + 0.3V)

REF to GND ...............................................-0.3V to (VDD + 0.3V)

Digital Inputs to GND...............................................-0.3V to +6V

DOUT to GND............................................-0.3V to (VDD + 0.3V)

DOUT Current..................................................................±25mA

Continuous Power Dissipation (TA = +70°C)

8-Pin SO (derate 5.88mW/°C above +70°C) ..............471mW

Operating Temperature Ranges

MAX1084_CSA/MAX1085_CSA.........................0°C to +70°C

MAX1084_ESA/MAX1085_ESA ......................-40°C to +85°C

Storage Temperature Range............................-60°C to +150°C

Lead Temperature (soldering, 10s)................................+300°C

Soldering Temperature (reflow)......................................+260°C

MAX1084A

SINAD > 58dB

-3dB point

Up to the 5th harmonic

fIN1 = 99kHz, fIN2 =102kHz

MAX1084B

No missing codes over temperature

CONDITIONS

%40 60Duty Cycle

MHz0.5 6.4fSCLK

Serial Clock Frequency

ps< 50Aperture Jitter

ns10Aperture Delay

ns468tACQ

Track/Hold Acquisition Time

µs2.5tCONV

Conversion Time (Note 4)

kHz350Full-Linear Bandwidth

MHz6Full-Power Bandwidth

dB76IMDIntermodulation Distortion

dB70SFDRSpurious-Free Dynamic Range

LSB

±0.5

INLRelative Accuracy (Note 2)

Bits10Resolution

dB-70THDTotal Harmonic Distortion

dB60SINAD

Signal-to-Noise Plus Distortion

Ratio

ppm/°C ±0.8

Gain-Error Temperature

Coefficient

±1.0

LSB±1.0DNLDifferential Nonlinearity

LSB±4.0Offset Error

LSB±3.0Gain Error (Note 3)

UNITSMIN TYP MAXSYMBOLPARAMETER

pF18Input Capacitance

V0 2.5VAIN

Input Voltage Range

DC ACCURACY (Note 1)

DYNAMIC SPECIFICATIONS (100kHz sine wave, 2.5VP-P, clock = 6.4MHz)

CONVERSION RATE

ANALOG INPUT (AIN)

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS—MAX1084 (continued)

(VDD = +4.5V to +5.5V, fSCLK = 6.4MHz, 50% duty cycle, 16 clocks/conversion cycle (400ksps), 4.7µF capacitor at REF, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER

VCS = 5V

ISOURCE = 1mA

ISINK = 5mA

VIN = 0V or VDD

0 to 1.0mA output load

TA= +25°C

V4.5 5.5VDD

Positive Supply Voltage (Note 6)

pF15COUT

Three-State Output Capacitance

µA±10IL

Three-State Leakage Current

V4VOH

Output Voltage High

V0.4VOL

Output Voltage Low

pF15CIN

Input Capacitance

µA±1IIN

Input Leakage

V0.2VHYST

Input Hysteresis

V0.8VINL

Input Low Voltage

V3.0VINH

Input High Voltage

µF4.7 10Capacitive Bypass at REF

mV/mA0.1 2.0Load Regulation (Note 5)

V2.48 2.50 2.52VREF

REF Output Voltage

mA30REF Short-Circuit Current

ppm/°C±15TC VREF

REF Output Tempco

VDD = 5V ±10%, midscale input

SCLK = VDD, SHDN = GND

VDD = 5.5V

mV±0.5 ±2.0PSRPower-Supply Rejection

µA210ISHDN

Shutdown Supply Current

mA2.5 4.0IDD

Positive Supply Current (Note 7)

ELECTRICAL CHARACTERISTICS—MAX1085

(VDD = +2.7V to +3.6V, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

MAX1085A

MAX1085B

No missing codes over temperature

CONDITIONS

LSB

±0.5

INLRelative Accuracy (Note 2)

Bits

Resolution

ppm/°C

±1.6

Gain-Error Temperature

Coefficient

LSB

±3.0

Gain Error (Note 3)

±1.0

LSB

±1.0

DNLDifferential Nonlinearity

LSB

±3.0

Offset Error

UNITSMIN TYP MAXSYMBOLPARAMETER

DC ACCURACY (Note 1)

INTERNAL REFERENCE

DIGITAL INPUTS (SCLK, CS, SHDN)

DIGITAL OUTPUT (DOUT)

POWER SUPPLY

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS—MAX1085 (continued)

(VDD = +2.7V to +3.6V, fSCLK = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), 4.7µF capacitor at REF, TA= TMIN to

TMAX, unless otherwise noted. Typical values are at TA= +25°C.)

SINAD > 58dB

-3dB point

fIN1 = 99kHz, fIN2 =102kHz

Up to the 5th harmonic

CONDITIONS

< 50

Aperture Jitter

Aperture Delay

625

tACQ

Track/Hold Acquisition Time

µs

3.3

tCONV

Conversion Time (Note 4)

kHz

250

Full-Linear Bandwidth

MHz

Full-Power Bandwidth

IMDIntermodulation Distortion

SFDRSpurious-Free Dynamic Range

-70

THDTotal Harmonic Distortion

SINAD

Signal-to-Noise Plus Distortion

Ratio

UNITSMIN TYP MAXSYMBOLPARAMETER

ISINK = 5mA

VIN = 0V or VDD

TA= +25°C

0 to 0.75mA output load

0.4

VOL

Output Voltage Low

CIN

Input Capacitance

µA

±1

IIN

Input Leakage

0.2

VHYST

Input Hysteresis

0.8

VINL

Input Low Voltage

2.0

VINH

Input High Voltage

µF

4.7 10

Capacitive Bypass at REF

mV/mA

0.1 2.0

Load Regulation (Note 5)

ppm/°C

±15

TC VREF

REF Output Tempco

40 60

MHz

0.5 4.8

fSCLK

Serial Clock Frequency

Duty Cycle

REF Short Circuit Current

2.48 2.50 2.52

VREF

REF Output Voltage

0 2.5

VAIN

Input Voltage Range

CIN

Input Capacitance

VCS = 3V

ISOURCE = 0.5mA

COUT

Three-State Output Capacitance

µA

±10

Three-State Leakage Current

VDD - 0.5V

VOH

Output Voltage High

2.7 3.6

VDD

Positive Supply Voltage (Note 6)

VDD = 3.6V mA

2.5 3.5

IDD

Positive Supply Current (Note 7)

SCLK = VDD, SHDN = GND µA

210

ISHDN

Shutdown Supply Current

VDD = 2.7V to 3.6V, midscale input mV

±0.5 ±2.0

PSRPower-Supply Rejection

DYNAMIC SPECIFICATIONS (75kHz sinewave, 2.5VP-P, fSAMPLE = 300ksps, fSCLK = 4.8MHz)

CONVERSION RATE

INTERNAL REFERENCE

DIGITAL INPUTS (SCLK,CS, SHDN)

DIGITAL OUTPUTS (DOUT)

ANALOG INPUT

POWER SUPPLY

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 5

TIMING CHARACTERISTICS—MAX1084

(Figures 1, 2, 8, 9; VDD = +4.5V to +5.5V, TA= TMIN to TMAX, unless otherwise noted.)

TIMING CHARACTERISTICS—MAX1085

(Figures 1, 2, 8, 9; VDD = +2.7V to +3.6V, TA= TMIN to TMAX, unless otherwise noted.)

CLOAD = 20pF

CONDITIONS

100

tCSW

CS Pulse-Width High

tCL

SCLK Pulse-Width Low

tCH

156

tCP

SCLK Period

SCLK Pulse-Width High

tDOE

CS Fall to DOUT Enable

10 65

tDOD

CS Rise to DOUT Disable

tDOV

SCLK Rise to DOUT Valid

tDOH

SCLK Rise to DOUT Hold

tCSS

CS Fall to SCLK Rise Setup

tCSH

SCLK Rise to CS Rise Hold

tCSO

SCLK Rise to CS Fall Ignore

tCS1

CS Rise to SCLK Rise Ignore

UNITSMIN TYP MAXSYMBOLPARAMETER

CLOAD = 20pF

CONDITIONS

tCL

SCLK Pulse-Width Low

tCH

208

tCP

SCLK Period

SCLK Pulse-Width High

13 85

tDOD

CS Rise to DOUT Disable

100

tDOV

SCLK Rise to DOUT Valid

tDOH

SCLK Rise to DOUT Hold

tCSS

CS Fall to SCLK Rise Setup

tCSH

SCLK Rise to CS Rise Hold

tCSO

SCLK Rise to CS Fall Ignore

tCS1

CS Rise to SCLK Rise Ignore

UNITSMIN TYP MAXSYMBOLPARAMETER

Note 1: Tested at VDD = VDD,MIN.

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: Internal reference, offset, and reference errors nulled.

Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 5: External load should not change during conversion for specified accuracy. Guaranteed specification limit of 2mV/mA due to

production test limitation.

Note 6: Electrical characteristics are guaranteed from VDD,MIN to VDD,MAX. For operations beyond this range, see Typical Operating

Characteristics.

Note 7: MAX1084 tested with 20pF on DOUT and fSCLK = 6.4MHz, 0 to 5V. MAX1085 tested with same loads, fSCLK = 4.8MHz, 0 to

3V. DOUT = full scale.

CLOAD = 20pF ns

tDOE

CS Fall to DOUT Enable

CLOAD = 20pF ns

100

tCSW

CS Pulse-Width High

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

6 _______________________________________________________________________________________

-0.10

-0.04

-0.06

-0.08

-0.02

0.02

0.04

0.06

0.08

0.10

0 400200 600 800 1000 1200

INTEGRAL NONLINEARLITY

vs. DIGITAL OUTPUT CODE

MAX1084/5toc01

DIGITAL OUTPUT CODE

INL (LSB)

-0.15

-0.05

-0.10

0.05

0.10

0.15

0 400 600200 800 1000 1200

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1084/5toc02

DIGITAL OUTPUT CODE

DNL (LSB)

-0.25

0.25

0.50

2.5 4.0 4.53.0 3.5 5.0 5.5 6.0

OFFSET ERROR vs. SUPPLY VOLTAGE

MAX1084/5 toc03

VDD (V)

OFFSET ERROR (LSB)

0.10

0.05

0.25

0.20

0.15

0.40

0.35

0.30

0.45

-40 0 20-20 406080100

OFFSET ERROR vs. TEMPERATURE

MAX104/5 toc04

TEMPERATURE (°C)

OFFSET ERROR (LSB)

-0.25

-0.10

-0.15

-0.20

-0.05

0.05

0.10

0.15

0.20

0.25

2.5 3.53.0 4.0 4.5 5.0 5.5

GAIN ERROR vs. SUPPLY VOLTAGE

MAX1084/5 toc05

VDD (V)

GAIN ERROR (LSB)

-0.50

-0.25

0.25

-40 0 20-20 406080100

GAIN ERROR vs. TEMPERATURE

MAX1084/5 toc06

TEMPERATURE (°C)

GAIN ERROR (LSB)

Typical Operating Characteristics

(MAX1084: VDD = +5.0V, fSCLK = 6.4MHz; MAX1055: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,

TA = +25°C, unless otherwise noted.)

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 7

2.490

2.496

2.494

2.492

2.498

2.500

2.502

2.504

2.506

2.508

2.510

2.5 3.53.0 4.0 4.5 5.0 5.5

INTERNAL REFERENCE VOLTAGE

vs. SUPPLY VOLTAGE

MAX1084/5 toc07

SUPPLY VOLTAGE (V)

VREF (V)

2.490

2.496

2.494

2.492

2.500

2.498

2.508

2.506

2.504

2.502

2.510

-40-200 20406080100

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1084/5 toc08

TEMPERATURE (°C)

VREF (V)

1.50

2.00

1.75

2.50

2.25

2.75

3.00

2.5 3.5 4.03.0 4.5 5.0 5.5

SUPPLY CURRENT vs. SUPPLY VOLTAGE

MAX1084/5 toc09

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

CONVERTING,

SCLK = 6.4MHz

CONVERTING,

SCLK = 4.8MHz

STATIC

CODE = 1111 1111 1111

RL = ∞

CL = 10pF

1.5

1.8

2.4

2.1

2.7

3.0

-40 0-20 20406080100

SUPPLY CURRENT vs. TEMPERATURE

MAX1084/5 toc10

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

VDD = 5V, CONVERTING

VDD = 3V, CONVERTING

VDD = 5V, STATIC VDD = 3V, STATIC

Typical Operating Characteristics (continued)

(MAX1084: VDD = +5.0V, fSCLK = 6.4MHz; MAX1085: VDD = +3.0V, fSCLK = 4.8MHz; CLOAD = 20pF, 4.7µF capacitor at REF,

TA= +25°C, unless otherwise noted.)

Pin Description

Serial-Clock Input. SCLK drives the conversion process and clocks data out at rates up to 6.4MHz

(MAX1084) or 4.8MHz (MAX1085).

Positive Supply VoltageVDD

FUNCTIONNAME

Sampling Analog Input, 0 to VREF RangeAIN2

Analog and Digital GroundGND5

Active-Low Chip Select. Initiates conversions on the falling edge. When CS is high, DOUT is high

impedance.

Reference Voltage for Analog-to-Digital Conversion. Internal 2.5V reference output. Bypass with a

4.7µF capacitor.

REF4

Active-Low Shutdown Input. Pulling SHDN low shuts down the device and reduces the supply current

to 2µA (typ).

SHDN

SCLK8

Serial-Data Output. DOUT changes state at SCLK’s rising edge. High impedance when CS is high.

DOUT6

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

8 _______________________________________________________________________________________

_______________Detailed Description

Converter Operation

The MAX1084/MAX1085 use an input track/hold (T/H)

and successive-approximation register (SAR) circuitry to

convert an analog input signal to a digital 10-bit output.

Figure 3 shows the MAX1084/MAX1085 in their simplest

configuration. The internal reference is trimmed to 2.5V.

The serial interface requires only three digital lines

(SCLK,

CS,

and DOUT) and provides an easy interface to

microprocessors (µPs).

The MAX1084/MAX1085 have two modes: normal and

shutdown. Pulling

SHDN

low shuts the device down and

reduces supply current to 2µA (typ); pulling

SHDN

high

puts the device into operational mode. Pulling CS low ini-

tiates a conversion that is driven by SCLK. The conver-

sion result is available at DOUT in unipolar serial format.

The serial data stream consists of three zeros, followed

by the data bits (MSB first). All transitions on DOUT

occur 20ns after the rising edge of SCLK. Figures 8 and

9 show the interface timing information.

Analog Input

Figure 4 shows the sampling architecture of the ADC’s

comparator. The full-scale input voltage is set by the

internal reference (VREF = +2.5V).

Track/Hold

In track mode, the analog signal is acquired and stored

in the internal hold capacitor. In hold mode, the T/H

switch opens and maintains a constant input to the

ADC’s SAR section.

During acquisition, the analog input AIN charges

capacitor CHOLD. Bringing

low ends the acquisition

interval. At this instant, the T/H switches the input side

of CHOLD to GND. The retained charge on CHOLD repre-

sents a sample of the input, unbalancing node ZERO at

the comparator’s input.

In hold mode, the capacitive digital-to-analog converter

(DAC) adjusts during the remainder of the conversion

cycle to restore node ZERO to 0 within the limits of 10-

bit resolution. This action is equivalent to transferring a

charge from CHOLD to the binary-weighted capacitive

DOUT DOUT

6kΩ

DGND

CLOAD = 20pF CLOAD = 20pF

6kΩ

DGND

VDD

b) HIGH-Z TO VOL AND VOH TO VOL

a) HIGH-Z TO VOH AND VOL TO VOH

DOUT DOUT

6kΩ

DGND

CLOAD = 20pF CLOAD = 20pF

6kΩ

DGND

VDD

b) VOLTO HIGH-Za) VOH TO HIGH-Z

Figure 1. Load Circuits for DOUT Enable Time

Figure 2. Load Circuits for DOUT Disable Time

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

_______________________________________________________________________________________ 9

DAC, which in turn forms a digital representation of the

analog input signal. At the conversion’s end, the input

side of CHOLD switches back to AIN, and CHOLD

charges to the input signal again.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

allowed between conversions. The acquisition time,

tACQ, is the maximum time the device takes to acquire

the signal and the minimum time needed for the signal

to be acquired. Acquisition time is calculated by:

tACQ = 7(RS+ RIN) ✕12pF

where RIN = 800Ω, RS= the input signal’s source

impedance, and tACQ is never less than 468ns

(MAX1284) or 625ns (MAX1085). Source impedance

below 4kΩdoes not significantly affect the ADC’s AC

performance.

Higher source impedances can be used if a 0.01µF

capacitor is connected to the analog input. Note that

the input capacitor forms an RC filter with the input

source impedance, limiting the ADC’s input signal

bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 6MHz

(MAX1084) or 3MHz (MAX1085) small-signal band-

width, so it is possible to digitize high-speed transient

events and measure periodic signals with bandwidths

exceeding the ADC’s sampling rate by using under-

sampling techniques. To avoid aliasing of unwanted

high-frequency signals into the frequency band of inter-

est, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog

input to VDD and GND, allow the input to swing from

(GND - 0.3V) to (VDD + 0.3V) without damage.

If the analog input exceeds 50mV beyond the supplies,

limit the input current to 2mA.

Internal Reference

The MAX1084/MAX1085 have an on-chip voltage refer-

ence trimmed to 2.5V. The internal reference output is

connected to REF and also drives the internal capacitive

DAC. The output can be used as a reference voltage

source for other components and can source up to

800µA. Bypass REF with a 4.7µF capacitor. Larger

capacitors increase wake-up time when exiting shut-

down (see Using

SHDN

to Reduce Supply Current). The

internal reference is disabled in shutdown (SHDN = 0).

Serial Interface

Initialization After Power-Up and

Starting a Conversion

When power is first applied, and if SHDN is not pulled

low, it takes the fully discharged 4.7µF reference

bypass capacitor up to 1.4ms to acquire adequate

charge for specified accuracy. No conversions should

be performed during this time.

CHOLD

12pF

RIN

800Ω

HOLD

CSWITCH*

6pF

*INCLUDES ALL INPUT PARASITICS

AIN

REF

GND

ZERO

AUTOZERO

RAIL

COMPARATOR

CAPACITIVE DAC

TRACK

SHUTDOWN

INPUT

ANALOG INPUT

0 TO VREF

+3V to +5V

VDD

AIN

SHDN

REF

SCLK

DOUT

GND

SERIAL

INTERFACE

4.7µF

10µF0.1µF

MAX1084

MAX1085

Figure 3. Typical Operating Circuit

Figure 4. Equivalent Input Circuit

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

10 ______________________________________________________________________________________

To start a conversion, pull

low. At

CS’s

falling edge,

the T/H enters its hold mode and a conversion is initiat-

ed. Data can then be shifted out serially with the exter-

nal clock.

Using

SSHHDDNN

to Reduce Supply Current

Power consumption can be reduced significantly by

shutting down the MAX1084/MAX1085 between conver-

sions. Figure 6 shows a plot of average supply current

vs. conversion rate. The wake-up time, tWAKE, is the

time from SHDN deasserted to the time when a conver-

sion may be initiated (Figure 5).This time depends on

the time in shutdown (Figure 7) because the external

4.7µF reference bypass capacitor loses charge slowly

during shutdown and can be as long as 1.4ms.

Timing and Control

Conversion-start and data-read operations are con-

trolled by the

and SCLK digital inputs. The timing

diagrams of Figures 8 and 9 outline serial-interface

operation.

falling edge initiates a conversion sequence: the

T/H stage holds the input voltage, the ADC begins to

convert, and DOUT changes from high impedance to

logic low. SCLK is used to drive the conversion

process, and it shifts data out as each bit of conversion

is determined.

SCLK begins shifting out the data after the rising edge

of the third SCLK pulse. DOUT transitions 20ns after

each SCLK rising edge. The third rising clock edge

produces the MSB of the conversion at DOUT, followed

by the remaining bits. Since there are 12 data bits and

3 leading zeros, at least 15 rising clock edges are

needed to shift out these bits. Extra clock pulses occur-

ring after the conversion result has been clocked out,

and prior to a rising edge of

, produce trailing zeros

at DOUT and have no effect on converter operation.

Pull

high after reading the conversion’s LSB. For

maximum throughput,

can be pulled low again to ini-

tiate the next conversion immediately after the specified

minimum time (tCS).

Output Coding and Transfer Function

The data output from the MAX1084/MAX1085 is binary.

Figure 10 depicts the nominal transfer function. Code

transitions occur halfway between successive-integer LSB

values; VREF = 2.5V, and 1LSB = 2.44mV or 2.5V/1024.

Applications Information

Connection to Standard Interfaces

The MAX1084/MAX1085 serial interface is fully compat-

ible with SPI, QSPI, and MICROWIRE (Figure 11).

If a serial interface is available, set the CPU’s serial

interface in master mode so the CPU generates the ser-

ial clock. Choose a clock frequency up to 6.4MHz

(MAX1084) or 4.8MHz (MAX1085).

1) Use a general-purpose I/O line on the CPU to pull

low. Keep SCLK low.

2) Activate SCLK for a minimum of 13 clock cycles. The

first two clocks produce zeros at DOUT. DOUT output

data transitions 20ns after SCLK rising edge and is

available in MSB-first format. Observe the SCLK-to-

DOUT valid timing characteristic. Data can be clocked

into the µP on SCLK’s falling or rising edge.

COMPLETE CONVERSION SEQUENCE

tWAKE

POWERED UPPOWERED DOWNPOWERED UP

CONVERSION 0 CONVERSION 1

DOUT

SHDN

Figure 5. Shutdown Sequence

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 11

Figure 6. Supply Current vs. Conversion Rate

10,000

1000

0.1 0.1 1 10 100 1k 10k 100k

100

CONVERSION RATE (SAMPLES)

SUPPLY CURRENT (µA)

VDD = 3.0V

DOUT = FS

RL = ∞

CL = 10pF

SUPPLY CURRENT

vs. CONVERSION RATE

Figure 7. Reference Power-Up vs. Time in Shutdown

0.50

0.25

1.00

0.75

1.25

1.50

0.0001 0.010.001 0.1 1 10

TIME IN SHUTDOWN (s)

REFERENCE POWER-UP DELAY (ms)

CREF = 4.7µF

A/D STATE

DOUT HIGH-Z HIGH-Z

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0

SCLK

143 8 12 15

ACQ

HOLD/CONVERT ACQUISITION

Figure 8. Interface Timing Sequence

SCLK

DOUT

tDOE

tDOH

tDOD

tDOV

tCSO tCSS tCSI

tCSO tCSH

tCH

tCL

tCP

tCSW

Figure 9. Detailed Serial-Interface Timing

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

12 ______________________________________________________________________________________

3) Pull

high at or after the 13th rising clock edge. If

remains low, the two sub-bits and trailing zeros

are clocked out after the LSB.

4) With

= high, wait the minimum specified time, tCS,

before initiating a new conversion by pulling

low.

If a conversion is aborted by pulling

high before

the conversion completes, wait the minimum acquisi-

tion time, tACQ, before starting a new conversion.

must be held low until all data bits are clocked out.

Data can be output in 2 bytes or continuously, as shown

in Figure 8. The bytes contain the result of the conversion

padded with three leading zeros, 2 sub-bits, and trailing

zeros if SCLK is still active with CS kept low.

SPI and Microwire

When using SPI or QSPI, set CPOL = 0 and CPHA = 0.

Conversion begins with a

falling edge. DOUT goes

low, indicating a conversion is in progress. Two con-

secutive 1-byte reads are required to get the full 10+2

bits from the ADC. DOUT output data transitions on

SCLK’s rising edge and is clocked into the µP on the

following rising edge.

The first byte contains 3 leading zeros, and 5 bits of

conversion result. The second byte contains the remain-

ing 5 bits, 2 sub-bits, and 1 trailing zero. See Figure 11

for connections and Figure 12 for timing.

QSPI

Unlike SPI, which requires two 1-byte reads to acquire

the 10 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1084/MAX1085 require 13 clock cycles

from the µP to clock out the 10 bits of data. Additional

clock cycles clock out the 2 sub-bits followed by trailing

zeros. Figure 13 shows a transfer using CPOL = 0 and

CPHA = 1. The result of conversion contains two zeros

followed by the 10 bits of data in MSB-first format.

Layout and Grounding

For best performance, use PC boards. Wire-wrap

boards are not recommended. Board layout should

ensure that digital and analog signal lines are separat-

ed from each other. Do not run analog and digital

(especially clock) lines parallel to one another, or digital

lines underneath the ADC package.

11…111

11…110

11…101

00…011

00…010

00…001

00…000

012 FS

OUTPUT CODE

FS - 3/2LSBINPUT VOLTAGE (LSB)

1LSB = VREF

1024

FS = VREF

FULL-SCALE

TRANSITION

Figure 10. Unipolar Transfer Function, Full Scale (FS) = VREF,

Zero Scale (ZS) = GND

SCLK

DOUT

I/O

SCK

MISO

+3V OR +5V

a) SPI

SCLK

DOUT

SCK

MISO

+3V OR +5V

b) QSPI

MAX1084

MAX1085

MAX1084

MAX1085

MAX1084

MAX1085

SCLK

DOUT

I/O

c) MICROWIRE

Figure 11. Common Serial-Interface Connections to the

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 13

Figure 14 shows the recommended system ground con-

nections. Establish a single-point analog ground (“star”

ground point) at GND, separate from the logic ground.

Connect all other analog grounds and GND to this star

ground point for further noise reduction. No other digital

system ground should be connected to this single-point

analog ground. The ground return to the power supply for

this ground should be low impedance and as short as

possible for noise-free operation.

High-frequency noise in the VDD power supply may affect

the ADC’s high-speed comparator. Bypass this supply to

the single-point analog ground with 0.1µF and 10µF

bypass capacitors. Minimize capacitor lead lengths for

best supply-noise rejection. To reduce the effect of sup-

ply noise, a 10Ωresistor can be connected as a lowpass

filter to attenuate supply noise (Figure 14).

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the endpoints of the transfer function,

once offset and gain errors have been nullified. The

static linearity parameters for the MAX1084/MAX1085

are measured using the endpoints method.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of 1LSB or less guarantees no

missing codes and a monotonic transfer function.

Aperture Jitter

Aperture jitter (tAJ) is the sample-to-sample variation in

the time between the samples.

Aperture Delay

Aperture delay (tAD) is the time defined between the

falling edge of CS and the instant when an actual sam-

ple is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The theoretical minimum analog-

to-digital noise is caused by quantization error and

results directly from the ADC’s resolution, (N bits):

SCLK

DOUT

D9 D8 D7 D6 D4 D3 D2 D1 D0 S1

FIRST BYTE READ SECOND BYTE READ

HIGH-Z HIGH-Z

SCLK

DOUT

1412

D9 D8 D7 D6 D2D3D4 D1 D0 S1 S0

HIGH-Z

HIGH-Z D5

Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)

Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

14 ______________________________________________________________________________________

SNR = (6.02 ✕N + 1.76)dB

In reality, there are other noise sources besides quanti-

zation noise, including thermal noise, reference noise,

clock jitter, etc. Therefore, SNR is computed by taking

the ratio of the RMS signal to the RMS noise, which

includes all spectral components minus the fundamen-

tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to RMS

equivalent of all other ADC output signals.

SINAD (dB) = 20 ✕log (SignalRMS/NoiseRMS)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the full-

scale range of the ADC, calculate the effective number

of bits as follows:

ENOB = (SINAD - 1.76)/6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

where V1 is the fundamental amplitude, and V2 through

V5 are the amplitudes of the 2nd- through 5th-order

harmonics, respectively.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest distortion

component.

THD LOG VVVV

=×

+++

20 2

___________________Chip Information

PROCESS: BiCMOS

SUPPLIES

VDD VDD GND

DGND

VDD

DIGITAL

CIRCUITRY

GNDVDD

MAX1084

MAX1085

*OPTIONAL

R* = 10Ω

4.7µF

0.1µF

Figure 14. Power-Supply Grounding Condition

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

______________________________________________________________________________________ 15

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

8 SO S8+5 21-0041 90-0096

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the

package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the

package regardless of RoHS status.

MAX1084/MAX1085

400ksps/300ksps, Single-Supply, Low-Power,

Serial 10-Bit ADCs with Internal Reference

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 5/00 Initial release —

1 12/10 Add lead-free, update Absolute Maximum Ratings, update Figure 10, style updates 1–5, 7–12,

14, 15, 16