1
Data sheet acquired from Harris Semiconductor
SCHS121
Features
Buffered Inputs
Typical Propagation Delay: 10ns at VCC = 5V,
CL = 15pF, TA = 25oC
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating T emperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il1µA at VOL, VOH
Description
The Harris CD74HC30, CD74HCT30, each contain an 8-input
NAND gate in one package. They provide the system
designer with the direct implementation of the positive logic
8-input NAND function. Logic gates utilize silicon gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Pinout
CD54HC30, CD74HC30, CD74HCT30
(PDIP, CERDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP.RANGE
(oC) PACKAGE PKG.
NO.
CD74HC30E -55 to 125 14 Ld PDIP E14.3
CD74HCT30E -55 to 125 14 Ld PDIP E14.3
CD74HC30M -55 to 125 14 Ld SOIC M14.15
CD74HCT30M -55 to 125 14 Ld SOIC M14.15
CD54HCT30H -55 to 125 Die
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
A
B
C
D
E
F
GND
VCC
NC
H
G
NC
NC
Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 1652.1
CD54HC30, CD74HC30,
CD74HCT30
High Speed CMOS Logic
8-Input NAND Gate
[ /Title
(CD54H
C30,
CD74H
C30,
CD74H
CT30)
/
Subject
(High
Speed
CMOS
Logic 8-
August 1997
2
Functional Diagram
Logic Symbol
TRUTH TABLE
INPUTS
OUTPUTABCDEFGH
LXXXXXXX H
XLXXXXXX H
XXLXXXXX H
XXXLXXXX H
XXXXLXXX H
XXXXXLXX H
XXXXXXLX H
XXXXXXXL H
HHHHHHHH L
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant
1
2
3
4
5
6
11
12
A
B
C
D
E
F
G
H
8Y
Y = ABCDEFGH
8Y
A
B
C
D
E
F
G
H
1
2
3
4
5
6
11
12
CD54HC30, CD74HC30, CD74HCT30
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A
CERDIP Package . . . . . . . . . . . . . . . . 130 55
SOIC Package. . . . . . . . . . . . . . . . . . . 180 N/A
Maximum Junction Temperature (Hermetic Pac kage or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO +85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
---------V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
---------V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54HC30, CD74HC30, CD74HCT30
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 2 - 20 - 40 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL -0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC
and
GND
- 5.5 - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 2 - 20 - 40 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO +85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
All 0.6
NOTE: Unit Load is ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oCTO125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,Input to
Output (Figure 1) tPLH, tPHL CL= 50pF 2 - - 130 - 165 - 195 ns
4.5 - - 26 - 33 - 39 ns
6 - - 22 - 28 - 33 ns
PropagationDelay,DataInputto
Output Y tPLH, tPHL CL= 15pF 5 - 10 - ----ns
CD54HC30, CD74HC30, CD74HCT30
5
Transition Times (Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI- - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 5, 6) CPD - 5-25-----pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2) tRHL, tPHL CL= 50pF 4.5 - - 28 - 35 - 42 ns
PropagationDelay,DataInputto
Output Y tPLH, tPHL CL= 15pF 5 - 11 - ----ns
Transition Times (Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CI- - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 5, 6) CPD - 5-26-----pF
NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oCTO125
o
C
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54HC30, CD74HC30, CD74HCT30
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