AN32155A
Page 1 of 24
Product Standards
FEATURES DESCRIPTION
AN32155A is a 4 x 3 LED driver equipped with a
step-up charge pump circuit.
4 x 3 LED Matrix Driver
(Total LED that can be driven = 12)
LED maximum current selectable
Step-up charge pump DC/DC converter : 200 mA
I2C interface (Slave address selectable)
24 pin Wafer Level Chip Size Package (WLCSP)
X1~X3
CPOUT
VB
Y1~Y4
Battery
INT
GND
CPGND
SDA
NRST
39 k
SCL
CP1
IREF
4
3
VLDO
1.0 F
CPU I/F
CN1
CP2
CN2
1.0 F
1.0 F
2.2 F
4.7 F
SLASEL
43 Matrix LED Driver LSI with
Step-up Charge Pump Control Circuit
http://www.semicon.panasonic.co.jp/en/
APPLICATIONS
Mobile Phone
Smart Phone
PCs
Game Consoles
Home Appliances etc.
TYPICAL APPLICATION
CLKIO
VDD
Note)
The application circuit is an example. The operation of the mass production set is not guaranteed. Sufficient evaluation and
verification is required in the design of the mass production set. The Customer is fully responsible for the incorporation of the
above illustrated application circuit in the design of the equipment.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 2 of 24
Product Standards
ABSOLUTE MAXIMUM RATINGS
*2C– 30 to + 85Topr
Operating ambience temperature
*2C– 30 to + 125Tj
Operating junction temperature
*2C–55to+125Tstg
Storage temperature
SLASEL, SCL, SDA,
CLKIO, NRST
Input Voltage Range —V– 0.3 to 6.5
CLKIO, VLDO, INT,
Y1, Y2, Y3, Y4,
X1, X2, X3
Output Voltage Range —V– 0.3 to 6.5
—kV2.0HBMESD
*1V6.5CPOUT MAX
*1V6.5VDD MAX
NoteUnitRatingSymbolParameter
*1V6.5VB MAX
Supply voltage
POWER DISSIPATION RATING
Note) For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply
voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not
exceed the allowable value.
CAUTION
Note) This product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating.
This rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated
recommended operating range.
When subjected under the absolute maximum rating for a long time, the reliability of the product may be affected.
*1: VBMAX = VB, VDDMAX = VDD , CPOUTMAX = CPOUT
The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta= 25C.
0.2028 W0.507 W197.29 C /W
24 pin Wafer Level Chip Size Package (WLCSP)
PD(Ta=85 C)PD(Ta=25 C)JA
PACKAGE
Although this LSI has built-in ESD protection circuit, it may still sustain permanent damage if not handled
properly. Therefore, proper ESD precautions are recommended to avoid electrostatic damage to the
MOS gates
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 3 of 24
Product Standards
RECOMMENDED OPERATING CONDITIONS
*3VVDD + 0.3—–0.3SLASEL, SCL, SDA, CLKIO
Input Voltage Range *3VVB + 0.3—–0.3NRST
*3VVDD + 0.3—–0.3CLKIO
Output Voltage Range *3VVB + 0.3—–0.3
VLDO, INT,
Y1, Y2, Y3, Y4,
X1, X2, X3
*1V
6.03.63.1
VB
(CPOUT)
1.85
Typ.
1.7
Min.
*1, 2V
6.0VDD
Supply voltage range
NoteUnitMax.SymbolParameter
Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
Do not apply external currents and voltages to any pin not specifically mentioned.
Voltage values, unless otherwise specified, are with respect to GND. GND is voltage for GND and CPGND.
VDD is voltage for VDD. VB is voltage for VB and VBCP. VLED is voltage for VLED.
*2: VDD voltage must be applied in the range which does not exceed VB voltage.
*3: (VDD + 0.3 ) V must not exceed 6.5 V. (VB + 0.3 ) V must not exceed 6.5 V.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 4 of 24
Product Standards
—mA4.62.3—
VB = 3.1 V
NRST = High
Charge Pump ON,
1.5, 1.2 MHz operation mode
LED = current 0 mA setting
ICC5
—mA2.61.3—
VB = 3.1 V
NRST = High
Charge Pump ON,
1.5, 600 kHz operation mode
LED = current 0 mA setting
ICC4
—mA0.520.26—
VB = 4.6 V
NRST = High
VB through mode
ICPOUT = 0 mA
LED = current 0 mA setting
ICC3
—A6035—
VB = 3.6 V
NRST = High
ICC2
Current consumption (5)
at charge pump 1.5
(1.2 MHz operation)
Current consumption (4)
at charge pump 1.5
(600 kHz operation)
Current consumption (3)
at VB through mode
Current consumption (2)
at OFF mode
—A10—
VB = 3.6 V
NRST = 0V
ICC1
Current consumption (1)
at OFF mode
Current consumption
VB through switch
—2.01.0—
VB = 4.5 V
ICPOUT = – 30 mA
RVBS = (VVB –V
CPOUT) / 30
mA
RVBSResistance at switch ON
SCAN switch
—3.01.6—
CPOUT = 4.5 V
IY1 to IY4 = 20 mA
RSCANResistance at switch ON
—MHz2.882.401.92VB = 3.1 V to 4.6 VFDC1Oscillation frequency
Internal oscillator
Limits
Typ Unit
Max
Note
Min
Condition SymbolParameter
ELECTRICAL CHARACTERISTICS
VB = 3.6 V, VDD = 1.85 V
Note) Ta= 25 C 2 C unless otherwise specified.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 5 of 24
Product Standards
—%5—–5
At 12.8 mA setting
Current error between each
channel and the median of X1 to 3
IMXCH
—A1——
OFF setting
VX1 to VX3 = 4.5 V
IMXOFF = IX1 to IX3
IMXOFF
—A2001000IMAX[2:0] = 011 settingIMXSTEP
*1mA1.051.000.95
At 1 mA setting
VX1 to VX3 = 1 V
IMX2 = IX1 to IX3
IMX2
*1 mA26.7825.5024.22
At 25.50 mA setting
VX1 to VX3 = 1 V
IMX1 = IX1 to IX3
IMX1
Error between channels
Off leak current
Current step
Output current (2)
Output current (1)
Current regulator (matrix)
—V5.75.55.3
Charge pump DC/DC
overvoltage detection
VOV
Overvoltage detection
voltage
Step-up mode switch of charge pump
—V0.400.35—
X1 to 3 pin voltage at the time
when the step-up mode switch of
charge pump changes
VLD1
Step-up mode switch
voltage of charge pump
Minimum voltage at which LED driver can keep constant current value
—V0.350.20—
IMAX[2:0] = 011,
95% LED current value at the time
when X1 to 3 pin voltage is set to
1V.
Minimum value of X1 to 3 pin
voltage
VLD2
Minimum voltage at which
LED driver can keep
constant current value
Overvoltage detection
Limits
Typ Unit
Max
Note
Min
Condition SymbolParameter
Note)*1 : The specified values are the values in case that a recommended component (ERJ2RHD393X) is connected to IREF pin.
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VDD = 1.85 V
Note) Ta= 25 C 2 C unless otherwise specified.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 6 of 24
Product Standards
—V
VB
+ 0.3
—1.5High-level recognition voltageVIH3High-level input voltage range
—V0.6—–0.3Low-level recognition voltageVIL3Low-level input voltage range
—A10—VNRST = 3.6 VIIH3High-level input current
—A10—VNRST = 0 VIIL3Low-level input current
INT
—50——IINT = 5 mA RINTONON resistance
—V
VDD
+ 0.3
—
0.7
VDD
High-level recognition voltage
(at external clock input mode)
VIH2High-level input voltage range
—V
0.3
VDD
—–0.3
Low-level recognition voltage
(at external clock input mode)
VIL2Low-level input voltage range
—M1.60.80.4—RPD2Pin pull-down resistance
—V
VDD
+ 0.3
—
0.8
VDD
ICLKIO = –1mA
(at external clock output mode)
VOH2High-level input voltage
—V
VDD
+ 0.3
—
0.7
VDD
High-level recognition voltageVIH1High-level input voltage range
—V
0.3
VDD
—–0.3Low-level recognition voltageVIL1Low-level input voltage range
—A10—VSLASEL = 3.6 VIIH1High-level input current
CLKIO
—A10—VSLASEL = 0 VIIL1Low-level input current
NRST
—V
0.2
VDD
—–0.3
ICLKIO = 1mA
(at external clock output mode)
VOL2Low-level input voltage
SLASEL
Limits
Typ Unit
Max
Note
Min
Condition SymbolParameter
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VDD = 1.85 V
Note) Ta= 25 C 2 C unless otherwise specified.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 7 of 24
Product Standards
*4
*5
pF10——CiCapacitance for each I/O pin
*4
*5
ns500—Tsp
Pulse width of spikes which
must be suppressed by the
input filter
*4
*5
ns250
20 +
0.1Cb
Bus capacitance : 10 pF to
400pF
IP6mA(V
OLmax = 0.6 V)
IP: Max. sink current
Tof
Output fall time from VIHmin to
VILmax
*4
*5
V
0.1
VDD
Hysteresis of SDA, SCL
VDD < 2 V
Vhys2
Hysteresis of Schmitt trigger
input 2
*4
*5
V
0.05
VDD
Hysteresis of SDA, SCL
VDD > 2 V
Vhys1
Hysteresis of Schmitt trigger
input 1
I2C bus (Internal I/O stage characteristics)
—kHz400———fSCL
—A100–10VSCL,VSDA = 0.17 V ~ 2.88 VIi
SCL clock frequency
Input current each I/O pin
*3V
0.3
VDD
——
Voltage which recognized
that SDA and SCL are High-
level
VIL4High-level input voltage
*2,3V
VDD +
0.5,
6.0
—
0.7
VDD
Voltage which recognized
that SDA and SCL are Low-
level
VIH4Low-level input voltage
—V
0.2
VDD
—0
VDD < 2 V
ISDA = 3 mA
VOL42Low-level output voltage 2
—V0.4—0
VDD > 2 V
ISDA = 3 mA
VOL41Low-level output voltage 1
I2C bus (Internal I/O stage characteristics)
Limits
Typ Unit
Max
Note
Min
Condition SymbolParameter
Note) *2 : The maximum value of High-level input voltage range is the voltage which is the lower of (VDD + 0.5 V) or 6.0 V.
*3 : The input threshold voltage of I2C bus (Vth) is linked to VDD (I2C bus I/O stage supply voltage).
In case the pull-up voltage is not VDD, the threshold voltage (Vth) is fixed to ((VDD / 2) (Schmitt width) / 2 ) and
High-level, Low-level of input voltage are not specified. In this case, pay attention to Low-level (max.) value (VILMAX). It
is recommended that the pull-up voltage of I2C bus is set to the I2C bus I/O stage supply voltage (VDD).
*4 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page.19. All values referred to VIHMIN and VILMAX level.
*5 : These are values checked by design but not production tested.
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VDD = 1.85 V
Note) Ta= 25 C 2 C unless otherwise specified.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 8 of 24
Product Standards
*4
*5
s0.6tSU:STA
Set-up time for a repeat START
condition
*4
*5
s0.6tHIGH
High period of the SCL clock
*4
*5
s1.3tLOW
Low period of the SCL clock
*4
*5
ns300
20 +
0.1Cb
tr
Rise time of both SDA and SCL
signals
*4
*5
ns100tSU:DAT
Data set-up time
*4
*5
s0tHD:DAT
Data hold time
*4
*5
s1.3tBUF
Bus free time between STOP
and START condition
*4
*5
s0.6tSU:STO
Set-up time of STOP condition
*4
*5
ns300
20 +
0.1Cb
tf
Fall time of both SDA and SCL
signals
*4
*5
s0.9—tVD:ACK
Data valid acknowledge
*4
*5
s0.9—tVD:DAT
Data valid time
*4
*5
pF400Cb
Capacitive load for each bus line
I2C bus (Bus line specifications)
*4
*5
V
0.1
VDD
VaL
Noise margin at the Low-level for
each connected device
*4
*5
s0.6
The first clock pulse is
generated after tHD:STA.
tHD:STA
Hold time
(repeated) START condition
*4
*5
V
0.2
VDD
VaH
Noise margin at the High-level
for each connected device
Limits
Typ Unit
Max
Note
Min
Condition SymbolParameter
Note) *4 : The timing of Fast-mode Plus devices in I2C-bus is specified in Page.19. All values referred to VIHMIN and VILMAX level.
*5 : These are values checked by design but not production tested.
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VDD = 1.85 V
Note) Ta= 25 C 2 C unless otherwise specified.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 9 of 24
Product Standards
ELECTRICAL CHARACTERISTICS (continued)
VB = 3.6 V, VDD = 1.85 V
Note) Ta= 25 C 2 C unless otherwise specified.
S : START condition
Sr : Repeat START condition
P : STOP condition
tftr
tf
70 %
30 %
SDA
SCL
tHD;STA
70 %
30 %
70 %
30 %
S1 / fSCL
1st clock cycle
tHD;DAT
tSU;DAT
70 %
30 %
70 %
30 %
tr
tLOW
70 %
30 %
tHIGH
tVD;DAT
●●●
cont.
9th clock
●●●
cont.
tHD;STA
Sr
tSP
70 %
30 %
tSU;STO
VILMAX = 0.3 VDD
VIHMIN = 0.7 VDD
tSU;STA
9th clock
tVD;ACK
tBUF
P S
SDA
SCL
●●●
●●●
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 10 of 24
Product Standards
PIN CONFIGURATION
Top View
1 2 3 4 5
E D C B A
CP
OUT
Y4Y3
Y1 CN1
VB
CP1INT
NRST CLK
IO
SDAGND
X3 SLA
SEL
SCLX1
X2 VLDO
CN2
CP
GND
CP2
VDD
IREF
Y2
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 11 of 24
Product Standards
PIN FUNCTIONS
(Must be connected) *1I2C interface clock input pinInputSCLE3(1)
(Must be connected) *1I2C interface data input / output pinInput/OutputSDAD3(2)
(Must be connected) *1I2C interface slave address selection pinInputSLASELD4(3)
(Must be connected) *1Power supply pin for interfaceInputVDDD5(4)
(Must be connected) *1Reset input pinInputNRSTC1(5)
OpenInterrupt output pinOutputINTC2(6)
Open
Clock input/output and LED lighting external
synchronous input pin
Input/OutputCLKIOC4(7)
(Must be connected) *1Ground pinGround
GND
CPGND
D2(8)
A5(22)
Open
Constant current circuit, PWM control output pin
Connected to 1st row of matrix LED
OutputX1E2(9)
Open
Constant current circuit, PWM control output pin
Connected to 2nd row of matrix LED
OutputX2E1(10)
Open
Constant current circuit, PWM control output pin
Connected to 3rd row of matrix LED
OutputX3D1(11)
Open
Control switch pin for matrix driver
Connected to A column of matrix LED
OutputY1B1(12)
Open
Control switch pin for matrix driver
Connected to B column of matrix LED
OutputY2A1(13)
Open
Control switch pin for matrix driver
Connected to C column of matrix LED
OutputY3B2(14)
Open
Control switch pin for matrix driver
Connected to D column of matrix LED
OutputY4B3(15)
(Must be connected) *1
Charge pump output pin / Power supply pin for
matrix driver
OutputCPOUTA3(16)
(Must be connected) *1Power supply pinPower supplyVBA4(17)
OpenCapacitor connection pin for charge pumpOutputCP1C3(18)
OpenCapacitor connection pin for charge pumpOutputCN1B4(19)
OpenCapacitor connection pin for charge pumpOutputCP2C5(20)
Open
Capacitor connection pin for charge pumpOutputCN2B5(21)
(Must be connected) *1Resistor connection pin for constant current setupOutputIREFE5(23)
(Must be connected) *1Power supply pin for internal circuitsOutputVLDOE4(24)
Pin processing
at unused
DescriptionType
Pin
name
Pin No.
Note) *1 : This terminal is required pin when using this LSI. This terminal must be connected.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 12 of 24
Product Standards
FUNCTIONAL BLOCK DIAGRAM
Charge
Pump
I2C serial
interface
frame
and brightness
controller
Moving pattern
generator
SCL
Logic
SDA
VLDO CLKIO
IREF
LED
drivers
X3
X2
X1
GND
periodical
scanning selectors
Y4
Y3
Y2
Y1
CPOUT
CPGND
CN2
CP2
CN1
CP1
VB
SLASEL
VDD
NRST
INT
Reference
Generator
&
Voltage
regulators
A4(17)
C3(18)
B4(19)
C5(20)
B5(21)
A5(22)
E5(23)
E4(24)
E3(1)
D3(2)
D4(3)
D5(4)
C1(5)
C2(6)
C4(7)
D2(8)
E2(9)
E1(10)
D1(11)
A3(16)
B3(15)
B2(14)
A1(13)
B1(12)
Note) This block diagram is for explaining functions.
Part of the block diagram may be omitted, or it may be simplified.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 13 of 24
Product Standards
OPERATION
1. Power-on / Power-off sequence control
Serial input is possible
NRST
1 ms or more
NRST
VB
VDD
VDD
VB
1.1 Power ON
3 ms or more
1.2 Power OFF
Note) Even if the power-on timing of VDD is the same as the rising timing of VB, there is no problem unless VDD voltage
exceeds VB voltage.
1 ms or moreSerial input is possible
Note) Even if the power-off timing of VDD is the same as the falling timing of VB, there is no problem unless VDD voltage
exceeds VB voltage.
Doc No.
TA4-EA-05270
Revision.
3
Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 14 of 24
Product Standards
SRESET———————00hSRESETW00h
SEQNUM[1:0]
INTSEL——
SLPINTC3
MSK
SLPINTD1
MSK
SLPINTD2
MSK
SLPINTD3
MSK
CNTINT
MSK
FUNCINT
MSK
VBDET
MSK
SDET
MSK
00hINTMSK2R/W0Fh
SLPINTA1
MSK
SLPINTA3
MSK
SLPINTB2
MSK
SLPINTB3
MSK
SLPINTC1
MSK
SLPINTC3
CLR
SLPINTD1
CLR
SLPINTD2
CLR
SLPINTA1
CLR
SLPINTA3
CLR
SLPINTB2
CLR
SLPINTB3
CLR
SLPINTC1
CLR
SLPINTC3SLPINTD1SLPINTD2
SLPINTA1SLPINTA3SLPINTB2SLPINTB3SLPINTC1
X1CONSTX3CONSTY1CONSTY2CONSTY3CONST
EXTPWMCLKDIRIOEN
MTXONMTXTIME[1:0]
MTX
DETTM
VDETMTX
VDETX1
EN
VDETX2
EN
FCPOFFFCP15ERRSTOPERRCLRERRMSK
CPOFFVBCP15
—INFTIME[2:0]
CPSWOSCEN
CPCLK
SEL15
SLPINTA2
MSK
SLPINTB1
MSK
SLPINTD3
CLR
CNTINT
CLR
FUNCINT
CLR
VBDET
CLR
SLPINTA2
CLR
SLPINTB1
CLR
SLPINTD3CNTINTFUNCINTVBDET
SLPINTA2SLPINTB1
———RSTCNT
X2CONST—
—CTLGAIN[2:0]
MTX
CPMD
VDETX3
EN
———
FVBFCP20
SLPINTC2
CLR
00hINTCLR1W0Ch
SDET00hINT2R0Bh
SLPINTC200hINT1R0Ah
—00hINTSELW09h
Y4CONST00hCONSTW08h
—00hIOCNTW07h
CP20CPERR——
SEQON
CPCLK
SEL20
CPRET
MODE
——
INTMSK1
INTCLR2
MTXON
VDETLED
CNT
STATE
FORCE
STATE
CHANGE
LEDMODE
POWERCNT
Register
Name D0
—00hR/W05h
RETURN
VB
00hR/W04h
—00hR/W01h
SLPINTC2
MSK
00hW0Eh
INFON00hW
W
R/W
R
R/W
—01h03h
02h
Default
Sub
Address
—00h0Dh
IMAX[2:0]60h06h
D5D6D7
Data
D1D2D3D4
Note) Read value of "—"(the blanks) is [0] in the register map.
OPERATION (continued)
2. Register map
Doc No.
TA4-EA-05270
Revision.
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Established
:
2010-08-06
Revised
:
2013-04-01
AN32155A
Page 15 of 24
Product Standards
LSIVER[2:0]——
COUNTC3[1:0]COUNTD1[1:0]COUNTD2[1:0]COUNTD3[1:0]00hCOUNT3R/W1Ah
C1ONC2ONC3ON—D1OND2OND3ON—00hLEDON2R/W11h
A1ONA2ONA3ON—B1ONB2ONB3ON—00hLEDON1R/W10h
COUNTC1[1:0]
COUNTA1[1:0]
ACTC1ACTC3ACTD1ACTD2ACTD3
ACTA1ACTA2ACTA3
FFC1FFC3FFD1FFD2FFD3
FFA1FFA2FFA3
FADEC1FADEC3FADED1FADED2FADED3
FADEA1FADEA2FADEA3
——
COUNTB2[1:0]COUNTB3[1:0]
COUNTA2[1:0]COUNTA3[1:0]
ACTC2—
—ACTB1ACTB2ACTB3
FFC2—
—01hLSIVERR1Bh
COUNTC2[1:0]00hCOUNT2R/W19h
COUNTB1[1:0]00hCOUNT1R/W18h
—FFB1FFB2FFB3
FADEC2—
—FADEB1FADEB2FADEB3
ACT2
ACT1
FF2
FF1
FADE2
FADE1
Register
Name D0
ACTINV00hR/W16h
—00hR/W15h
—00hR/W12h
—00hR/W
R/W
R/W
R/W
—00h14h
13h
Default
Sub
Address
ACTON00h17h
D5D6D7
Data
D1D2D3D4
Note) Read value of "—"(the blanks) is [0] in the register map.
OPERATION (continued)
2. Register map (continued)
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Product Standards
SEQC21SEQC22SEQC23SEQC24————00hSEQC2R/W27h
SEQC11SEQC12SEQC13SEQC14————00hSEQC1R/W26h
SEQB31SEQB32SEQB33SEQB34————00hSEQB3R/W25h
SEQB21SEQB22SEQB23SEQB24————00hSEQB2R/W24h
SEQB11SEQB12SEQB13SEQB14————00hSEQB1R/W23h
SEQA31SEQA32SEQA33SEQA34————00hSEQA3R/W22h
SEQA21SEQA22SEQA23SEQA24————00hSEQA2R/W21h
SEQA11SEQA12SEQA13SEQA14————00hSEQA1R/W20h
SEQD31SEQD33———
SEQD21SEQD22SEQD23
SEQD11SEQD13———
SEQC31SEQC32SEQC33
SEQD32SEQD34
SEQD24———
SEQD12SEQD14
SEQC34———
—00hSEQD3R/W2Bh
—00hSEQD2R/W2Ah
—00hSEQD1R/W29h
—00hSEQC3R/W28h
Register Name
D0
R/W Default
Sub
Address D5D6D7
Data
D1D2D3D4
Note) Read value of "—"(the blanks) is [0] in the register map.
OPERATION (continued)
2. Register map (continued)
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Product Standards
DLB3[4:0]—
DLB2[4:0]—
DLB1[4:0]—
DLA3[4:0]—
DLA2[4:0]—
DLA1[4:0]—
—
—
—
—
—
—
DLLCA300hA3SET3R/W38h
TSA3[7:0]00hA3SET2R/W37h
BLA3[7:0]00hA3SET1R/W36h
DLLCB100hB1SET3R/W3Bh
TSB1[7:0]00hB1SET2R/W3Ah
BLB1[7:0]00hB1SET1R/W39h
DLLCB200hB2SET3R/W3Eh
TSB2[7:0]00hB2SET2R/W3Dh
BLB2[7:0]00hB2SET1R/W3Ch
DLLCB300hB3SET3R/W41h
TSB3[7:0]00hB3SET2R/W40h
BLB3[7:0]00hB3SET1R/W3Fh
BLA2[7:0]00hA2SET1R/W33h
TSA2[7:0]00hA2SET2R/W34h
DLLCA200hA2SET3R/W35h
BLA1[7:0]00hA1SET1R/W30h
TSA1[7:0]00hA1SET2R/W31h
DLLCA100hA1SET3R/W32h
Register Name
D0
R/W Default
Sub
Address D5D6D7
Data
D1D2D3D4
Note) Read value of "—"(the blanks) is [0] in the register map.
OPERATION (continued)
2. Register map (continued)
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Product Standards
DLD3[4:0]—
DLD2[4:0]—
DLD1[4:0]—
DLC3[4:0]—
DLC2[4:0]—
DLC1[4:0]—
—
—
—
—
—
—
BLD1[7:0]00hD1SET1R/W4Bh
TSD1[7:0]00hD1SET2R/W4Ch
DLLCD100hD1SET3R/W4Dh
BLD2[7:0]00hD2SET1R/W4Eh
TSD2[7:0]00hD2SET2R/W4Fh
DLLCD200hD2SET3R/W50h
BLD3[7:0]00hD3SET1R/W51h
TSD3[7:0]00hD3SET2R/W52h
DLLCD300hD3SET3R/W53h
BLC1[7:0]00hC1SET1R/W42h
TSC1[7:0]00hC1SET2R/W43h
DLLCC100hC1SET3R/W44h
BLC2[7:0]00hC2SET1R/W45h
TSC2[7:0]00hC2SET2R/W46h
DLLCC200hC2SET3R/W47h
BLC3[7:0]00hC3SET1R/W48h
TSC3[7:0]00hC3SET2R/W49h
DLLCC3
00hC3SET3R/W4Ah
Register Name
D0
R/W Default
Sub
Address D5D6D7
Data
D1D2D3D4
Note) Read value of "—"(the blanks) is [0] in the register map.
OPERATION (continued)
2. Register map (continued)
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Product Standards
3.2. START and STOP conditions
A High to Low transition on the SDA line while SCL is High is one such unique case. This situation indicates
START condition. A Low to High transition on the SDA line while SCL is High defines STOP condition.
START and STOP conditions are always generated by the master. After START condition occur, the bus will
be busy.
The bus is considered to be free again a certain time after the STOP condition.
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer
is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most
significant bit (MSB) first.
3.3. Transferring Data
START condition STOP condition
SDA
SCL
Byte transfer completion,
Receive interrupt
acknowledgement
signal from slave
acknowledgement
signal from receiver
START or repeated
START condition
STOP or repeated
START condition
SCL
SDA
MSB
ACK ACK
12 789 123 –89
Sr
or
P
Sr
P
S
or
Sr
• This LSI, I2C-bus, is designed to correspond to the Standard-mode (100 kbps) and Fast-mode(400 kbps)
devices in the version 03 of NXP's specification. However, it does not correspond to the HS-mode (to 3.4
Mbps).
• This LSI will operate as a slave device in the I2C-bus system. This LSI will not operate as a master device.
• The program operation check of this LSI has not been conducted on the multi-master bus system and the mix-
speed bus system, yet. The connected confirmation of this LSI to the CBUS receiver also has not been
checked. Please confirm with our company if it will be used in these mode systems.
• The I2C is the brand of NXP.
OPERATION (continued)
3. I2C-bus interface
3.1 Basic Rules
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Product Standards
: Data transmission from Master
: Data transmission from Slave
It is possible to select slave address by switching SLASEL pin from Low-level to High-level.
The slave address of this LSI is as follows.
0110100XLow
0110101X
Slave address
High
SLASEL
Data of Sub address X Data of Sub address X+1
ACK : 0
START condition Write mode : 0
AAA
7-bit 8-bit 8-bit
ACK : 0 ACK : 0
8-bit
Data of Sub address X+m-1 Data of Sub address X+m
A
8-bit
ACK : 0
8-bit
ACK : 0
A
A
ACK : 0
Sub address (X)1Data byte Data byteSSlave address W
Data byte Data byte P
STOP condition
ACK : 0
START condition Write mode : 0
AAAP
7-bit 8-bit 8-bit
ACK : 0 ACK : 0
SSlave address Sub addressW 0 Data byte
Write mode (Auto increment mode)
When MSB of sub address (8-bit) is "1", auto increment mode is defined.
By transmitting data bytes continuously, the data bytes are written into continuous sub address.
The sub address is incremented automatically.
Write mode
When MSB of sub address (8-bit) is "0", the sub address is not incremented automatically.
By transmitting data bytes continuously, the next data bytes are written into the same sub address. by
transmitting data byte continuously
OPERATION (continued)
3. I2C-bus interface (continued)
3.4 Data format
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Product Standards
When the data is read without specifying sub address 8-bit, it is possible to read the value of sub address
specified at adjacent write mode.
ACK : 0
START condition Write mode : 0
ACK : 0 NACK : 1
STOP conditionRepeated START condition Read mode : 1
ACK : 0
SSlave address Sub addressWA 0Sr Slave address A
7-bit 8-bit 7-bit
Data byte
8-bit
A
A PR
SSlave address Data byte
STOP condition
ACK : 0
START condition Read mode : 1
RA AP
7-bit 8-bit
NACK : 1
: Data transmission from Master
: Data transmission from Slave
When MSB of sub address (8-bit) is "0", sub address is incremented automatically.
Data byte of specified sub address is read repeatedly continuously until STOP condition is received.
Read mode (In case sub address is specified)
Read mode (Auto increment mode in case sub address is specified)
Read mode (In case sub address is not specified)
When MSB of sub address (8-bit) is "1", auto increment mode is specified.
Until STOP condition is received, data byte of sub address incremented automatically by specified sub address
can be read continuously
The sub address is incremented automatically.
Data byte A
8-bit
ACK : 0
Data byte
8-bit
NACK : 1
AP
SSlave address Sub address (X)
ACK : 0
START condition
WA 1SrSlave address A
7-bit 8-bit 7-bit
ACK : 0
Data byte
8-bit
A
ACK : 0
A R
Repeated START condition Read mode : 1
ACK : 0
Data of Sub address X
STOP condition
Write mode : 0
Data of Sub address X+m–1 Data of Sub address X+m
OPERATION (continued)
3. I2C-bus interface (continued)
3.4 Data format (continued)
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Product Standards
CPOUT
VB
VLDO
VDD
GND
CPGND
Charge
pump LOGIC MTX SCAN I2C
BGR
TSD
Oscillator 2.4 MHz
(PAD) CLKIO
(Register) IOCNT
Logic block
(MTX)
*Matrix operation, PWM control
1
0
1
0
1
4
Charge pump
CPCLKSEL15 (at 1.5mode)
CPCLKSEL20 (at 2mode)
600kHz
(Register)
1
2
1.2MHz
Distribution diagram of control / clock system
OPERATION (continued)
4. Signal distribution diagram
Distribution diagram of power supply system
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Product Standards
PACKAGE INFORMATION ( Reference Data )
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Product Standards
IMPORTANT NOTICE
1. When using the LSI for new models, verify the safety including the long-term reliability for each product.
2. When the application system is designed by using this LSI, please confirm the notes in this book.
Please read the notes to descriptions and the usage notes in the book.
3. This LSI is intended to be used for general electronic equipment.
Consult our sales staff in advance for information on the following applications: Special applications in which exceptional
quality and reliability are required, or if the failure or malfunction of this LSI may directly jeopardize life or harm the human
body.
Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)
(2) Traffic control equipment (such as for automobile, airplane, train, and ship)
(3) Medical equipment for life support
(4) Submarine transponder
(5) Control equipment for power plant
(6) Disaster prevention and security device
(7) Weapon
(8) Others : Applications of which reliability equivalent to (1) to (7) is required
Our company shall not be held responsible for any damage incurred as a result of or in connection with the LSI being used for
any special application, unless our company agrees to the use of such special application.
4. This LSI is neither designed nor intended for use in automotive applications or environments unless the specific product is
designated by our company as compliant with the ISO/TS 16949 requirements.
Our company shall not be held responsible for any damage incurred by customers or any third party as a result of or in
connection with the LSI being used in automotive application, unless our company agrees to such application in this book.
5. Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. Our company shall not be held responsible for any damage
incurred as a result of our LSI being used by our customers, not complying with the applicable laws and regulations.
6. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might emit
smoke or ignite.
7. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In
addition, refer to the Pin Description for the pin configuration.
8. Perform visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as
solder-bridge between the pins of the semiconductor device. Also, perform full technical verification on the assembly quality,
because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI
during transportation.
9. Take notice in the use of this product that it might be damaged or occasionally emit smoke when an abnormal state occurs
such as output pin-VCC short (Power supply fault), output pin-GND short (Ground fault), or output-to-output-pin short (load
short). Safety measures such as installation of fuses are recommended because the extent of the above-mentioned damage
and smoke emission will depend on the current capability of the power supply..
10. The protection circuit is for maintaining safety against abnormal operation. Therefore, the protection circuit should not work
during normal operation.
Especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily
exceeded due to output pin to VCC short (Power supply fault), or output pin to GND short (Ground fault), the LSI might be
damaged before the thermal protection circuit could operate.
11. Unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the
pins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated
during the ON and OFF timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven.
12. Verify the risks which might be caused by the malfunctions of external components.
13. Due to the unshielded structure of this LSI, functions and characteristics of the product cannot be guaranteed under the
exposure of light. During normal operation or even under testing condition, please ensure that the LSI is not exposed to light.
14. Please ensure that your design does not have metal shield parts touching the chip surface as the surface potential is GND
voltage.
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Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for general applications (such as office equipment, communications
equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book.
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment,
life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of
the products may directly jeopardize life or harm the human body.
It is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with
your using the products described in this book for any special application, unless our company agrees to your using the products in
this book for any special application.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or im-
provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
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