ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
Product Specification
PS021410-0605
CrimzonTM ZLR16300
Z8 Low Voltage ROM MCUs
with Infrared Timers
Disclaimer PS021410-0605
This publication is subject to replacement by a later edition. To determine whether a later edition
exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.zilog.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or
service names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty
and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no
warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No licenses are
conveyed, implicitly or otherwise, by this document under any intellectual property rights.
CrimzonTM ZLR16300
Product Specification
PS021410-0605
iii
Revision History
Each instance in Table 1 reflects a change to this document from its previous revi-
sion. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document
Date
Revision
Level Description Page#
December
2004
07 Changed low power consumption and current usage for STOP and HALT
modes, removed mask option note, and added characterization data to
Table 7.
1, 2, 8
Removed Preliminary designation All
January
2005
08 Changed low power consumption value to 5mW. Changed STOP and
HALT mode current values to 1.3µA and 0.5mA respectively. Changed
VCC Low Voltage Protection typical rating to 1.8V.
1, 12
April 2005 09 Clarified Port 1 reserved address status by removing Port 1 in Figure 1
and adding a note in Figure 12. Reference CR5843.
3, 21
June 2005 10 Added 1K and 2K parts. All
CrimzonTM ZLR16300
Product Specification
PS021410-0605 Table of Contents
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port 0 (P07–P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port 2 (P27–P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Port 3 (P37–P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 58
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 63
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CrimzonTM ZLR16300
Product Specification
PS021410-0605 List of Figures
v
List of Figures
Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 20-Pin DIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . 5
Figure 4. 28-Pin DIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 17
Figure 11. Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15. Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 37
Figure 21. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 24. T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 26. Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 28. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 29. Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 48
Figure 30. Stop Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 31. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 32. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 33. Stop Mode Recovery Register 2 ((0F) DH:D2–D4,
D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
CrimzonTM ZLR16300
Product Specification
PS021410-0605 List of Figures
vi
Figure 34. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . . 55
Figure 35. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 36. TC8 Control Register ((0D) 00H: Read/Write
Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 37. T8 and T16 Common Control Functions ((0D)
01H: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 38. T16 Control Register ((0D) 02H: Read/Write
Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 39. T8/T16 control Register (0D) 03H: Read/Write
(Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 40. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 41. Port Configuration Register (PCON) ((0F)00H: Write Only . . . . . . . 64
Figure 42. Stop Mode Recovery Register ((0F) 0BH: D6–D0=Write Only,
D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 43. Stop Mode Recovery Register 2 ((0F) 0DH: D2–D4,
D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 44. Watch-Dog Timer Register ((0F) 0FH: Write Only) . . . . . . . . . . . . . 67
Figure 45. Port 2 Mode Register (F6H: Write Only). . . . . . . . . . . . . . . . . . . . . . 67
Figure 46. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . 68
Figure 47. Port 0 Register (F8H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 48. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . 70
Figure 49. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . 71
Figure 50. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . 71
Figure 51. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 52. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 53. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 73
Figure 54. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 55. 20-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 56. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 57. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 58. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 59. 28-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 60. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CrimzonTM ZLR16300
Product Specification
PS021410-0605 List of Tables
vii
List of Tables
Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Table 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 3. Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 4. 20-Pin DIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . . 5
Table 5. 28-Pin DIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Port 3 Pin Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. CTR1(0D)01h T8 and T16 Common Functions . . . . . . . . . . . . . . . . 28
Table 11. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 13. SMR2(F)0DH:Stop Mode Recovery Register 2* . . . . . . . . . . . . . . . 51
Table 14. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 15. Watch-Dog Timer Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 16. ROM Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
CrimzonTMZLR16300
Product Specification
PS021410-0605 Features
1
Features
Table 1 lists the features of ZiLOG®’s CrimzonTM ZLR16300 family members.
•
Low power consumption–5mW (typical)
•
Three standby modes:
–
STOP—1.3µA (typical)
–
HALT—0.5mA (typical)
–
Low voltage reset
•
Special architecture to automate both generation and reception of complex pulses
or signals:
–
One programmable 8-bit counter/timer with two capture registers and two
load registers
–
One programmable 16-bit counter/timer with one 16-bit capture register
pair and one 16-bit load register pair
–
Programmable input glitch filter for pulse reception
•
Six priority interrupts
–
Three external
–
Two assigned to counter/timers
–
One low-voltage detection interrupt
•
Low voltage detection and high voltage detection flags
•
Programmable Watch-Dog Timer (WDT)
•
Power-On Reset (POR)
•
Two independent comparators with programmable interrupt polarity
•
Selectable pull-up transistors on ports 0, 2, 3
Table 1. Features
Device ROM (KB) RAM* (Bytes) I/O Lines Voltage Range
CrimzonTM ZLR16300 1, 2, 4, 8, 16 237 24, 16 2.0V–3.6V
* General purpose
CrimzonTMZLR16300
Product Specification
PS021410-0605 General Description
2
•
Mask options
–
Port 0: 0–3 pull-ups
–
Port 0: 4–7 pull-ups
–
Port 2: 0–7 pull-ups
–
Port 3: 0–3 pull-ups
–
Watch-Dog Timer at Power On Reset
General Description
The CrimzonTM ZLR16300 is a ROM-based member of the MCU family of general
purpose microcontrollers. With 1KB to 16KB of program memory and 237B of
general purpose RAM, ZiLOG®’s CMOS microcontrollers offer fast-executing,
efficient use of memory, sophisticated interrupts, input/output bit manipulation
capabilities, automated pulse generation/reception, and internal key-scan pull-up
transistors.
The CrimzonTM ZLR16300 architecture (Figures 1 and 2) is based on ZiLOG®’s 8-
bit microcontroller core with an Expanded Register File allowing access to regis-
ter-mapped peripherals, input/output (I/O) circuits, and powerful counter/timer cir-
cuitry. The Z8 core offers a flexible I/O scheme, an efficient register and address
space structure, and a number of ancillary features that are useful in many con-
sumer, automotive, computer peripheral, and battery-operated hand-held applica-
tions.
There are three basic address spaces available to support a wide range of config-
urations: Program Memory, Register File and Expanded Register File. The regis-
ter file is composed of 256B of RAM. It includes three I/O port registers, 16 control
and status registers, and 237 general-purpose registers. The Expanded Register
File consists of two additional register groups (F and D).
To unburden the program from coping with such real-time problems as generating
complex waveforms or receiving and demodulating complex waveform/pulses, the
CrimzonTM ZLR16300 offers a new intelligent counter/timer architecture with 8-bit
and 16-bit counter/timers (see Figure 2). Also included are a large number of
user-selectable modes and two on-board comparators to process analog signals
with separate reference voltages.
Power connections use the conventional descriptions listed in Table 2.
Table 2. Power Connections
Connection Circuit Device
Power VCC VDD
Ground GND VSS
CrimzonTMZLR16300
Product Specification
PS021410-0605 General Description
3
Figure 1. Functional Block Diagram
Z8® Core
Port 2
Port 0
P21
P22
P23
P24
P25
P26
P27
P20
I/O Bit
Programmable
P04
P05
P06
P07
P00
P01
P02
P03
I/O Nibble
Programmable
Register File
256 x 8-Bit
Register Bus
Internal
Address Bus
Internal
Data Bus
Expanded
Register
File
Expanded
Register Bus
Z8
®
Core
Counter/Timer 8
8-Bit
Counter/Timer 16
16-Bit
V
DD
V
SS
XTAL
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
Port 3
Machine
Timing &
Instruction
Control
Power
4
4
ROM
Up to 16K x 8
Watch-Dog
Timer
Low Voltage
Detection
High Voltage
Detection
Power-On
Reset
Note: Refer to the specific package for available pins.
CrimzonTMZLR16300
Product Specification
PS021410-0605 General Description
4
Figure 2. Counter/Timers Diagram
HI16 LO16
16-Bit
T16
TC16H TC16L
HI8 LO8
And/Or
Logic
Clock
Divider
Glitch
Filter
Edge
Detect
Circuit 8-Bit
T8
TC8H TC8L
88
16
8
Input
SCLK
1248
Timer 16
Timer 8/16
Timer 8
88
88
8
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Description
5
Pin Description
The pin configuration for the 20-pin DIP/SOIC/SSOP is illustrated in Figure 3 and
described in Table 3. The pin configuration for the 28-pin DIP/SOIC/SSOP are
depicted in Figure 4 and described in Table 4.
Figure 3. 20-Pin DIP/SOIC/SSOP Pin Configuration
Table 3. 20-Pin DIP/SOIC/SSOP Pin Identification
Pin # Symbol Function Direction
1–3 P25–P27 Port 2, Bits 5,6,7 Input/Output
4 P07 Port 0, Bit 7 Input/Output
5V
DD Power Supply
6 XTAL2 Crystal Oscillator Clock Output
7 XTAL1 Crystal Oscillator Clock Input
8–10 P31–P33 Port 3, Bits 1,2,3 Input
11,12 P34, P36 Port 3, Bits 4,6 Output
13 P00/Pref1/P30 Port 0, Bit 0/Analog reference input
Port 3, Bit 0
Input/Output for P00
Input for Pref1/P30
14 P01 Port 0, Bit 1 Input/Output
15 VSS Ground
16–20 P20–P24 Port 2, Bits 0,1,2,3,4 Input/Output
P25
P26
P27
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P24
P23
P22
P21
P20
VSS
P01
P00/Pref1/P30
P36
P34
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
20-Pin
DIP
SOIC
SSOP
CrimzonTMZLR16300
Product Specification
PS021410-0605 Absolute Maximum Ratings
6
Figure 4. 28-Pin DIP/SOIC/SSOP Pin Configuration
Table 4. 28-Pin DIP/SOIC/SSOP Pin Identification
Absolute Maximum Ratings
Stresses greater than those listed in Table 5 might cause permanent damage to
the device. This rating is a stress rating only. Functional operation of the device at
Pin Symbol Direction Description
1-3 P25-P27 Input/Output Port 2, Bits 5,6,7
4-7 P04-P07 Input/Output Port 0, Bits 4,5,6,7
8V
DD Power supply
9 XTAL2 Output Crystal, oscillator clock
10 XTAL1 Input Crystal, oscillator clock
11–13 P31-P33 Input Port 3, Bits 1,2,3
14 P34 Output Port 3, Bit 4
15 P35 Output Port 3, Bit 5
16 P37 Output Port 3, Bit 7
17 P36 Output Port 3, Bit 6
18 Pref1 Input Analog ref input; connect to VCC if not used
Port 3 Bit 0
19-21 P00-P02 Input/Output Port 0, Bits 0,1,2
22 VSS Ground
23 P03 Input/Output Port 0, Bit 3
24-28 P20-P24 Input/Output Port 2, Bits 0-4
P24
P23
P22
P21
P20
P03
VSS
P02
P01
P00
Pref1/P30
P36
P37
P35
P25
P26
P27
P04
P05
P06
P07
VDD
XTAL2
XTAL1
P31
P32
P33
P34
1
28-Pin
PDIP
SOIC
SSOP
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Test Conditions
7
any condition above those indicated in the operational sections of these specifica-
tions is not implied. Exposure to absolute maximum rating conditions for an
extended period might affect device reliability.
Standard Test Conditions
The characteristics listed in this product specification apply for standard test con-
ditions as noted. All voltages are referenced to GND. Positive current flows into
the referenced pin (see Figure 5).
Figure 5. Test Load Diagram
Table 5. Absolute Maximum Ratings
Parameter Minimum Maximum Units Notes
Ambient temperature under bias 0 +70 C
Storage temperature –65 +150 C
Voltage on any pin with respect to VSS –0.3 +4.0 V 1
Voltage on VDD pin with respect to VSS –0.3 +3.6 V
Maximum current on input and/or inactive output pin –5 +5 mA
Maximum output current from active output pin -25 +25 mA
Maximum current into VDD or out of VSS 75 mA
Note:
1. This voltage applies to all pins except the following: VDD.
From Output
Under Test
150 pF
CrimzonTMZLR16300
Product Specification
PS021410-0605 DC Characteristics
8
Capacitance
Table 6 lists the capacitances.
DC Characteristics
Table 6. Capacitance
Parameter Maximum
Input capacitance 12pF
Output capacitance 12pF
I/O capacitance 12pF
Note: TA = 25°C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND
Table 7. DC Characteristics
TA= 0°C to +70°C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
VCC Supply Voltage 2.0 V 3.6 V See Note 5
VCH Clock Input High
Voltage
2.0-3.6V 0.8 VCC VCC+0.3 V Driven by External
Clock Generator
VCL Clock Input Low
Voltage
2.0-3.6V VSS–0.3 0.5 V Driven by External
Clock Generator
VIH Input High Voltage 2.0-3.6V 0.7 VCC VCC+0.3 V
VIL Input Low Voltage 2.0-3.6V VSS–0.3 0.2 VCC V
VOH1 Output High Voltage 2.0-3.6V VCC–0.4 V IOH = –0.5mA
VOH2 Output High Voltage
(P36, P37, P00, P01)
2.0-3.6V VCC–0.8 V IOH = –7mA
VOL1 Output Low Voltage 2.0-3.6V 0.4 V IOL = 4.0mA
VOL2 Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6V 0.8 V IOL = 10mA
VOFFSET Comparator Input
Offset Voltage
2.0-3.6V 25 mV
VREF Comparator
Reference
Voltage
2.0-3.6V 0 VDD
-1.75
V
IIL Input Leakage 2.0-3.6V –1 1 µAV
IN = 0V, VCC
Pull-ups disabled
RPU Pull-up Resistance 2.0V 225 675 KΩVIN = 0V; Pullups selectedby mask
option
3.6V 75 275 KΩ
IOL Output Leakage 2.0-3.6V –1 1 µAV
IN = 0V, VCC
ICC Supply Current 2.0 V
3.6 V
1.2
2.1
3
5
mA
mA
at 8.0MHz
at 8.0MHz
1, 2
1, 2
CrimzonTMZLR16300
Product Specification
PS021410-0605 DC Characteristics
9
ICC1 Standby Current
(HALT Mode)
2.0 V
3.6 V
0.5
0.8
1.6
2.0
mA
mA
VIN = 0V, Clock at 8.0MHz
Same as above
1, 2, 6
1, 2, 6
ICC2 Standby Current
(STOP Mode)
2.0 V
3.6 V
2.0 V
3.6 V
1.2
1.4
3.5
6.5
8
10
20
30
µA
µA
µA
µA
VIN = 0 V, VCC WDT is not Running
Same as above
VIN = 0 V, VCC WDT is Running
Same as above
3
3
3
3
ILV Standby Current
(Low Voltage)
0.8 6 µA Measured at 1.3V 4
VBO VCC Low Voltage
Protection
1.8 2.0 V 8MHz maximum
Ext. CLK Freq.
VLVD Vcc Low Voltage
Detection
2.4 V
VHVD Vcc High Voltage
Detection
2.7 V
Notes:
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (minimum 0.1 µF), physically close to VDD and VSS pins if operating
voltage fluctuations are anticiipated, such as those resulting from driving an IR LED.
6. Comparators and Timers are on. Interrupt disabled.
7. Typical vales shown are at 25 degrees C.
Table 7. DC Characteristics (Continued)
TA= 0°C to +70°C
Units Conditions NotesSymbol Parameter VCC Min Typ(7) Max
CrimzonTMZLR16300
Product Specification
PS021410-0605 AC Characteristics
10
AC Characteristics
Figure 6 and Table 8 describe the Alternating Current (AC) characteristics.
Figure 6. AC Timing Diagram
Clock
Stop Mode
Recovery
Source
Clock
Setup
1
22
3
3
TIN
7
45
6
7
IRQN
89
11
10
CrimzonTMZLR16300
Product Specification
PS021410-0605 AC Characteristics
11
Table 8. AC Characteristics
TA=0°C to +70°C
8.0MHz
Watch-Dog
Timer Mode
Register
(D1, D0)No Symbol Parameter VCC Minimum Maximum Units Notes
1 TpC Input Clock Period 2.0–3.6 121 DC ns 1
2 TrC,TfC Clock Input Rise and
Fall Times
2.0–3.6 25 ns 1
3 TwC Input Clock Width 2.0–3.6 37 ns 1
4 TwTinL Timer Input
Low Width
2.0
3.6
100
70
ns 1
5 TwTinH Timer Input High
Width
2.0–3.6 3TpC 1
6 TpTin Timer Input Period 2.0–3.6 8TpC 1
7 TrTin,TfTin Timer Input Rise and
Fall Timers
2.0–3.6 100 ns 1
8 TwIL Interrupt Request
Low Time
2.0
3.6
100
70
ns 1, 2
9 TwIH Interrupt Request
Input High Time
2.0–3.6 10TpC 1, 2
10 Twsm Stop-Mode
Recovery Width
Spec
2.0–3.6 12
10TpC
ns 3
4
11 Tost Oscillator
Start-Up Time
2.0–3.6 5TpC 4
12 Twdt Watch-Dog Timer
Delay Time
2.0–3.6
2.0–3.6
2.0–3.6
2.0–3.6
10
20
40
160
ms
ms
ms
ms
0, 0
0, 1
1, 0
1, 1
13 TPOR Power-On Reset 2.0–3.6 2.5 10 ms
Notes:
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.
2. Interrupt request through Port 3 (P33–P31).
3. SMR – D5 = 1.
4. SMR – D5 = 0.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Functions
12
Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip
oscillator input. Additionally, an external single-phase clock can be connected to
the on-chip oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip
oscillator output.
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are
configured under software control as a nibble I/O port. The output drivers are
push-pull or open-drain controlled by bit D2 in the PCON register.
If one or both nibbles are needed for I/O operation, they must be configured by
writing to the Port 0 mode register. After a hardware reset, Port 0 is configured
(Figure 7) as an input port.
An optional pull-up transistor is available as a mask option on all Port 0 bits with
nibble select.
Internal pull-ups are disabled on any given pin or group of port
pins when programmed into Output mode.
The Port 0 direction is reset to be input following an SMR.
Notes:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Functions
13
Figure 7. Port 0 Configuration
Port 2 (P27–P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 8). These
eight I/O lines can be independently configured under software control as inputs
or outputs. Port 2 is always available for I/O operation. A mask option is available
to connect eight pull-up transistors on this port. Bits programmed as outputs are
globally programmed as either push-pull or open-drain. The POR resets with the
eight bits of Port 2 configured as inputs.
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up
the part. P20 can be programmed to access the edge-detection circuitry in
Demodulation mode.
4
4
ZLR16300 Port 0 (I/O)
Pad
In
Out
I/O
Open-Drain
Resistive
Transistor
Pull-up
VCC
Mask
Option
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Functions
14
Figure 8. Port 2 Configuration
Port 3 (P37–P30)
Port 3 is an 8-bit, CMOS-compatible fixed I/O port (see Figure 9). Port 3 consists
of four fixed input (P33–P30) and four fixed output (P37–P34), which can be con-
figured under software control for interrupt and as output from the counter/timers.
P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are
push-pull outputs.
Port 2 (I/O)
Pad
In
Out
I/O
Open-Drain Resistive
Transistor
Pull-up
VCC
Mask
Option
ZLR16300
ROM
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Functions
15
Figure 9. Port 3 Configuration
Two on-board comparators process analog signals on P31 and P32, with refer-
ence to the voltage on Pref1 and P33. The analog function is enabled by program-
ming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising,
falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33
are the comparator reference voltage inputs. Access to the Counter Timer edge-
detection circuit is through P31 or P20 (see “T8 and T16 Common Functions—“T8
-
Port 3 (I/O)
P32 (AN2)
P31 (AN1)
Pref1
From Stop Mode Recovery Source of SMR
IRQ2, P31 Data Latch
Pref1/P30
P31
P32
P33
P34
P35
P36
P37
D1 1 = Analog
0 = Digital
R247 = P3M
+
-
+IRQ0, P32 Data Latch
IRQ1, P33 Data Latch
Comp1
Comp2
Dig.
An.
ZLR16300
ROM
P33 (REF2)
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Functions
16
and T16 Common Functions—CTR1(0D)01h” on page 28). Other edge detect and
IRQ modes are described in Table 9.
Comparators are powered down by entering Stop Mode. For
P31–P33 to be used in a Stop Mode Recovery (SMR) source,
these inputs must be placed into Digital mode.
2
Port 3 also provides output for each of the counter/timers and the AND/OR Logic
(see Figure 10). Control is performed by programming bits D5–D4 of CTR1, bit 0
of CTR0, and bit 0 of CTR2.
Table 9. Port 3 Pin Function Summary
Pin I/O Counter/Timers Comparator Interrupt
Pref1/P30 IN RF1
P31 IN IN AN1 IRQ2
P32 IN AN2 IRQ0
P33 IN RF2 IRQ1
P34 OUT T8 AO1
P35 OUT T16
P36 OUT T8/16
P37 OUT AO2
P20 I/O IN
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Pin Functions
17
Figure 10. Port 3 Counter/Timer Output Configuration
Pad
P34
Comp1
VDD
MUX
PCON, D0
MUX
CTR0, D0
P31
P30 (Pref1)
P34 data
T8_Out
+
Pad
P35
VDD
MUX
CTR2, D0
Out 35
T16_Out
Pad
P36
VDD
MUX
CTR1, D6
Out 36
T8/T16_Out
Pad
P37
VDD
MUX
PCON, D0
P37 data
-
P31
P3M D1
Comp2
P32
P33
+
-
P32
P3M D1
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
18
Comparator Inputs
In ANALOG mode, P31 and P32 have a comparator front end. The comparator
reference is supplied to P33 and Pref1. In this mode, the P33 internal data latch
and its corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32,
and P33) as indicated in Figure 9 on page 15. In digital mode, P33 is used as D3
of the Port 3 input register, which then generates IRQ1.
Comparators are powered down by entering STOP mode. For
P31–P33 to be used in a STOP Mode Recovery source, these
inputs must be placed into Digital mode.
Comparator Outputs
These channels can be programmed to be output on P34 and P37 through the
PCON register.
Functional Description
These devices incorporate special functions to enhance the Z8®’s functionality in
consumer and battery-operated applications.
Program Memory
These devices address from 1KB to16KB of program memory. The first 12 Bytes
are reserved for interrupt vectors. These locations contain the six 16-bit vectors
that correspond to the six available interrupts. See Figure 11.
RAM
The ZLR16300 product family features 237 Bytes of RAM.
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
19
Figure 11. Program Memory Map
On-Chip
ROM
Reset Start Address
IRQ5
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
12
11
10
9
8
7
6
5
4
3
2
1
0
Maximum ROM Size
Location of
first Byte of
instruction
executed
after RESET
Interrupt Vector
(Lower Byte)
Interrupt Vector
(Upper Byte)
Not Accessible
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
20
Expanded Register File
The register file has been expanded to allow for additional system control regis-
ters and for mapping of additional peripheral devices into the register address
area. The Z8 register address space (0 through15 (OFh) has been implemented
as 16 banks, with 16 registers per bank. These register banks are known as the
ERF (Expanded Register File). Bits 7–4 of register RP select the working register
group. Bits 3–0 of register RP select the expanded register file bank.
An expanded register bank is also referred to as an expanded
register group (see Figure 12).
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
21
Figure 12. Expanded Register File Architecture
UUUUUUU0
00000000
00000000
00000000
00
0F
7F
F0
FF
FF SPL
00000000
UUUUUUUU
00000000
UUUUUUUU
UUUUUUUU
UUUUUUUU
11111111
00000000
11001111
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
UUUUUUUU
FE SPH
FD RP
FC FLAGS
FB IMR
FA IRQ
F9 IPR
F8 P01M
F7 P3M
F6 P2M
F5 Reserved
F4 Reserved
F3 Reserved
F2 Reserved
F1 Reserved
F0 Reserved
D7
D6 D5 D4 D3 D2 D1 D0
UU001101
U01000U0
11111110
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D SMR2
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
76543210
Expanded Register
Bank Pointer
Working Register
UUUUUUUU
UUUUUUUU
00000000
(D) 0C LVD
(D) 0B HI8
(D) 0A LO8
(D) 09 HI16
(D) 08 LO16
(D) 07 TC16H
(D) 06 TC16L
(D) 05 TC8H
(D) 04 TC8L
(D) 03 CTR3
(D) 02 CTR2
(D) 01 CTR1
(D) 00 CTR0
Group Pointer
Register File (Bank 0)**
00011111
*
*
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
U = Unknown
* Is not reset with a Stop-Mode Recovery
** All addresses are in hexadecimal
↑ Is not reset with a Stop-Mode Recovery, except Bit 0
↑↑ Bit 5 is not reset with a Stop-Mode Recovery
↑↑↑ Bits 5,4,3,2 not reset with a Stop-Mode Recovery
↑↑↑↑ Bits 5 and 4 not reset with a Stop-Mode Recovery
↑↑↑↑↑ Bits 5,4,3,2,1 not reset with a Stop-Mode Recovery
Expanded Reg. Bank 0/Group (0)
(0) 03 P3
(0) 02 P2
0U
U
↑↑↑↑↑
↑↑↑↑
↑↑↑
↑↑
*
*
*
*
*
*
*
*
*
*
*
Expanded Reg. Bank F/Group 0**
Register**
Register Pointer
Z8® Standard Control Registers
Expanded Reg. Bank D/Group 0
↑
Reset Condition
U
(0) 00 P0
Reserved
NOTE: A write has no effect. Will always read back FF.
NOTE
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
22
The upper nibble of the register pointer (see Figure 13) selects which working reg-
ister group, of 16 bytes in the register file, is accessed out of the possible 256. The
lower nibble selects the expanded register file bank and in the case of the Crim-
zonTM ZLR16300 family, banks 0, F, and D are implemented. A 0h in the lower
nibble allows the normal register file (bank 0) to be addressed. Any other value
from 1h to Fh exchanges the lower 16 registers to the selected expanded register
bank.
Figure 13. Register Pointer
Example: (See Figure 12 on page 21)
R253 RP = 00h
R0 = Port 0
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0Dh
R0 = CTR0
R1 = CTR1
R2 = CTR2
R3 = CTR3
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register
File Pointer
Working Register
Pointer
Default Setting After Reset = 0000 0000
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
23
The counter/timers are mapped into ERF group D. Access is easily performed
using the following:
LD RP, #0Dh ;Select ERF D for
access to bank D
;(working register
group 0)
LD R0,#xx ;load CTR0
LD 1, #xx ;load CTR1
LD R1, 2 ;CTR2→CTR1
LD RP, #0Dh ;Select ERF D for
access to bank D
; (working register
group 0)
LD RP, #7Dh ;Select expanded
register bank D and working ;register group 7 of
bank 0 for access.
LD 71h, 2 ;CTRL2→register 71h
LD R1, 2 ;CTRL2→register 71h
Register File
The register file (bank 0) consists of 3 I/O port registers, 237 general-purpose reg-
isters, 16 control and status registers (R0, R2, R3, R4–R239, and R240–R255,
respectively), and two expanded register Banks D (see Table 10) and F. Instruc-
tions can access registers directly or indirectly through an 8-bit address field,
thereby allowing a short, 4-bit register address to use the Register Pointer
(Figure 14). In the 4-bit mode, the register file is divided into 16 working register
groups, each occupying 16 continuous locations. The Register Pointer addresses
the starting location of the active working register group.
Register address E0h–EFh can only be accessed through
working registers and indirect addressing modes.
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
24
Figure 14. Register Pointer—Detail
Stack
The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is
used for the internal stack that resides in the general-purpose registers (R4–
R239). SPH (R254) can be used as a general-purpose register.
R7R6R5R4R3R2R1R
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
Specified Working
Register Group
Register Group 1
Register Group 0
I/O Ports
R253
The lower nibble of the
register file address provided
by the instruction points to
the specified register.
* RP = 00: Selects Register Bank 0, Working Register Group 0
R15 to R0
R15 to R4 *
R3 to R0 *
40
3F
30
2F
20
1F
10
0F
00
Register Group 2
4F
FF
F0
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
25
Timers
T8_Capture_HI—HI8(0D)0Bh
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 1.
T8_Capture_LO—L08(0D)0Ah
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 0.
T16_Capture_HI—HI16(0D)09h
This register holds the captured data from the output of the 16-bit Counter/
Timer16. This register holds the MS-Byte of the data.
T16_Capture_LO—L016(0D)08h
This register holds the captured data from the output of the 16-bit Counter/
Timer16. This register holds the LS-Byte of the data.
Counter/Timer2 MS-Byte Hold Register—TC16H(0D)07h
Field Bit Position Description
T8_Capture_HI [7:0] R/W Captured Data - No Effect
Field Bit Position Description
T8_Capture_L0 [7:0] R/W Captured Data - No Effect
Field Bit Position Description
T16_Capture_HI [7:0] R/W Captured Data - No Effect
Field Bit Position Description
T16_Capture_LO [7:0] R/W Captured Data - No Effect
Field Bit Position Description
T16_Data_HI [7:0] R/W Data
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
26
Counter/Timer2 LS-Byte Hold Register—TC16L(0D)06h
Counter/Timer8 High Hold Register—TC8H0(D)05h
Counter/Timer8 Low Hold Register—TC8L(0D)04h
CTR0 Counter/Timer8 Control Register—CTR0(0D)00h
Table 10 lists and briefly describes the fields for this register.
Field Bit Position Description
T16_Data_LO [7:0] R/W Data
Field Bit Position Description
T8_Level_HI [7:0] R/W Data
Field Bit Position Description
T8_Level_LO [7:0] R/W Data
Table 10.CTR0(0D)00h Counter/Timer8 Control Register
Field Bit Position Value Description
T8_Enable 7------- R/W 0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------- R/W 0*
1
Modulo-N
Single Pass
Time_Out --5------ R/W 0**
1
0
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
Reset Flag to 0
T8 _Clock ---43--- R/W 0 0**
0 1
1 0
1 1
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1
Disable Data Capture Interrupt
Enable Data Capture Interrupt
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
27
T8 Enable
This field enables T8 when set (written) to 1.
Single/Modulo-N
When set to 0 (Modulo-N), the counter reloads the initial value when the terminal
count is reached. When set to 1 (Single-Pass), the counter stops when the termi-
nal count is reached.
Timeout
This bit is set when T8 times out (terminal count reached). To reset this bit, write a
1 to its location.
Writing a 1 is the only way to reset the Terminal Count
status condition. Reset this bit before using/enabling the
counter/timers.
The first clock of T8 might not have complete clock width
and can occur any time when enabled.
Take care when using the OR or AND commands to manipulate
CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode).
These instructions use a Read-Modify-Write sequence in which
the current status from the CTR0 and CTR1 registers is ORed
or ANDed with the designated value and then written back into
the registers.
T8 Clock
These bits define the frequency of the input signal to T8.
Counter_INT_Mask ------1- R/W 0**
1
Disable Time-Out Interrupt
Enable Time-Out Interrupt
P34_Out -------0 R/W 0*
1
P34 as Port Output
T8 Output on P34
Note:
*
Indicates the value at Power-On Reset.
*
* Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery.
Table 10.CTR0(0D)00h Counter/Timer8 Control Register (Continued)
Field Bit Position Value Description
Caution:
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
28
Capture_INT_Mask
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon
a positive or negative edge detection in Capture Mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
T8 and T16 Common Functions—CTR1(0D)01h
This register controls the functions in common with the T8 and T16.
Table 11 lists and briefly describes the fields for this register.
Table 11. CTR1(0D)01h T8 and T16 Common Functions
Field Bit Position Value Description
Mode 7------- R/W 0*
1
Transmit Mode
Demodulation Mode
P36_Out/
Capture_Input
-6------ R/W
0*
1
0*
1
Transmit Mode
Port Output
T8/T16 Output
Demodulation Mode
P31
P20
T8/T16_Logic/
Edge _Detect
--54---- R/W
00**
01
10
11
00**
01
10
11
Transmit Mode
AND
OR
NOR
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
29
Mode
If the result is 0, the counter/timers are in Transmit mode; otherwise, they are in
Demodulation Mode.
P36_Out/Demodulator_Input
In Transmit Mode, this bit defines whether P36 is used as a normal output pin or
the combined output of T8 and T16.
In Demodulation Mode, this bit defines whether the input signal to the Counter/
Timers is from P20 or P31.
Transmit_Submode/
Glitch_Filter
----32-- R/W
00
01
10
11
00
01
10
11
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out = 0
T16_Out = 1
Demodulation Mode
No Filter
4 SCLK Cycle
8 SCLK Cycle
Reserved
Initial_T8_Out/
Rising Edge
------1-
R/W
R
W
0
1
0
1
0
1
Transmit Mode
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
Rising Edge Detected
No Effect
Reset Flag to 0
Initial_T16_Out/
Falling_Edge
-------0
R/W
R
W
0
1
0
1
0
1
Transmit Mode
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
Falling Edge Detected
No Effect
Reset Flag to 0
Note:
*Default at Power-On Reset.
*
* Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery.
Table 11. CTR1(0D)01h T8 and T16 Common Functions (Continued)
Field Bit Position Value Description
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
30
If the input signal is from Port 31, a capture event may also generate an IRQ2
interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by
clearing its IMR bit D2 or use P20 as the input.
T8/T16_Logic/Edge_Detect
In Transmit Mode, this field defines how the outputs of T8 and T16 are combined
(AND, OR, NOR, NAND).
In Demodulation Mode, this field defines which edge should be detected by the
edge detector.
Transmit_Submode/Glitch Filter
In Transmit Mode, this field defines whether T8 and T16 are in the Ping-Pong
mode or in independent normal operation mode. Setting this field to “Normal
Operation Mode” terminates the “Ping-Pong Mode” operation. When set to 10,
T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1.
In Demodulation Mode, this field defines the width of the glitch that must be fil-
tered out.
Initial_T8_Out/Rising_Edge
In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the
output of T8 is set to 1 when it starts to count. When the counter is not enabled
and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This
ensures that when the clock is enabled, a transition occurs to the initial state set
by CTR1, D1.
In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the
input signal. In order to reset the mode, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it
is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in
Normal or Ping-Pong Mode (CTR1, D3; D2). When the counter is not enabled and
this bit is set, T16_OUT is set to the opposite state of this bit. This ensures that
when the clock is enabled, a transition occurs to the initial state set by CTR1, D0.
In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the
input signal. In order to reset it, a 1 should be written to this location.
Modifying CTR1 (D1 or D0) while the counters are enabled
causes unpredictable output from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register—CTR2(0D)02h
Table 12 lists and briefly describes the fields for this register.
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
31
T16_Enable
This field enables T16 when set to 1.
Single/Modulo-N
In Transmit Mode, when set to 0, the counter reloads the initial value when it
reaches the terminal count. When set to 1, the counter stops when the terminal
count is reached.
Table 12.CTR2(0D)02h: Counter/Timer16 Control Register
Field Bit Position Value Description
T16_Enable 7------- R
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Single/Modulo-N -6------ R/W
0
1
0
1
Transmit Mode
Modulo-N
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize
Edge
Time_Out --5----- R
W
0**
1
0
1
No Counter Timeout
Counter Timeout
Occurred
No Effect
Reset Flag to 0
T16 _Clock ---43--- R/W 00**
01
10
11
SCLK
SCLK/2
SCLK/4
SCLK/8
Capture_INT_Mask -----2-- R/W 0**
1
Disable Data Capture Int.
Enable Data Capture Int.
Counter_INT_Mask ------1- R/W 0* Disable Timeout Int.
Enable Timeout Int.
P35_Out -------0 R/W 0*
1
P35 as Port Output
T16 Output on P35
Note:
*Indicates the value upon Power-On Reset.
** Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
32
In Demodulation Mode, when set to 0, T16 captures and reloads on detection of
all the edges. When set to 1, T16 captures and detects on the first edge but
ignores the subsequent edges. For details, see the description of T16 Demodula-
tion Mode on page 40.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write
a 1 to this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
Counter_INT_Mask
Set this bit to allow an interrupt when T16 times out.
P35_Out
This bit defines whether P35 is used as a normal output pin or T16 output.
CTR3 T8/T16 Control Register—CTR3(0D)03h
Table 13 lists and briefly describes the fields for this register. This register allow
the T8 and T16 counters to be synchronized.
Table 13.CTR3(0D)03h T8/T16 Control Register
T16_Enable 7------- R
R
W
W
0*
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
T8 Enable -6------ R/W 0**
1
0
1
Counter Disabled
Counter Enabled
Stop Counter
Enable Counter
Sync Mode --5----- R/W 0*
1
Disable Sync Mode
Enable Sync Mode
Reserved ---43210 R/W 1
x
Always reads 11111
No Effect
*
Indicates the value upon Power-On Reset.
*
** Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
33
Counter/Timer Functional Blocks
Input Circuit
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–
D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is
detected. Glitches in the input signal that have a width less than specified (CTR1
D3, D2) are filtered out (see Figure 15).
Figure 15. Glitch Filter Circuitry
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is
1; if it is 1, T8_OUT is 0. See Figure 16.
MUX Glitch
Filter
Edge
Detector
P31
P20
Pos
Edge
Neg
Edge
CTR1
D5,D4
CTR1
D6
CTR1
D3, D2
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
34
Figure 16. Transmit Mode Flowchart
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
T8 (8-Bit)
Transmit Mode
No T8_Enable Bit Set
CTR0, D7
Yes
CTR1, D1
Value
Reset T8_Enable Bit
01
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
No T8_Timeout
Yes
Single Pass Single
Modulo-N
T8_OUT Value 0
Enable T8
No T8_Timeout
Yes
Pass?
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
1
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
35
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1).
If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In Single-Pass Mode (CTR0, D6), T8 counts down to 0 and stops,
T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt
can be generated if it is enabled (CTR0, D1). In Modulo-N Mode, upon reaching
terminal count, T8_OUT is toggled, but no interrupt is generated. From that point,
T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout sta-
tus bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One
cycle is complete. T8 then loads from TC8H or TC8L according to the T8_OUT
level and repeats the cycle. See Figure 17.
Figure 17. 8-Bit Counter/Timer Circuits
The values in TC8H or TC8L can be modified at any time. The new values take
effect when they are loaded.
To ensure known operation do not write these registers at
the time the values are to be loaded into the counter/timer.
An initial count of 1 is not allowed (a non-function occurs).
An initial count of 0 causes TC8 to count from 0 to FFh to
FEh.
CTR0 D1
Negative Edge
Positive Edge
Z8
®
Data Bus
IRQ4
CTR0 D2
SCLK
Z8® Data Bus
CTR0 D4, D3
Clock
T8_OUT
LO8
TC8H TC8L
Clock
Select
8-Bit
Counter T8
HI8
Caution:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
36
The letter h denotes hexadecimal values.
Transition from 0 to FFh is not a timeout condition.
Using the same instructions for stopping the counter/timers
and setting the status bits is not recommended.
Two successive commands are necessary. First, the counter/timers must be
stopped. Second, the status bits must be reset. These commands are required
because it takes one counter/timer clock interval for the initiated event to actually
occur. See Figure 18 and Figure 19.
Figure 18. T8_OUT in Single-Pass Mode
Figure 19. T8_OUT in Modulo-N Mode
T8 Demodulation Mode
The user must program TC8L and TC8H to FFh. After T8 is enabled, when the first
edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to
count down. When a subsequent edge (rising, falling, or both depending on
CTR1, D5; D4) is detected during counting, the current value of T8 is comple-
mented and put into one of the capture registers. If it is a positive edge, data is put
into LO8; if it is a negative edge, data is put into HI8. From that point, one of the
N
ote:
Caution:
TC8H
Counts
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
T8_OUT Toggles;
Timeout Interrupt
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
Timeout
Interrupt
Timeout
Interrupt
T8_OUT
T8_OUT Toggles
TC8L TC8H TC8H TC8LTC8L
...
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
37
edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if
enabled (CTR0, D2). Meanwhile, T8 is loaded with FFh and starts counting again.
If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be
generated if enabled (CTR0, D1). T8 then continues counting from FFh (see
Figure 21 and Figure 21).
Figure 20. Demodulation Mode Count Capture Flowchart
T8 (8-Bit)
Count Capture
T8 Enable
(Set by User)
No
Yes
Edge Present
What Kind
of Edge
T8 HI8
No
Yes
Negative
FFh T8
Positive
T8 LO8
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
38
Figure 21. Demodulation Mode Flowchart
T8 (8-Bit)
Capture Mode
T8 Enable
CTR0, D7
No
Yes
FFh→ TC8
First
Edge Present
Enable TC8
T8_Enable
Bit Set
Edge Present
T8 Timeout
Set Edge Present Status
Bit and Trigger Data
Capture Int. If Enabled
Set Timeout Status
Bit and Trigger
Timeout Int. If Enabled
Continue Counting
Disable TC8
No
Yes
No
Yes
Yes
Yes
No
No
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
39
T16 Transmit Mode
In Normal or Ping-Pong mode, the output of T16 when not enabled, is dependent
on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force
the output of T16 to either a 0 or 1 whether it is enabled or not by programming
CTR1 D3; D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched
to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled
(in NORMAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if
enabled), and a status bit (CTR2, D5) is set. See Figure 22.
Figure 22. 16-Bit Counter/Timer Circuits
Global interrupts override this function as described in
“Interrupts” on page 43.
If T16 is in Single-Pass mode, it is stopped at this point (see Figure 23). If it is in
Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting contin-
ues (see Figure 24).
The values in TC16H and TC16L can be modified at any time. The new values
take effect when they are loaded.
CTR2 D1
Negative Edge
Positive Edge
Z8® Data Bus
IRQ3
CTR2 D2
SCLK
Z8® Data Bus
CTR2 D4, D3
Clock
T16_OUT
LO16
TC16H TC16L
Clock
Select
16-Bit
Counter T16
HI16
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
40
Do not load these registers at the time the values are to be
loaded into the counter/timer to ensure known operation.
An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to FFFFh to FFFEh. Transition
from 0 to FFFFh is not a timeout condition.
Figure 23. T16_OUT in Single-Pass Mode
Figure 24. T16_OUT in Modulo-N Mode
T16 Demodulation Mode
The user must program TC16L and TC16H to FFh. After T16 is enabled, and the
first edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16
captures HI16 and LO16, reloads, and begins counting.
If D6 of CTR2 Is 0
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is
detected during counting, the current count in T16 is complemented and put into
HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1,
D1; D0) is set, and an interrupt is generated if enabled (CTR2, D2). T16 is loaded
with FFFFh and starts again.
This T16 mode is generally used to measure space time, the length of time
between bursts of carrier signal (marks).
Caution:
TC16H*256+TC16L Counts
“Counter Enable” Command
T16_OUT Switches to Its
Initial Value (CTR1 D0)
T16_OUT Toggles,
Timeout Interrupt
TC16H*256+TC16L
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Toggles,
Timeout Interrupt
“Counter Enable” Command,
T16_OUT Switches to Its
Initial Value (CTR1 D0)
TC16_OUT
...
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
41
If D6 of CTR2 Is 1
T16 ignores the subsequent edges in the input signal and continues counting
down. A timeout of T8 causes T16 to capture its current value and generate an
interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues
counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 cap-
tures and reloads on the next edge (rising, falling, or both depending on CTR1,
D5; D4), continuing to ignore subsequent edges.
This T16 mode generally measures mark time, the length of an active carrier sig-
nal burst.
If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit
(CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2
D1).
Ping-Pong Mode
This operation mode is only valid in Transmit Mode. T8 and T16 must be pro-
grammed in Single-Pass mode (CTR0, D6; CTR2, D6), and Ping-Pong mode
must be programmed in CTR1, D3; D2. The user can begin the operation by
enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled,
T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level,
TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is dis-
abled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0),
data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches
the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Inter-
rupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2,
D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See
Figure 25.
Enabling ping-pong operation while the counter/timers are
running might cause intermittent counter/timer function. Disable
the counter/timers and reset the status flags before instituting
this operation.
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
42
Figure 25. Ping-Pong Mode Diagram
Initiating Ping-Pong Mode
First, make sure both counter/timers are not running. Set T8 into Single-Pass
mode (CTR0, D6), set T16 into Single-Pass mode (CTR2, D6), and set the Ping-
Pong mode (CTR1, D2; D3). These instructions can be in random order. Finally,
start Ping-Pong mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See
Figure 25.
Figure 26. Output Circuit
The initial value of T8 or T16 must not be 1. If you stop the timer and restart the
timer, reload the initial value to avoid an unknown previous value.
Enable
TC8
Enable
Timeout
TC16
Ping-Pong
CTR1 D3,D2
Timeout
T16_OUT
MUX
CTR1 D3
T8_OUT
P34
AND/OR/NOR/NAND
Logic
MUX
MUX
MUX
P35
P36
P34_Internal
CTR1 D5, D4
P36_Internal
P35_Internal
CTR1, D2
CTR0 D0
CTR1 D6
CTR2 D0
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
43
During Ping-Pong Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alter-
nately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the
counter/timers reach the terminal count.
Timer Output
The output logic for the timers is illustrated in Figure 26. P34 is used to output T8-
OUT when D0 of CTR0 is set. P35 is used to output the value of T16-OUT when
D0 of CRTR2 is set. When D6 of CTR1 is et, P36 outputs the logic combination of
T8-OUT and T16-OUT determined by D5 and D4 of CTR1.
Interrupts
The CrimzonTM ZLR16300 features six different interrupts (Table 14). The inter-
rupts are maskable and prioritized (Figure 27). The six sources are divided as fol-
lows: three sources are claimed by Port 3 lines P33–P31, two by the counter/
timers (Table 14) and one for low voltage detection. The Interrupt Mask Register
(globally or individually) enables or disables the six interrupt requests.
The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M).
When in digital mode, Pin P33 is the source. When in analog mode the output of
the Stop Mode Recovery source logic is used as the source for the interrupt. See
Figure 32, Stop Mode Recovery Source, on page 52.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
44
Figure 27. Interrupt Block Diagram
Low-Voltage
Detection
Timer 8
Timer 16
Interrupt Edge
Select
IMR
IPR
Priority
Logic
IRQ
6
IRQ2 IRQ0 IRQ1 IRQ3 IRQ4 IRQ5
P31 P32
IRQ Register
D6, D7
Global
Interrupt
Enable
Interrupt
Request
Vector Select
D1 of P3M Register
P33
01
Stop Mode Recovery Source
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
45
When more than one interrupt is pending, priorities are resolved by a programma-
ble priority encoder controlled by the Interrupt Priority Register. An interrupt
machine cycle activates when an interrupt request is granted. As a result, all sub-
sequent interrupts are disabled, and the Program Counter and Status Flags are
saved. The cycle then branches to the program memory vector location reserved
for that interrupt. All CrimzonTM ZLR16300 interrupts are vectored through loca-
tions in the program memory. This memory location and the next byte contain the
16-bit address of the interrupt service routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs are masked, and the
Interrupt Request register is polled to determine which of the interrupt requests
require service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered. These interrupts are programmable by the user. The software can poll
to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register
(R250), bits D7 and D6. The configuration is indicated in Table 15.
Table 14.Interrupt Types, Sources, and Vectors
Name Source Vector Location Comments
IRQ0 P32 0,1 External (P32), Rising, Falling Edge Triggered
IRQ1 P33 2,3 External (P33), Falling Edge Triggered
IRQ2 P31, TIN 4,5 External (P31), Rising, Falling Edge Triggered
IRQ3 T16 6,7 Internal
IRQ4 T8 8,9 Internal
IRQ5 LVD 10,11 Internal
Table 15.IRQ Register
IRQ Interrupt Edge
D7 D6 IRQ2 (P31) IRQ0 (P32)
00F F
01F R
10R F
11R/F R/F
Note: F = Falling Edge; R = Rising Edge
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
46
Clock
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for
connection to a crystal, ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz
maximum, with a series resistance (RS) less than or equal to 100 Ω. The on-chip
oscillator can be driven with a suitable external clock source.
The crystal must be connected across XTAL1 and XTAL2 using the recommended
capacitors (capacitance greater than or equal to 22 pF) from each pin to ground.
Figure 28. Oscillator Configuration
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the
Power-On Reset (POR) timer function. The POR time allows VDD and the oscilla-
tor circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
Power Fail to Power OK status, including Waking up from VBO Standby
•
Stop-Mode Recovery (if D5 of SMR = 1)
•
WDT Timeout
C1
C2
XTAL1
XTAL2
XTAL1
XTAL2
XTAL1
XTAL2
Crystal
C1, C2 = 33 pF TYP*
f = 8MHz
* Preliminary value including pin parasitics
External Clock
Ceramic Resonator
f = 8MHz
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
47
The POR timer is 2.5 ms minimum. Bit 5 of the Stop-Mode Register determines
whether the POR timer is bypassed after Stop-Mode Recovery (typical for external
clock).
Halt Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5
remain active. The devices are recovered by interrupts, either externally or inter-
nally generated. An interrupt request must be executed (enabled) to exit Halt
Mode. After the interrupt service routine, the program continues from the instruc-
tion after the Halt.
Stop Mode
This instruction turns off the internal clock and external crystal oscillation, reduc-
ing the standby current to 10 µA or less. Stop Mode is terminated only by a reset,
such as WDT timeout, POR or SMR. This condition causes the processor to
restart the application program at address 000Ch. In order to enter Stop (or Halt)
mode, first flush the instruction pipeline to avoid suspending execution in mid-
instruction. Execute an NOP instruction (Opcode = FFh) immediately before the
appropriate sleep instruction, as follows:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
48
FF NOP ; clear the pipeline
6F STOP ; enter Stop Mode
or
FF NOP ; clear the pipeline
7F HALT ; enter Halt Mode
Port Configuration Register
The Port Configuration (PCON) register (Figure 29) configures the comparator
output on Port 3. It is located in the expanded register file at Bank F, location 00.
PCON (0F) 00H
Figure 29. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the compar-
ator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configu-
ration.
Port 0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Reserved (Must be 1)
Port 0
0: Open-Drain
1: Push-Pull*
Reserved (Must be 1)
* Default setting after reset
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
49
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop
Mode Recovery (Figure 30). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of Stop recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input (Figure 32 on page 52) is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4 of the SMR register spec-
ify the source of the Stop-Mode Recovery signal. Bits D0 determines if SCLK/
TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded
Register File at address 0Bh.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
50
SMR (0F) 0BH
Figure 30. Stop Mode Recovery Register
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 31). This
control selectively reduces device power consumption during normal processor
execution (SCLK control) and/or Halt Mode (where TCLK sources interrupt logic).
After Stop-Mode Recovery, this bit is set to 0.
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
* Default after Power On Reset or Watch-Dog Reset
* * Default setting after Reset and Stop Mode Recovery
* * * At the XOR gate input
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
51
Figure 31. SCLK Circuit
Stop-Mode Recovery Register 2—SMR2(0F)0DH
Table 16 lists and describes the fields for this register.
Stop-Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the Stop recovery
(Figure 32 and Table 17).
Table 16.SMR2(F)0DH:Stop Mode Recovery Register 2*
Field Bit Position Value Description
Reserved 7------- 0 Reserved (Must be 0)
Recovery Level -6------ W0
†
1
Low
High
Reserved --5----- 0 Reserved (Must be 0)
Source ---432-- W 000†
001
010
011
100
101
110
111
A. POR Only
B. NAND of P23–P20
C. NAND of P27–P20
D. NOR of P33–P31
E. NAND of P33–P31
F. NOR of P33–P31, P00, P07
G. NAND of P33–P31, P00, P07
H. NAND of P33–P31, P22–P20
Reserved ------10 00 Reserved (Must be 0)
Notes:
* Port pins configured as outputs are ignored as an SMR recovery source.
† Indicates the value at Power-On Reset
SCLK
TCLKSMR, D0
2
÷
OSC
16÷
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
52
Figure 32. Stop Mode Recovery Source
SMR2 D4 D3 D2
100
SMR2 D4 D3 D2
111
SMR D4D3D2
010
SMR D4D3D2
111
SMR D4D3D2
101
SMR D4D3D2
100
SMR D4D3D2
011
SMR D4D3D2
000
SMR D4D3D2
110
VCC
P31
P32
P33
P27
P20
P23
P20
P27
SMR2 D4 D3 D2
001
SMR2 D4 D3 D2
000
SMR2 D4 D3 D2
010
SMR2 D4 D3 D2
011
SMR2 D4 D3 D2
101
SMR2 D4 D3 D2
110
VCC
P20
P23
P20
P27
P31
P32
P33
P31
P32
P33
P31
P32
P33
P00
P07
P31
P32
P33
P00
P07
P31
P32
P33
P20
P21
SMR D6
SMR2 D6
To RESET and WDT
Circuitry (Active Low)
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
53
Any Port 2 bit defined as an output drives the corresponding
input to the default state. This condition allows the remaining
inputs to control the AND/OR function. Refer to SMR2 register
on page 54 for other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if Low, disables the TPOR delay after Stop Mode Recovery. The default
configuration of this bit is 1. If the “fast” wake up is selected, the Stop Mode
Recovery source must be kept active for at least 10 TpC.
This bit must be set to 1 if using a crystal or resonator clock
source. The TPOR delay allows the clock source to stabilize
before executing instructions.
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery
sources wakes the CrimzonTM ZLR16300 from Stop Mode. A 0 indicates Low
level recovery. The default is 0 on POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from Stop Mode.
The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR).
Table 17.Stop Mode Recovery Source
SMR:432 Operation
D4 D3 D2 Description of Action
0 0 0 POR and/or external reset recovery
001Reserved
010P31 transition
011P32 transition
100P33 transition
101P27 transition
1 1 0 Logical NOR of P20 through P23
1 1 1 Logical NOR of P20 through P27
Note:
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
54
Stop Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop Mode Recovery for SMR2 (Figure 33).
SMR2 (0F) DH
Figure 33. Stop Mode Recovery Register 2 ((0F) DH:D2–D4, D6 Write Only)
If SMR2 is used in conjunction with SMR, either of the specified events causes a
Stop Mode Recovery.
Port pins configured as outputs are ignored as an SMR or
SMR2 recovery source. For example, if the NAND or P23–P20
is selected as the recovery source and P20 is configured as an
output, the remaining SMR pins (P23–P21) form the NAND
equation.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0Low *
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
* Default setting after reset
* * At the XOR gate input
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
55
Watch-Dog Timer Mode Register (WDTMR)
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8
if it reaches its terminal count. The WDT must initially be enabled by executing the
WDT instruction. On subsequent executions of the WDT instruction, the WDT is
refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT
instruction affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register
control a tap circuit that determines the minimum timeout period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
STOP. Bits 4 through 7 are reserved (Figure 34). This register is accessible only
during the first 60 processor cycles (120 XTAL clocks) from the execution of the
first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode
Recovery (Figure 33). After this point, the register cannot be modified by any
means (intentional or otherwise). The WDTMR cannot be read. The register is
located in Bank F of the Expanded Register File at address location 0Fh. It is
organized as illustrated in Figure 34.
WDTMR (0F) 0FH
Figure 34. Watch-Dog Timer Mode Register (Write Only)
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in Table 18.
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 10 ms min.
01* 20 ms min.
10 40 ms min.
11 160 ms min.
WDT During Halt
0OFF
1ON *
WDT During Stop
0OFF
1ON *
Reserved (Must be 0)
* Default setting after reset
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
56
WDTMR During Halt (D2)
This bit determines whether or not the WDT is active during Halt Mode. A 1 indi-
cates active during Halt. The default is 1. See Figure 35.
Figure 35. Resets and WDT
Table 18.Watch-Dog Timer Time Select
D1 D0 Timeout of Internal RC-Oscillator
0010 ms min.
0120 ms min.
1040 ms min.
1 1 160 ms min.
-
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High
input translation.
+
From Stop
Mode
Recovery
Source
Stop Delay
Select (SMR)
5 Clock Filter *CLR2 18 Clock RESET
CLK Generator RESET
WDT TAP SELECT
POR 10 ms 20 ms 40 ms 160 ms
CLK
*CLR1 WDT/POR Counter Chain
Internal
RC
Oscillator.
WDT
VDD
Low Operating
Voltage Det.
VBO
VDD
Internal
RESET
Active
High
12-ns Glitch Filter
XTAL
CrimzonTMZLR16300
Product Specification
PS021410-0605 Functional Description
57
WDTMR During Stop (D3)
This bit determines whether or not the WDT is active during Stop Mode. A 1 indi-
cates active during Stop. The default is 1.
ROM Selectable Options
There are five ROM Selectable Options to choose from based on ROM code
requirements. These options are listed in Table 19.
Voltage Brown-Out/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for
correct operation of the device. Reset is globally driven when VDD falls below VBO.
A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or
resonator clock. If the VDD is allowed to stay above VRAM, the RAM content is pre-
served. When the power level is returned to above VBO, the device performs a
POR and functions normally.
Low-Voltage Detection Register—LVD(0D)0CH
Voltage detection does not work at Stop mode. It must be
disabled during Stop mode in order to reduce current.
Table 19.ROM Selectable Options
Port 00–03 Pull-Ups On/Off
Port 04–07 Pull-Ups On/Off
Port 20–27 Pull-Up Port 3 Pull-Ups On/Off
Port 3 Pull-Ups On/Off
Watch-Dog Timer at Power-On Reset On/Off
Field Bit Position Description
LVD 765432--- Reserved
-----2 R 1
0*
HVD flag set
HVD flag reset
------1- R 1
0*
LVD flag set
LVD flag reset
-------0 R/W 1
0*
Enable VD
Disable VD
*
Default after POR
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0D)
58
Do not modify register P01M while checking a low-voltage
condition. Switching noise of both ports 0 and 1 together might
trigger the LVD flag.
Voltage Detection and Flags
The Voltage Detection register (LVD, register 0Ch at the expanded register bank
0Dh) offers an option of monitoring the VCC voltage. The Voltage Detection is
enabled when bit 0 of LVD register is set. When Voltage Detection is enabled, the
the VCC level is monitored in real time. The flags in the LVD register valid 20uS
after Voltage Detection is enabled. The HVD flag (bit 2 of the LVD register) is set
only if VCC is lower than the VHVD. When Voltage Detection is enabled, the LVD
flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is
cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the
IMR register. Otherwise, bit 5 of IRQ register is latched as a flag only.
If it is necessary to receive an LVD interrupt upon power-up at
an operating voltage lower than the low battery detect
threshold, enable interrupts using the Enable Interrupt
instruction (EI) prior to enabling the voltage detection.
Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are depicted in Figure 36 through
Figure 40.
Note:
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0D)
59
Figure 36. TC8 Control Register ((0D) 00H: Read/Write Except Where Noted)
CTR0 (0D) 00H
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt**
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture Interrupt**
1 Enable T8 Data Capture Interrupt
00 SCLK on T8**
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8
R 0 No T8 Counter Timeout**
R 1 T8 Counter Timeout Occurred
W 0 No Effect
W 1 Reset Flag to 0
0 Modulo-N*
1 Single Pass
R 0 T8 Disabled *
R 1 T8 Enabled
W0 Stop T8
W 1 Enable T8
* Default setting after reset.
** Default setting after Reset. Not reset with a Stop Mode recovery
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0D)
60
Figure 37. T8 and T16 Common Control Functions ((0D) 01H: Read/Write)
CTR1 (0D) 01H
D7 D6 D5 D4 D3 D2 D1 D0
Transmit Mode*
R/W 0 T16_OUT is 0 initially*
1 T16_OUT is 1 initially
Capture Mode
R 0 No Falling Edge Detection
R 1 Falling Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode*
R/W 0 T8_OUT is 0 initially*
1 T8_OUT is 1 initially
Capture Mode
R 0 No Rising Edge Detection
R 1 Rising Edge Detection
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode*
0 0 Normal Operation*
0 1 Ping-Pong Mode
1 0 T16_OUT = 0
1 1 T16_OUT = 1
Capture Mode
0 0 No Filter
0 1 4 SCLK Cycle Filter
1 0 8 SCLK Cycle Filter
11Reserved
Transmit Mode/T8/T16 Logic
0 0 AND**
01OR
1 0 NOR
1 1 NAND
Capture Mode
0 0 Falling Edge Detection
01Rising Edge Detection
1 0 Both Edge Detection
11Reserved
Transmit Mode
0 P36 as Port Output *
1 P36 as T8/T16_OUT
Capture Mode
0 P31 as Demodulator Input
1 P20 as Demodulator Input
Transmit/Capture Mode
0 Transmit Mode *
1 Capture Mode
* Default setting after reset.
** Default setting after Reset. Not reset with a Stop Mode
recovery.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0D)
61
Take care in differentiating the Transmit Mode from Capture
Mode. Depending on which of these two modes is operating,
the CTR1 bit has different functions.
Changing from one mode to another cannot be performed
without disabling the counter/timers.
CTR2 (0D) 02H
Figure 38. T16 Control Register ((0D) 02H: Read/Write Except Where Noted)
D7 D6 D5 D4 D3 D2 D1 D0
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt*
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture Interrupt**
1 Enable T16 Data Capture Interrupt
0 0 SCLK on T16**
0 1 SCLK/2 on T16
1 0 SCLK/4 on T16
1 1 SCLK/8 on T16
R 0 No T16 Timeout**
R 1 T16 Timeout Occurs
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode
0 Modulo-N for T16*
1 Single Pass for T16
Capture Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
R 0 T16 Disabled *
R 1 T16 Enabled
W 0 Stop T16
W1Enable T16
* Default setting after reset.
** Default setting after Reset. Not reset with a
Stop Mode recovery.
Notes:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0D)
62
CTR3 (0D) 03H
Figure 39. T8/T16 control Register (0D) 03H: Read/Write (Except Where Noted)
If Sync Mode is enabled, the first pulse of T8 (carrier) is always
synchronized with T16 (demodulated signal). It can always
provide a full carrier pulse.
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
No effect when written
Always reads 11111
Sync Mode
0 Disable Sync Mode**
1 Enable Sync Mode
T8 Enable
R 0* T8 Disabled
R 1 T8 Enabled
W 0 Stop T8
W 1 Enable T8
T16 Enable
R 0* T16 Disabled
R 1 T16 Enabled
W 0 Stop T16
W 1 Enable T16
* Default setting after reset.
** Default setting after reset. Not reset after Stop
Mode recovery
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0F)
63
LVD (0D) 0CH
Figure 40. Voltage Detection Register
Expanded Register File Control Registers (0F)
The expanded register file control registers (0F) are depicted in Figures 41
through Figure 54.
D7 D6 D5 D4 D3 D2 D1 D0
Voltage Detection
0: Disable *
1: Enable
LVD Flag (Read only)
0: LVD flag reset *
1: LVD flag set
HVD Flag (Read only)
0: HVD flag reset *
1: HVD flag set
Reserved (Must be 0)
* Default setting after reset.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0F)
64
PCON (0F) 00H
Figure 41. Port Configuration Register (PCON) ((0F)00H: Write Only
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output *
1 P34, P37 Comparator Output
Reserved. (Must be 1)
Port 0
0: Open-Drain
1: Push-Pull *
Reserved (Must be 1)
* Default setting after reset
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0F)
65
SMR (0F) 0BH
Figure 42. Stop Mode Recovery Register ((0F) 0BH: D6–D0=Write Only, D7=Read
Only)
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only* *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low**
1 High
Stop Flag
0 POR * * * * *
1 Stop Recovery * *
* Default setting after Reset
* * Set after STOP Mode Recovery
* * * At the XOR gate input
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.
Not reset with a Stop Mode recovery.
* * * * * Default setting after Power On Reset
CrimzonTMZLR16300
Product Specification
PS021410-0605 Expanded Register File Control Registers (0F)
66
SMR2 (0F) 0DH
Figure 43. Stop Mode Recovery Register 2 ((0F) 0DH: D2–D4, D6 Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0Low
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
* Default setting after reset. Not reset with a Stop Mode recovery.
* * At the XOR gate input
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Control Registers
67
WDTMR (0F) 0FH
Figure 44. Watch-Dog Timer Register ((0F) 0FH: Write Only)
Standard Control Registers
R246 P2M (F6H)
Figure 45. Port 2 Mode Register (F6H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00 10 ms min.
01 20 ms min.*
10 40 ms min.
11 80 ms min.
WDT During Halt
0OFF
1ON *
WDT During Stop
0OFF
1ON *
Reserved (Must be 0)
* Default setting after reset. Not reset with a Stop Mode recovery.
D7 D6 D5 D4 D3 D2 D1 D0
P27–P20 I/O Definition
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
* Default setting after reset. Not reset with a Stop Mode recovery.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Control Registers
68
R247 P3M (F7H)
Figure 46. Port 3 Mode Register (F7H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
0: Port 2 Open Drain *
1: Port 2 Push-Pull
0= P31, P32 Digital Mode*
1= P31, P32 Analog Mode
Reserved (Must be 0)
* Default setting after reset. Not reset with a Stop Mode recovery.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Control Registers
69
R248 P01M (F8H)
Figure 47. Port 0 Register (F8H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
0: Output
1: Input *
Reserved (Must be 0)
Reserved (Must be 1)
Reserved (Must be 0)
P07–P04 Mode
0: Output
1: Input *
Reserved (Must be 0)
* Default setting after reset; only P00, P01 and P07 are available on 20-pin
configurations.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Control Registers
70
R249 IPR (F9H)
Figure 48. Interrupt Priority Register (F9H: Write Only)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4, Priority
(Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2, Priority
(Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5, Priority
(Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved; must be 0
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Control Registers
71
R250 IRQ (FAH)
Figure 49. Interrupt Request Register (FAH: Read/Write)
R251 IMR (FBH)
Figure 50. Interrupt Mask Register (FBH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
IRQ5 = LVD
Inter Edge
P31↓P32↓ = 00
P31↓P32↑ = 01
P31↑P32↓ = 10
P31↑↓ P32↑↓ = 11
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5–IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
0 Master Interrupt Disable *
1 Master Interrupt Enable * *
* Default setting after reset
* * Only by using EI, DI instruction; DI is required before changing the IMR register
CrimzonTMZLR16300
Product Specification
PS021410-0605 Standard Control Registers
72
R252 Flags (FCH)
Figure 51. Flag Register (FCH: Read/Write)
R253 RP (FDH)
Figure 52. Register Pointer (FDH: Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Tag
Zero Flag
Carry Flag
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank Pointer
Working Register Pointer
Default setting after reset = 0000 0000
CrimzonTMZLR16300
Product Specification
PS021410-0605 Package Information
73
R254 SPH (FEH)
Figure 53. Stack Pointer High (FEH: Read/Write)
R255 SPL (FFH)
Figure 54. Stack Pointer Low (FFH: Read/Write)
Package Information
Package information for all device versions of ZGR16300 is depicted in Figures
55 through Figure 60.
D7 D6 D5 D4 D3 D2 D1 D0
General-Purpose Register
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Low
Byte (SP7–SP0)
CrimzonTMZLR16300
Product Specification
PS021410-0605 Package Information
74
Figure 55. 20-Pin DIP Package Diagram
Figure 56. 20-Pin SOIC Package Diagram
CrimzonTMZLR16300
Product Specification
PS021410-0605 Package Information
75
Figure 57. 20-Pin SSOP Package Diagram
CrimzonTMZLR16300
Product Specification
PS021410-0605 Package Information
76
Figure 58. 28-Pin SOIC Package Diagram
CrimzonTMZLR16300
Product Specification
PS021410-0605 Package Information
77
Figure 59. 28-Pin DIP Package Diagram
CrimzonTMZLR16300
Product Specification
PS021410-0605 Ordering Information
78
Figure 60. 28-Pin SSOP Package Diagram
Please check with ZiLOG® on the actual bonding diagram and
coordinate for chip-on-board assembly.
Ordering Information
The following table provides ordering information for the ZLR16300 16K, 8K, 4K,
2K, and 1K parts.
SYMBOL
A
A1
B
C
A2
e
MILLIMETER INCH
MIN MAX MIN MAX
1.73
0.05
1.68
0.25
5.20
0.65 TYP
0.09
10.07
7.65
0.63
1.86
0.0256 TYP
0.13
10.20
1.73
7.80
5.30
1.99
0.21
1.78
0.75
0.068
0.002
0.066
0.010
0.205
0.004
0.397
0.301
0.025
0.073
0.005
0.068
0.209
0.006
0.402
0.307
0.030
0.078
0.008
0.070
0.015
0.212
0.008
0.407
0.311
0.037
0.38
0.20
10.33
5.38
7.90
0.95
NOM NOM
D
E
H
L
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES .
H
C
DETAIL A
E
D
28 15
114
SEATING PLANE
A2
e
A
Q1
A1
B
L
0 - 8
DETAIL 'A'
Note:
CrimzonTMZLR16300
Product Specification
PS021410-0605 Ordering Information
79
Memory Size Part No. Description
16K ZLR16300H2816C 28-pin SSOP 16K ROM
ZLR16300P2816C 28-pin PDIP 16K ROM
ZLR16300S2816C 28-pin SOIC 16K ROM
ZLR16300H2016C 20-pin SSOP 16K ROM
ZLR16300P2016C 20-pin PDIP 16K ROM
ZLR16300S2016C 20-pin SOIC 16K ROM
8K ZLR16300H2808C 28-pin SSOP 8K ROM
ZLR16300P2808C 28-pin PDIP 8K ROM
ZLR16300S2808C 28-pin SOIC 8K ROM
ZLR16300H2008C 20-pin SSOP 8K ROM
ZLR16300P2008C 20-pin PDIP 8K ROM
ZLR16300S2008C 20-pin SOIC 8K ROM
4K ZLR16300H2804C 28-pin SSOP 4K ROM
ZLR16300P2804C 28-pin PDIP 4K ROM
ZLR16300S2804C 28-pin SOIC 4K ROM
ZLR16300H2004C 20-pin SSOP 4K ROM
ZLR16300P2004C 20-pin PDIP 4K ROM
ZLR16300S2004C 20-pin SOIC 4K ROM
2K ZLR16300H2802C 28-pin SSOP 2K ROM
ZLR16300P2802C 28-pin PDIP 2K ROM
ZLR16300S2802C 28-pin SOIC 2K ROM
ZLR16300H2002C 20-pin SSOP 2K ROM
ZLR16300P2002C 20-pin PDIP 2K ROM
ZLR16300S2002C 20-pin SOIC 2K ROM
1K ZLR16300H2801C 28-pin SSOP 1K ROM
ZLR16300P2801C 28-pin PDIP 1K ROM
ZLR16300S2801C 28-pin SOIC 1K ROM
ZLR16300H2001C 20-pin SSOP 1K ROM
ZLR16300P2001C 20-pin PDIP 1K ROM
ZLR16300S2001C 20-pin SOIC 1K ROM
ZLP32300100KIT Development System
ZLP323ICE01ZEM Emulator
Note:
1. Replace C with G for Lead-Free Packaging.
2. Contact www.zilog.com for the die form.
CrimzonTMZLR16300
Product Specification
PS021410-0605 Ordering Information
80
For fast results, contact your local ZiLOG sales office for assistance in ordering
the part desired.
Codes
ZL = ZiLOG Low Voltage Family
R = ROM
16300 = Family Designation
P = Package Type:
H = SSOP
P = Plastic DIP
S = SOIC
## = Number of Pins
CC = Memory Size
X = Molding Compound
Example
ZL R 16300 P 28 16 C
Molding Compound
Memory Size
Number of Pins
Package Type
Family Designation
ROM
ZiLOG Low Voltage
Family
CrimzonTM ZLR16300
Product Specification
PS021410-0605 Index
81
Index
Numerics
16-bit counter/timer circuits 39
20-pin DIP package diagram 74
20-pin SSOP package diagram 75
28-pin DIP package diagram 77
28-pin SOICpackage diagram 76
28-pin SSOP package diagram 78
8-bit counter/timer circuits 35
A
absolute maximum ratings 6
AC
characteristics 10
timing diagram 10
address spaces, basic 2
architecture 2
expanded register file 21
B
basic address spaces 2
block diagram, ZLR16300 functional 3
C
capacitance 8
capture_INT_mask 27, 32
characteristics
AC 10
DC 8
clock 46
comparator inputs/outputs 18
configuration
port 0 13
port 2 14
port 3 15
port 3 counter/timer 17
counter/timer
16-bit circuits 39
8-bit circuits 35
brown-out voltage/standby 57
clock 46
demodulation mode count capture flow-
chart 37
demodulation mode flowchart 38
EPROM selectable options 57
glitch filter circuitry 33
halt instruction 47
input circuit 33
interrupt block diagram 44
interrupt types, sources and vectors 45
oscillator configuration 46
output circuit 42
ping-pong mode 41
port configuration register 48
resets and WDT 56
SCLK circuit 51
stop instruction 47
stop mode recovery register 50
stop mode recovery register 2 54
stop mode recovery source 52
T16 demodulation mode 40
T16 transmit mode 39
T16_OUT in modulo-N mode 40
T16_OUT in single-pass mode 40
T8 demodulation mode 36
T8 transmit mode 33
T8_OUT in modulo-N mode 36
T8_OUT in single-pass mode 36
transmit mode flowchart 34
voltage detection and flags 58
watch-dog timer mode register 55
watch-dog timer time select 56
counter/timer functional blocks
input circuit 33
T8 transmit mode 33
counter_INT_mask 32
crt3 T8/T16 control register
register 32
CrimzonTM ZLR16300
Product Specification
PS021410-0605 Index
82
CTR(D)01h T8 and T16 common functions 28
CTR1 (0D)01 27
CTR3 T8/T16 control CTR3(0D)03h 32
D
DC characteristics 8
demodulation mode
count capture flowchart 37
flowchart 38
T16 40
T8 36
description
functional 18
general 2
pin 5
E
EPROM
selectable options 57
expanded register file 20
expanded register file architecture 21
expanded register file control registers 63
flag 72
interrupt mask register 71
interrupt priority register 70
interrupt request register 71
port 0 and 1 mode register 69
port 2 configuration register 67
port 3 mode register 68
port configuration register 67
register pointer 72
stack pointer high register 73
stack pointer low register 73
stop-mode recovery register 65
stop-mode recovery register 2 66
T16 control register 61
T8 and T16 common control functions reg-
ister 60
TC8 control register 58
watch-dog timer register 67
F
features
standby modes 1
ZLR16300 1
functional description
counter/timer functional blocks 33
CTR0(0D)00h register 26
CTR1(0D)01h register 28
CTR2(0D)02h register 30
expanded register file 20
expanded register file architecture 21
HI16(0D)09h register 25
HI8(0D)0Bh register 25
L08(0D)0Ah register 25
L0I6(0D)08h register 25
program memory map 19
RAM 18
register description 57
register file 23
register pointer 22
register pointer detail 24
stack 24
TC16H(0D)07h register 25
TC16L(0D)06h register 26
TC8H(0D)05h register 26
TC8L(0D)04h register 26
TC8L(D)04h register 26
G
glitch filter circuitry 33
H
halt instruction, counter/timer 47
I
input circuit 33
interrupt block diagram, counter/timer 44
interrupt types, sources and vectors 45
CrimzonTM ZLR16300
Product Specification
PS021410-0605 Index
83
L
low-voltage detection register 57
M
memory, program 18
modulo-N mode
T16_OUT 40
T8_OUT 36
O
oscillator configuration 46
output circuit, counter/timer 42
P
P34_out 27
P35_out 32
P36_out/demodulator input 29
package information
20-pin DIP package diagram 74
20-pin SSOP package diagram 75
28-pin DIP package diagram 77
28-pin SOIC package diagram 76
28-pin SSOP package diagram 78
pin configuration
20-pin DIP/SOIC/SSOP 5
28-pin DIP/SOIC/SSOP 6
pin functions
port 0 (P07 - P00) 12
port 0 configuration 13
port 2 (P27 - P20) 13
port 2 (P37 - P30) 14
port 2 configuration 14
port 3 configuration 15
port 3 counter/timer configuration 17
XTAL1 (time-based input 12
XTAL2 (time-based output) 12
ping-pong mode 41
port 0
configuration 13
pin function 12
port 2
configuration 14
pin function 13
port 3
configuration 15
counter/timer configuration 17
port 3 pin function 14
port configuration register 48
power connections 2
power supply 5
program memory 18
map 19
R
ratings, absolute maximum 6
register 54
CTR0(0D)00h 26
CTR1 (0D) 01 27
CTR1(0D)01h 28
CTR2(0D)02h 30
flag 72
HI16(0D)09h 25
HI8(0D)0Bh 25
interrupt priority 70
interrupt request 71
interruptmask 71
L016(0D)08h 25
L08(0D)0Ah 25
LVD(D)0Ch 57
pointer 72
port 0 and 1 69
port 2 configuration 67
port 3 mode 68
port configuration 48, 67
stack pointer high 73
stack pointer low 73
stop mode recovery 50
stop mode recovery 2 54
stop-mode recovery 65
stop-mode recovery 2 66
T16 control 61
T8 and T16 common control functions 60
TC16H(0D)07h 25
CrimzonTM ZLR16300
Product Specification
PS021410-0605 Index
84
TC16L(0D)06h 26
TC8 control 58
TC8H(0D)05h 26
TC8L(0D)04h 26
TC8L(D)04h 26
voltage detection 63
watch-dog timer 67
register description
counter/timer2 LS-Byte hold 26
counter/timer2 MS-Byte hold 25
counter/timer8 control 26
counter/timer8 High hold 26
counter/timer8 Low hold 26
CTR2 counter/timer 16 control 30
T16_capture_LO 25
T8 and T16 common functions 28
T8_Capture_HI 25
T8_capture_LO 25
register file 23
expanded 20
register pointer 22
detail 24
resets and WDT 56
S
SCLK circuit 51
single/modulo-N 27, 31
single-pass mode
T16_OUT 40
T8_OUT 36
stack 24
standard test conditions 7
standby modes 1
stop instruction, counter/timer 47
stop mode recovery
2 register 54
source 52
stop mode recovery 2 54
stop mode recovery register 50
T
T 16 clock 32
T16 enable 31
T16 initial out/falling edge 30
T16 transmit mode 39
T16_capture_HI 25
T8 and T16 common functions 27
t8 clock 27
T8 enable 27
T8 intiial out/rising edge 30
T8 transmit mode 33
T8/T16_logic/edge_detect 30
T8_Capture_HI 25
test conditions, standard 7
test load diagram 7
time_out 32
timeout 27
timers
counter/timer2 LS-byte hold 26
counter/timer2 MS-byte hold 25
counter/timer8 high hold 26
counter/timer8 low hold 26
CTR0 counter/timer8 control 26
T16_Capture_HI 25
T16_Capture_LO 25
T8_Capture_HI 25
T8_Capture_LO 25
timing diagram, AC 10
transmit mode flowchart 34
transmit_submode/glitch filter 30
V
VCC 5
voltage
brown-out/standby 57
detection and flags 58
voltage detection register 63
CrimzonTM ZLR16300
Product Specification
PS021410-0605 Index
85
W
watch-dog timer
mode registerwatch-dog timer mode regis-
ter 55
time select 56
X
XTAL1 5
XTAL1 pin function 12
XTAL2 5
XTAL2 pin function 12
Z
ZLR16300 family members 1