Description
The 3842A(AM)/43A(AM)/44A(AM)/45A(AM) are fixed frequency current mode PWM controller. They are specially designed
for
OFF
−
Line and DC to DC converter applications with a minimal external components. Internally implemented circuits include a
trimmed
oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comp
arator,
and a high current totempole output ideally suited for driving a power MOSFET. Protection circuitry includes built undervoltage
lockout
and current limiting. The 3842A(AM) and 3844A(AM) have UVLO thresholds of 16 V (on) and 10 V (off). The
corresponding
thresholds for the 3843A(AM)/45A(AM) are 8.4V (on) and 7.6V(off). The MIK3842A(AM) and MIK3843A(AM) can operate within 100% dut
y
cycle. The 3844A(AM) and UC3845A(AM) can operate within 50% duty cycle.
The 384XA(AM) has Start-Up Current 0.17mA (typ).
Fea
•
Low Start-Up and Operating Current
•
High Current Totem Pole Output
•
Undervoltage Lockout With Hysteresis
•
Operating Frequency Up To 300KHz (384XA)
500KHz (384XAM
)
Pin
Connection
Block diagram
(toggle flip flop used onl
y
in MIK3844, MIK3845)
T
op
view
7
8
V
5V
V
REF SET
/
R
E
S
E
T
U
V
L
O
36V GND
5
2
1
V
FB
CO
M
P
IN
T
E
RN
A
L
BIAS
1/
2
V
REF
+
ER
R
V
RE
GOOD
F
LOGI
C
2R
C.
S
.
CO
M
P
1V
R
R
P
W
M
L
A
T
C
H
POWER
V
CC
7
OU
T
6
3
CUR
R
E
N
T
SEN
S
E
R /
C
T
O
S
C
I
LL
A
T
O
R
S
T
5
PO
W
E
R
G
N
D
Absolute Maximum Ratings
Symbol Parameter Maximum Units
V
CC
Supply Voltage (low impedance source) 30 V
I
O
Output Current ±1 A
V
I
Input Voltage (Analog Inputs pins 2,3)
−
0.3 to 5.5 V
I
SINK (E.A)
Error Amp Output Sink Current 10 mA
Po Power Dissipation (T
A
=25
0
C) 1 WW
Tstg Storage Temperature Range -65 to150
o
C
o
C
T
L
Lead Temperature (soldering 5 sec.)
260
1
BE
IJI
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ES
T
E
K
ELE
CTR
O
N
I
C
S C
O
.,
L
T
D
Electrical characteristics
(*VCC=15V, RT=10kΩ, CT=3.3nF, TA=00C to +700C, unless otherwise specified)
Characteristics Symbol Test Conditions Min Typ Max Units
Reference Section
Reference Output Voltage V
REF
T
J
= 25°C, I
RE
F
= 1 mA 4.9 5.0 5.1 V
Line Regulation ∆V
REF
12V ≤V
CC
≤25 V 6.0 20
Load Regulation
∆
V
RE
F
1 mA
≤
I
REF
≤
20mA
6.0
25
mV
Short Circuit Output Current I
SC
T
A
= 25°C -100 -180 mA
Oscillator
Section
O
scillation Frequency
f T
J
= 25°C
MIK384XA
47
50
57
MIK384XAM
47
52
57
KHz
Frequency Change with Voltage ∆f/∆V
CC
12V ≤V
CC
≤25 V 0.05 1.0 %
Oscillator Amplitude V
(OSC)
(peak to peak) 1.6 V
Error Amplifier Section
Input Bias Current I
BIAS
V
FB
=3V -0.1 -2 µA
Input Voltage V
I(E.A)
V
pin1
= 2.5V 2.42 2.5 2.58 V
Open Loop Voltage Gain
A
V
OL
2V
≤
V
0
≤
4V
65
90
Po
w
er Suppl
y
Rejection Ratio
PSRR
12V
≤
V
CC
≤
25 V
60
70
dB
Output Sink Current
I
SINK
V
pin2
= 2.7V, V
pin1
= 1.1V
2
7
mA
Output Source Current I
SOURCE
V
pin2
= 2.3V, V
pin1
= 5V -0.5 -1.0 mA
High Output Voltage V
OH
V
pin2
= 2.3V, R
L
= 15KΩto GND 5.0 6.0
Low Output Voltage V
OL
V
pin2
= 2.7V, R
L
= 15KΩto PIN 8 0.8 1.1
Current
Sense
Section
V
Ga
in
G
V
(Note 1 & 2)
2.85
3.0
3.15
V/V
Maximum Input Signal V
I(MAX)
V
pin1
= 5V (Note1) 0.9 1.0 1.1 V
Supply Voltage Rejection SVR 12V ≤V
CC
≤25 V (Note 1) 70 dB
Input Bias Current I
BIAS
V
pin3
= 3V -3.0 -10 µA
Output
Section
Lo
w
Output Voltage
V
OL
High Output Voltage
V
OH
I
SINK
= 20 mA
0.08
0.4
I
SINK
= 200 mA 1.4 2.2
I
SINK
= 20 mA 13 13.5
I
SINK
= 200 mA
12
13.0
V
Rise Time t
R
T
J
= 25°C, C
L
= 1nF (Note 3) 45 150
Fall Time t
F
T
J
= 25°C, C
L
= 1nF (Note 3) 35 150
Under
v
oltage
Lockout
Section
nS
Start Theshold
V
T
H(
S
T
)
MIK3842A(AM)/44A(AM)
14.5
16.0
17.5
MIK3843A(AM)/45A(AM)
7.8
8.4
9.0
V
Min. Operating Voltage
(After Turn On)
PWM Section
V
OPR(min)
MIK3842A(AM)/44A(AM)
8.5
10
11.5
MIK3843A(AM)/45A(AM)
7.0
7.6
8.2
V
Max. Dut
y
C
y
cle
D
(
MA
X)
MIK3842A(AM)/43A(AM)
95
97
100
MIK3844A(AM)/45A(AM)
47
48
50
%
Min. Dut
y
C
y
cle
D
(MAX)
0
Total Standby Current
Start
−
Up Current I
ST
MIK384XA(AM) 0.17 0.3
Operating Suppl
y
Current
I
CC
(OPR)
V
pin3
= V
pin2
= 0V
13
17
mA
Zener Voltage
V
Z
I
CC
=25 mA
30
38
V
* - Adjust V
CC
above the start threshold before setting it to 15V.
Note 1: Parameter measured at trip point of latch with V
pin2
=0.
Note 2: Gain defined as A=∆V
pin1
/∆V
pin3
; 0 ≤V
pin3
≤0.8V.
Note 3: These parameters, although guaranteed, are not 100% tested in production.
2
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ES
T
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ELE
CTR
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.,
L
T
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Pin
functions
N Function Description
1 COMP This pin is the Error Amplifier output and is made for loop compensation.
2 V
FB
This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply
output through a resistor divider.
3 I
SENSE
A voltage proportional to inductor current is connected to this input. The PWM uses this information to
terminate the output switch conduction.
4 R
T
/C
T
The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor R
T
to V
ref
and capacitor C
T
to ground.
5 GROUND This pin is the combined control circuitry and power ground.
6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sink by
this pin.
7 V
CC
This pin is the positive supply of the integrated circuit.
8
V
r
e
f
This is the reference output. It provides charging current for capacitor C
T
through resistor R
T
.
Application information
2
.
5
V
1mA
V
FB
2
C
O
MP
1
F
igure
1.
Error
Amp
Configuration
V
CC
7
O
N
/
O
F
F
C
O
MMA
N
D
T
O
S
/R
O
F
IC
I
CC
M
I
K3
8
42
M
I
K
3843
M
I
K3
8
44
M
I
K
3845
1
3m
A
V
ON
V
OFF
1
6
V
1
0
V
8
.
4
V
7
.
6
V
0
.2m
A
V
OFF
V
ON
V
CC
Du
r
i
n
g
U
V
LO
,
t
h
e
Ou
t
p
u
t
is
lo
w
F
igure
2.
Undervoltage
Lockout
I
S
R
V
FB
COMP
CURRE
NT
SENSE
+
2
_
1
3
ER
R
O
R
A
MP 2R
R
1
V
CURRENT
SENSE
CO
M
P
AR
A
T
O
R
R
S
C
G
N
D
5
Peak current is determined by I
S
m
ax
1.0V
R
S
F
igure
3.
Current
Sense
Circuit
3
BE
IJI
N
G
ES
T
E
K
ELE
CTR
O
N
I
C
S C
O
.,
L
T
D
VREF VREF
8
RTR
T
8
R
SLOPE
R
T
/C
T
4
MIK
3
8
42
R
SLOPE
R
T
/C
T
4
M
I
K
3
8
4
2
ISI
S
R
S
R
1
I
SENSE
3
5
R
S
R
1
I
SENSE
3
5
GND
G
N
D
F
igure
4.
Slope
Compensation
T
echniques
SCR must be selected for a holding current of less than 0.5mA.
The simple t
w
o transistor circuit can be
used in place of the SCR as sho
w
n.
F
igure
5.
Latched
Shutdo
w
n
From V
0
R
I
R
d
V
FB
C
f
R
f
2
.
5 V
+
-
2
1
EA
+
1mA
2R
R
From V
0
R
p
C
p
R
I
C
f
V
FB
R
f
2
.
5 V
+
-
2
EA
+
1mA
2R
R
C
O
M
P
5
COMP
1
5
Error Amp compensation circuit for stabilizing any current-mode topology exceptfo
r
b
o
os
t
a
n
d
fl
y
b
a
c
k
c
o
n
v
e
rt
e
r
s
o
p
e
r
a
ti
n
g
w
ith
c
o
n
t
i
n
u
o
u
s
i
n
d
u
c
t
o
r
c
u
r
r
e
n
t.
Error Amp compensation circuit for stabilizing current-mode boost and flyback
t
o
p
o
lo
g
i
e
s
o
p
e
r
a
ti
n
g
w
ith
c
o
n
t
i
n
u
o
u
s
i
n
d
u
c
t
o
r
cu
r
r
e
n
t.
F
igure
6.
Error
Amplifier
Compensation
4
BE
IJI
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G
ES
T
E
K
ELE
CTR
O
N
I
C
S C
O
.,
L
T
D
F
igure
7.
External
Clock
S
y
nchronization
F
igure
8.
Soft
-
Start
Circuit
5
BE
IJI
N
G
ES
T
E
K
ELE
CTR
O
N
I
C
S C
O
.,
L
T
D
R
T
(
K
)
Ω
T
y
pical Performance Characteristics
%
50
C
5
n
F
50
30
C
1
n
F
C
5
n
F
C
2
n
F
20
20
C
5
00
p
F
C
1
0nF
10
10
C
2
00
p
F
5
C
1
0nF
5
3
C
1
00
p
F
V
=
15
V
2
V
C
C
= 15
2
CC
O
1
T
O
25
C
1
T = 25
10 20 30 50 100 200 300
5
0
0
f
K
H
z
)
1
0
2
0
3
0
5
0
1
00
2
00
3
00
5
0
0
f
K
H
z
)
D
m
a
x
(
%
)
F
i
g
u
r
e
1
.
T
i
m
i
n
g
R
e
s
i
s
t
o
r
v
s
. O
sc
il
l
a
t
o
r
F
r
e
qu
e
n
c
y
.
(
d
B
)
F
i
g
u
r
e
2
.
O
u
t
p
u
t D
ea
d
-
T
i
m
e
vs
.
O
s
c
i
l
l
a
t
o
r
F
r
e
q
u
enc
.
y
90
80
VCC = 15 V
V
O
= 2Vto 4V
80
60
R
=
L
1
0
0K
O
2
5
C
70
40
60
V
=
C
C
15 V
3.3nF
20
50
T = 25
0
40
1 2
3
5
R (
T
-
2
0
10 100 1K 10K 100K 1M
f
(
H
z
)
V
th
(V)
1
.
0
Figure 3. Maximum Output Duty Cycle vs.
Timing Resistor (MIK3842/4 .3)
V
CC
=
15V
I
SC
(mA)
1
0
0
Figure 4.
Error Amp Open-Loop Gain vs.
Fr
.
equency
V
C
C
=
15
V
0
.
8
90
0
.
6
T
O
125 C
T
O
25 C
80
0
.
4
70
0
.
2
60
0 2 4 V (
O
50
0
2
5
5
0
7
5
1
0
0
T
O
)
Figure 5. Current Sense Input Threshold vs.
E
r
r
o
r
A
m
p
O
u
t
p
u
t
V
o
l
t
a
g
e
.
Figure 6.
Reference Short Circuit Current vs.
T
e
mpe
r
a
t
ur
e
.
6
BE
IJI
N
G
ES
T
E
K
ELE
CTR
O
N
I
C
S C
O
.,
L
T
D
V
sat
(V)
-
1
V
15
V
S
o
u
r
s
e
S
a
tu
r
a
t
i
o
n
(
L
o
ad
to
G
r
o
und
)
I
CC
(mA)
-
2
8
0
s
µ
P
u
l
s
e
d
L
oa
d
120
H
z
R
a
t
e
2
0
3
1
5
2
1
0
I
=
Sense
0V
0V
R
10
K
S
i
n
k
S
a
tu
r
a
t
i
o
n
T = 25
C
1
(Load to
5
A
C
3
.
3n
F
0
0
2
0
0
400
6
00
I (
O
m
0
0
10
2
0
3
0
V
(
C
C
F
i
g
u
r
e
.
7
Ou
t
p
u
t
S
at
u
r
a
ti
on
V
o
l
t
a
g
e
v
s
.
L
o
ad
C
u
rr
e
n
t
F
i
g
u
r
e
.
8
S
u
p
p
l
y
C
u
r
r
e
n
t
v
s
.
Su
p
p
l
y
V
o
l
t
a
g
.
e
T
2
5
.
V
r
e
f
R
T
8
P
W
M
V
CC
7
5
V
R
E
G
6
R /C
T T
OUTPUT
O
U
T
PU
T
LARGE R / SMALL C
T
C
L
OCK
R C
T
T
/
4
I
D
O
S
C
I
L
L
A
T
O
R
5
R /C
T T
OUTPUT
SMALL R
T
/ LARGE
G
N
D
Figure 9.
O
scillator and
O
utput Waveforms
Or
d
e
ri
n
g I
n
f
o
rm
a
ti
o
n
O
R
D
E
RI
N
G
N
U
M
B
ER
P
A
C
K
A
G
E
M
AR
K
I
N
G
384
2
/
43
/
44
/
4
5
SOP-8 / DIP-8 KA3842/ 43/ 44/45
A
d
dr
e
ss
:
6A06--6A07
Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
Postalcode:100039
Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Fax : 010-58895793
Http://www.estek.com.cn
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m
a
il
:s
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l
e
s@
e
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k.c
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m.
c
n
R
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o
:
01
-
0
6
08
15
7
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K
ELE
CTR
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S C
O
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L
T
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