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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TL494

SLVS074H –JANUARY 1983–REVISED MARCH 2017

TL494 Pulse-Width-Modulation Control Circuits

1 Features

1• Complete PWM Power-Control Circuitry

• Uncommitted Outputs for 200-mA Sink or

Source Current

• Output Control Selects Single-Ended or

Push-Pull Operation

• Internal Circuitry Prohibits Double Pulse at

Either Output

• Variable Dead Time Provides Control Over

Total Range

• Internal Regulator Provides a Stable 5-V

Reference Supply With 5% Tolerance

• Circuit Architecture Allows Easy Synchronization

2 Applications

• Desktop PCs

• Microwave Ovens

• Power Supplies: AC/DC, Isolated,

With PFC, > 90 W

• Server PSUs

• Solar Micro-Inverters

• Washing Machines: Low-End and High-End

• E-Bikes

• Power Supplies: AC/DC, Isolated,

No PFC, < 90 W

• Power: Telecom/Server AC/DC Supplies:

Dual Controller: Analog

• Smoke Detectors

• Solar Power Inverters

3 Description

The TL494 device incorporates all the functions

required in the construction of a pulse-width-

modulation (PWM) control circuit on a single chip.

Designed primarily for power-supply control, this

device offers the flexibility to tailor the power-supply

control circuitry to a specific application.

The TL494 device contains two error amplifiers, an

on-chip adjustable oscillator, a dead-time control

(DTC) comparator, a pulse-steering control flip-flop, a

5-V, 5%-precision regulator, and output-control

circuits.

The error amplifiers exhibit a common-mode voltage

range from –0.3 V to VCC – 2 V. The dead-time

control comparator has a fixed offset that provides

approximately 5% dead time. The on-chip oscillator

can be bypassed by terminating RT to the reference

output and providing a sawtooth input to CT, or it can

drive the common circuits in synchronous multiple-rail

power supplies.

The uncommitted output transistors provide either

common-emitter or emitter-follower output capability.

The TL494 device provides for push-pull or single-

ended output operation, which can be selected

through the output-control function. The architecture

of this device prohibits the possibility of either output

being pulsed twice during push-pull operation.

The TL494C device is characterized for operation

from 0°C to 70°C. The TL494I device is characterized

for operation from –40°C to 85°C.

Device Information(1)

PART NUMBER PACKAGE (PIN) BODY SIZE

TL494

SOIC (16) 9.90 mm × 3.91 mm

PDIP (16) 19.30 mm × 6.35 mm

SOP (16) 10.30 mm × 5.30 mm

TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

4 Simplified Block Diagram

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Simplified Block Diagram ..................................... 1

5 Revision History..................................................... 2

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 4

7.5 Electrical Characteristics, Reference Section........... 5

7.6 Electrical Characteristics, Oscillator Section............. 5

7.7 Electrical Characteristics, Error-Amplifier Section .... 5

7.8 Electrical Characteristics, Output Section................. 6

7.9 Electrical Characteristics, Dead-Time Control

Section....................................................................... 6

7.10 Electrical Characteristics, PWM Comparator

Section....................................................................... 6

7.11 Electrical Characteristics, Total Device................... 6

7.12 Switching Characteristics........................................ 6

7.13 Typical Characteristics............................................ 7

8 Parameter Measurement Information .................. 8

9 Detailed Description............................................ 10

9.1 Overview................................................................. 10

9.2 Functional Block Diagram....................................... 10

9.3 Feature Description................................................. 10

9.4 Device Functional Modes........................................ 12

10 Application and Implementation........................ 13

10.1 Application Information.......................................... 13

10.2 Typical Application ............................................... 13

11 Power Supply Recommendations ..................... 20

12 Layout................................................................... 20

12.1 Layout Guidelines ................................................. 20

12.2 Layout Example .................................................... 21

13 Device and Documentation Support................. 21

13.1 Trademarks........................................................... 21

13.2 Electrostatic Discharge Caution............................ 21

13.3 Glossary................................................................ 21

14 Mechanical, Packaging, and Orderable

Information........................................................... 21

5 Revision History

Changes from Revision G (January 2015) to Revision H Page

• Updated package illustration.................................................................................................................................................. 1

• Corrected resistor polarity references in the Current-Limiting Amplifier section.................................................................. 15

• Updated Figure 12. .............................................................................................................................................................. 15

Changes from Revision F (January 2014) to Revision G Page

• Added Applications,Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, ,

Feature Description section, Device Functional Modes,Application and Implementation section, Power Supply

Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,

Packaging, and Orderable Information section. ..................................................................................................................... 1

Changes from Revision E (February 2005) to Revision F Page

• Updated document to new TI data sheet format - no specification changes......................................................................... 1

• Removed Ordering Information table. .................................................................................................................................... 1

• Added ESD warning............................................................................................................................................................. 21

1IN+

1IN−

FEEDBACK

DTC

GND

2IN+

2IN−

REF

OUTPUT CTRL

VCC

D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

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6 Pin Configuration and Functions

Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

1IN+ 1 I Noninverting input to error amplifier 1

1IN- 2 I Inverting input to error amplifier 1

2IN+ 16 I Noninverting input to error amplifier 2

2IN- 15 I Inverting input to error amplifier 2

C1 8 O Collector terminal of BJT output 1

C2 11 O Collector terminal of BJT output 2

CT 5 — Capacitor terminal used to set oscillator frequency

DTC 4 I Dead-time control comparator input

E1 9 O Emitter terminal of BJT output 1

E2 10 O Emitter terminal of BJT output 2

FEEDBACK 3 I Input pin for feedback

GND 7 — Ground

OUTPUT

CTRL 13 I Selects single-ended/parallel output or push-pull operation

REF 14 O 5-V reference regulator output

RT 6 — Resistor terminal used to set oscillator frequency

VCC 12 — Positive Supply

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the network ground terminal.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VCC Supply voltage(2) 41 V

VIAmplifier input voltage VCC + 0.3 V

VOCollector output voltage 41 V

IOCollector output current 250 mA

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

Tstg Storage temperature range –65 150 °C

7.2 ESD Ratings MAX UNIT

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 500 V

Charged device model (CDM), per JEDEC specification JESD22-

C101, all pins 200

7.3 Recommended Operating Conditions MIN MAX UNIT

VCC Supply voltage 7 40 V

VIAmplifier input voltage –0.3 VCC – 2 V

VOCollector output voltage 40 V

Collector output current (each transistor) 200 mA

Current into feedback terminal 0.3 mA

fOSC Oscillator frequency 1 300 kHz

CTTiming capacitor 0.47 10000 nF

RTTiming resistor 1.8 500 kΩ

TAOperating free-air temperature TL494C 0 70 °C

TL494I –40 85

(1) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient

temperature is PD= (TJ(max) – TA) / θJA. Operating at the absolute maximum TJof 150°C can affect reliability.

(2) The package thermal impedance is calculated in accordance with JESD 51-7.

7.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

PARAMETER TL494 UNIT

D DB N NS PW

RθJA Package thermal

impedance(1)(2) 73 82 67 64 108 °C/W

( )

n 1

x X

N 1

s = -

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(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

(2) All typical values, except for parameter changes with temperature, are at TA= 25°C.

(3) Duration of short circuit should not exceed one second.

7.5 Electrical Characteristics, Reference Section

over recommended operating free-air temperature range, VCC = 15 V, f = 10 kHz (unless otherwise noted)

PARAMETER TEST CONDITIONS(1) TL494C, TL494I UNIT

MIN TYP(2) MAX

Output voltage (REF) IO= 1 mA 4.75 5 5.25 V

Input regulation VCC = 7 V to 40 V 2 25 mV

Output regulation IO= 1 mA to 10 mA 1 15 mV

Output voltage change with temperature ΔTA= MIN to MAX 2 10 mV/V

Short-circuit output current(3) REF = 0 V 25 mA

(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

(2) All typical values, except for parameter changes with temperature, are at TA= 25°C.

(3) Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:

(4) Temperature coefficient of timing capacitor and timing resistor are not taken into account.

7.6 Electrical Characteristics, Oscillator Section

CT= 0.01 μF, RT= 12 kΩ(see Figure 5)

PARAMETER TEST CONDITIONS(1) TL494C, TL494I UNIT

MIN TYP(2) MAX

Frequency 10 kHz

Standard deviation of frequency(3) All values of VCC, CT, RT, and TAconstant 100 Hz/kHz

Frequency change with voltage VCC = 7 V to 40 V, TA= 25°C 1 Hz/kHz

Frequency change with temperature(4) ΔTA= MIN to MAX 10 Hz/kHz

(1) All typical values, except for parameter changes with temperature, are at TA= 25°C.

7.7 Electrical Characteristics, Error-Amplifier Section

See Figure 6

PARAMETER TEST CONDITIONS TL494C, TL494I UNIT

MIN TYP(1) MAX

Input offset voltage VO(FEEDBACK) = 2.5 V 2 10 mV

Input offset current VO(FEEDBACK) = 2.5 V 25 250 nA

Input bias current VO(FEEDBACK) = 2.5 V 0.2 1 μA

Common-mode input voltage range VCC = 7 V to 40 V –0.3 to VCC – 2 V

Open-loop voltage amplification ΔVO= 3 V, VO= 0.5 V to 3.5 V, RL= 2 kΩ70 95 dB

Unity-gain bandwidth VO= 0.5 V to 3.5 V, RL= 2 kΩ800 kHz

Common-mode rejection ratio ΔVO= 40 V, TA= 25°C 65 80 dB

Output sink current (FEEDBACK) VID = –15 mV to –5 V, V (FEEDBACK) = 0.7 V 0.3 0.7 mA

Output source current (FEEDBACK) VID = 15 mV to 5 V, V (FEEDBACK) = 3.5 V –2 mA

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(1) All typical values, except for temperature coefficient, are at TA= 25°C.

7.8 Electrical Characteristics, Output Section

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Collector off-state current VCE = 40 V, VCC = 40 V 2 100 μA

Emitter off-state current VCC = VC= 40 V, VE= 0 –100 μA

Collector-emitter saturation voltage Common emitter VE= 0, IC= 200 mA 1.1 1.3 V

Emitter follower VO(C1 or C2) = 15 V, IE= –200 mA 1.5 2.5

Output control input current VI= Vref 3.5 mA

(1) All typical values, except for temperature coefficient, are at TA= 25°C.

7.9 Electrical Characteristics, Dead-Time Control Section

See Figure 5 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Input bias current (DEAD-TIME CTRL) VI= 0 to 5.25 V –2 –10 μA

Maximum duty cycle, each output VI(DEAD-TIME CTRL) = 0, CT= 0.01 μF,

RT= 12 kΩ45% —

Input threshold voltage (DEAD-TIME CTRL) Zero duty cycle 3 3.3 V

Maximum duty cycle 0

(1) All typical values, except for temperature coefficient, are at TA= 25°C.

7.10 Electrical Characteristics, PWM Comparator Section

See Figure 5 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Input threshold voltage (FEEDBACK) Zero duty cyle 4 4.5 V

Input sink current (FEEDBACK) V (FEEDBACK) = 0.7 V 0.3 0.7 mA

(1) All typical values, except for temperature coefficient, are at TA= 25°C.

7.11 Electrical Characteristics, Total Device

PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Standby supply current RT= Vref,

All other inputs and outputs open VCC = 15 V 6 10 mA

VCC = 40 V 9 15

Average supply current VI(DEAD-TIME CTRL) = 2 V, See Figure 5 7.5 mA

(1) All typical values, except for temperature coefficient, are at TA= 25°C.

7.12 Switching Characteristics

TA= 25°C PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT

Rise time Common-emitter configuration, See Figure 7 100 200 ns

Fall time 25 100 ns

Rise time Emitter-follower configuration, See Figure 8 100 200 ns

Fall time 40 100 ns

00 10 20

VI− Input Voltage − (mV)

VO− Output V

oltage − (V)

00 10k 1M

f − Frequency − (Hz)

100k

Gain − (dB)

Df = 1%

(1)

100

1 k 4 k 10 k 40 k 100 k 400 k 1 M

f − Oscillator Frequency and Frequency V

ariation − Hz

400

1 k

4 k

10 k

40 k

100 k

RT− T

iming Resistance − Ω

0.1 Fµ

−2%

−1%

0% 0.01 Fµ

0.001 Fµ

VCC = 15 V

TA= 25 C°

CT= 1 Fµ

100

1 10 100 1 M

A − Amplifier Voltage Amplification − dB

f − Frequency − Hz

1 k

VCC = 15 V

ΔVO= 3 V

TA= 25 C°

10 k

100 k

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7.13 Typical Characteristics

Frequency variation (Δf) is the change in oscillator frequency

that occurs over the full temperature range.

Figure 1. Oscillator Frequency and Frequency Variation

Timing Resistance

xxx

xxx Figure 2. Amplifier Voltage Amplification

Frequency

Figure 3. Error Amplifier Transfer Characteristics Figure 4. Error Amplifier Bode Plot

Test

Inputs

DTC

FEEDBACK

GND

50 kW

12 kW

0.01 mF

VCC

REF

OUTPUT

CTRL

C1 Output 1

Output 2

150 W

2 W

150 W

2 W

VCC = 15 V

TEST CIRCUIT

1IN+

VCC

0 V

Voltage

at C1

Voltage

at C2

Voltage

at CT

DTC

FEEDBACK

0 V

0.7 V

0% MAX 0%

Threshold Voltage

VOLTAGE WAVEFORMS

Duty Cycle

Error

Amplifiers

1IN−

2IN−

2IN+

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8 Parameter Measurement Information

Figure 5. Operational Test Circuit and Waveforms

Output

Each Output

Circuit

68 W

2 W

15 V

CL= 15 pF

(See Note A)

90%

10%

90%

10%

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

NOTE A: CLincludes probe and jig capacitance.

Output

Each Output

Circuit

68 W

2 W

15 V

CL= 15 pF

(See Note A)

90%

10%

90%

10%

tftr

TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM

NOTE A: CLincludes probe and jig capacitance.

−

Vref

FEEDBACK

Amplifier Under Test

Other Amplifier

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Parameter Measurement Information (continued)

Figure 6. Amplifier Characteristics

Figure 7. Common-Emitter Configuration

Figure 8. Emitter-Follower Configuration

GND

VCC

Reference

Regulator

Pulse-Steering

Flip-Flop

DTC

PWM

Comparator

−

Error Amplifier 1

≈0.1 V

Dead-Time Control

Comparator

Oscillator

OUTPUT CTRL

(see Function Table)

0.7 mA

−

Error Amplifier 2

1IN+

1IN−

2IN+

2IN−

FEEDBACK

REF

≈0.7 V

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9 Detailed Description

9.1 Overview

The design of the TL494 not only incorporates the primary building blocks required to control a switching power

supply, but also addresses many basic problems and reduces the amount of additional circuitry required in the

total design. The TL494 is a fixed-frequency pulse-width-modulation (PWM) control circuit. Modulation of output

pulses is accomplished by comparing the sawtooth waveform created by the internal oscillator on the timing

capacitor (CT) to either of two control signals. The output stage is enabled during the time when the sawtooth

voltage is greater than the voltage control signals. As the control signal increases, the time during which the

sawtooth input is greater decreases; therefore, the output pulse duration decreases. A pulse-steering flip-flop

alternately directs the modulated pulse to each of the two output transistors. For more information on the

operation of the TL494, see the application notes located on ti.com.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 5-V Reference Regulator

The TL494 internal 5-V reference regulator output is the REF pin. In addition to providing a stable reference, it

acts as a preregulator and establishes a stable supply from which the output-control logic, pulse-steering flip-flop,

oscillator, dead-time control comparator, and PWM comparator are powered. The regulator employs a band-gap

circuit as its primary reference to maintain thermal stability of less than 100-mV variation over the operating free-

air temperature range of 0°C to 70°C. Short-circuit protection is provided to protect the internal reference and

preregulator; 10 mA of load current is available for additional bias circuits. The reference is internally

programmed to an initial accuracy of ±5% and maintains a stability of less than 25-mV variation over an input

voltage range of 7 V to 40 V. For input voltages less than 7 V, the regulator saturates within 1 V of the input and

tracks it.

T T

2R C

T T

R C

OSC

T T

R C

CHARGE

3 V C

CHARGE

3 V

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Feature Description (continued)

9.3.2 Oscillator

The oscillator provides a positive sawtooth waveform to the dead-time and PWM comparators for comparison to

the various control signals.

The frequency of the oscillator is programmed by selecting timing components RTand CT. The oscillator charges

the external timing capacitor, CT, with a constant current, the value of which is determined by the external timing

resistor, RT. This produces a linear-ramp voltage waveform. When the voltage across CTreaches 3 V, the

oscillator circuit discharges it, and the charging cycle is reinitiated. The charging current is determined by the

formula:

(1)

The period of the sawtooth waveform is:

(2)

The frequency of the oscillator becomes:

(3)

However, the oscillator frequency is equal to the output frequency only for single-ended applications. For push-

pull applications, the output frequency is one-half the oscillator frequency.

Single-ended applications:

(4)

Push-pull applications:

(5)

9.3.3 Dead-time Control

The dead-time control input provides control of the minimum dead time (off time). The output of the comparator

inhibits switching transistors Q1 and Q2 when the voltage at the input is greater than the ramp voltage of the

oscillator. An internal offset of 110 mV ensures a minimum dead time of ∼3% with the dead-time control input

grounded. Applying a voltage to the dead-time control input can impose additional dead time. This provides a

linear control of the dead time from its minimum of 3% to 100% as the input voltage is varied from 0 V to 3.3 V,

respectively. With full-range control, the output can be controlled from external sources without disrupting the

error amplifiers. The dead-time control input is a relatively high-impedance input (II< 10 μA) and should be used

where additional control of the output duty cycle is required. However, for proper control, the input must be

terminated. An open circuit is an undefined condition.

9.3.4 Comparator

The comparator is biased from the 5-V reference regulator. This provides isolation from the input supply for

improved stability. The input of the comparator does not exhibit hysteresis, so protection against false triggering

near the threshold must be provided. The comparator has a response time of 400 ns from either of the control-

signal inputs to the output transistors, with only 100 mV of overdrive. This ensures positive control of the output

within one-half cycle for operation within the recommended 300-kHz range.

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Feature Description (continued)

9.3.5 Pulse-Width Modulation (PWM)

The comparator also provides modulation control of the output pulse width. For this, the ramp voltage across

timing capacitor CTis compared to the control signal present at the output of the error amplifiers. The timing

capacitor input incorporates a series diode that is omitted from the control signal input. This requires the control

signal (error amplifier output) to be ∼0.7 V greater than the voltage across CTto inhibit the output logic, and

ensures maximum duty cycle operation without requiring the control voltage to sink to a true ground potential.

The output pulse width varies from 97% of the period to 0 as the voltage present at the error amplifier output

varies from 0.5 V to 3.5 V, respectively.

9.3.6 Error Amplifiers

Both high-gain error amplifiers receive their bias from the VIsupply rail. This permits a common-mode input

voltage range from –0.3 V to 2 V less than VI. Both amplifiers behave characteristically of a single-ended single-

supply amplifier, in that each output is active high only. This allows each amplifier to pull up independently for a

decreasing output pulse-width demand. With both outputs ORed together at the inverting input node of the PWM

comparator, the amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased low by

a current sink to provide maximum pulse width out when both amplifiers are biased off.

9.3.7 Output-Control Input

The output-control input determines whether the output transistors operate in parallel or push-pull. This input is

the supply source for the pulse-steering flip-flop. The output-control input is asynchronous and has direct control

over the output, independent of the oscillator or pulse-steering flip-flop. The input condition is intended to be a

fixed condition that is defined by the application. For parallel operation, the output-control input must be

grounded. This disables the pulse-steering flip-flop and inhibits its outputs. In this mode, the pulses seen at the

output of the dead-time control/PWM comparator are transmitted by both output transistors in parallel. For push-

pull operation, the output-control input must be connected to the internal 5-V reference regulator. Under this

condition, each of the output transistors is enabled, alternately, by the pulse-steering flip-flop.

9.3.8 Output Transistors

Two output transistors are available on the TL494. Both transistors are configured as open collector/open

emitter, and each is capable of sinking or sourcing up to 200 mA. The transistors have a saturation voltage of

less than 1.3 V in the common-emitter configuration and less than 2.5 V in the emitter-follower configuration. The

outputs are protected against excessive power dissipation to prevent damage, but do not employ sufficient

current limiting to allow them to be operated as current-source outputs.

9.4 Device Functional Modes

When the OUTPUT CTRL pin is tied to ground, the TL494 is operating in single-ended or parallel mode. When

the OUTPUT CTRL pin is tied to VREF, the TL494 is operating in normal push-pull operation.

VREF

1 kW

Load

Control

Osc

NTE331 140 mH

NTE6013

NTE153

TL494

4 kW

5-V

REF

R11

100 W

R12

30 W

R10

270 W

1 2 3 4 6 7 8

910111213141516

51 kW

50 kW

510 W

9.1 kW

5.1 kW

1 kW

2.5 mF

5-V

REF

5-V

REF

R13

0.1 W

0.001 Fm

5.1 k

+ −

32-V

Input

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The following design example uses the TL494 to create a 5-V/10-A power supply. This application was taken

from application note SLVA001.

10.2 Typical Application

Figure 9. Switching and Control Sections

RT+1

fOSC CT

(20 103) (0.001 10*6)+50 kW

OSC

T T

R C

RECTIFIER(AVG) O

V5 V

I I 10 A 1.6 A

V 32 V

» ´ » ´ =

RECTIFIER SECONDARY

V V 2 24 V 2 34 V= ´ = ´ =

20,000 μF

Bridge

Rectifiers

3 A/50 V

20,000 μF

0.3 W

120 V 24 V

3 A +32 V

+ +

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Typical Application (continued)

10.2.1 Design Requirements

• VI= 32 V

• VO=5V

• IO= 10 A

• fOSC = 20-kHz switching frequency

• VR= 20-mV peak-to-peak (VRIPPLE)

•ΔIL= 1.5-A inductor current change

10.2.2 Detailed Design Procedure

10.2.2.1 Input Power Source

The 32-V dc power source for this supply uses a 120-V input, 24-V output transformer rated at 75 VA. The 24-V

secondary winding feeds a full-wave bridge rectifier, followed by a current-limiting resistor (0.3 Ω) and two filter

capacitors (see Figure 10).

Figure 10. Input Power Source

The output current and voltage are determined by Equation 6 and Equation 7:

(6)

(7)

The 3-A/50-V full-wave bridge rectifier meets these calculated conditions. Figure 9 shows the switching and

control sections.

10.2.2.2 Control Circuits

10.2.2.2.1 Oscillator

Connecting an external capacitor and resistor to pins 5 and 6 controls the TL494 oscillator frequency. The

oscillator is set to operate at 20 kHz, using the component values calculated by Equation 8 and Equation 9:

(8)

Choose CT= 0.001 μF and calculate RT:

(9)

10.2.2.2.2 Error Amplifier

The error amplifier compares a sample of the 5-V output to the reference and adjusts the PWM to maintain a

constant output current (see Figure 11).

R13 0.1

10 A

= = W

1 NŸ

4 NŸ

Load

TL494

VREF

TL494

R13

0.1 Ÿ

SC O

I I 10.75 A

= + =

5.1 kW

VREF +

−

13 Error

Amplifier

TL494

5.1 kW

510 W

51 kW

5.1 kW

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Typical Application (continued)

Figure 11. Error-Amplifier Section

The TL494 internal 5-V reference is divided to 2.5 V by R3 and R4. The output-voltage error signal also is

divided to 2.5 V by R8 and R9. If the output must be regulated to exactly 5.0 V, a 10-kΩpotentiometer can be

used in place of R8 to provide an adjustment.

To increase the stability of the error-amplifier circuit, the output of the error amplifier is fed back to the inverting

input through RT, reducing the gain to 101.

10.2.2.2.3 Current-Limiting Amplifier

The power supply was designed for a 10-A load current and an ILswing of 1.5 A, therefore, the short-circuit

current should be:

(10)

The current-limiting circuit is shown in Figure 12.

Figure 12. Current-Limiting Circuit

Resistors R1 and R2 set the reference of approximately 1 V on the inverting input of the current-limiting amplifier.

Resistor R13, in series with the load, applies 1 V to the non-inverting terminal of the current-limiting amplifier

when the load current reaches 10 A. The output pulse width reduces accordingly. The value of R13 is calculated

in Equation 11.

(11)

10.2.2.2.4 Soft Start and Dead Time

To reduce stress on the switching transistors at the start-up time, the start-up surge that occurs as the output

filter capacitor charges must be reduced. The availability of the dead-time control makes implementation of a

soft-start circuit relatively simple (see Figure 13).

soft start time 50 s 50cycles

C2 2.5 F

R6 1 k

- m ´

= = = m

1 1

t 50 sper clock cycle

f 20kHz

= = = m

TL494

Pin 4 Voltage

PWM Output

Oscillator Ramp Voltage

ton

+5 V

0.1 V

Osc

Oscillator Ramp

TL494

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Typical Application (continued)

Figure 13. Soft-Start Circuit

The soft-start circuit allows the pulse width at the output to increase slowly (see Figure 13) by applying a

negative slope waveform to the dead-time control input (pin 4).

Initially, capacitor C2 forces the dead-time control input to follow the 5-V regulator, which disables the outputs

(100% dead time). As the capacitor charges through R6, the output pulse width slowly increases until the control

loop takes command. With a resistor ratio of 1:10 for R6 and R7, the voltage at pin 4 after start-up is 0.1 × 5 V,

or 0.5 V.

The soft-start time generally is in the range of 25 to 100 clock cycles. If 50 clock cycles at a 20-kHz switching

rate is selected, the soft-start time is:

(12)

The value of the capacitor then is determined by:

(13)

This helps eliminate any false signals that might be created by the control circuit as power is applied.

I1.5 A

C3 94 F

8f V 8 20 10 0.1 V

= = = m

D´ ´ ´

O(ripple)

ESR(max) 0.067

I 1.5 A

= = » W

TL494

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Product Folder Links: TL494

Typical Application (continued)

10.2.2.3 Inductor Calculations

The switching circuit used is shown in Figure 39.

Figure 14. Switching Circuit

The size of the inductor (L) required is:

d = duty cycle = VO/VI= 5 V/32 V = 0.156

f = 20 kHz (design objective)

ton = time on (S1 closed) = (1/f) × d = 7.8 μs

toff = time off (S1 open) = (1/f) – ton = 42.2 μs

L≉(VI– VO) × ton/ΔIL

≉[(32 V – 5 V) × 7.8 μs]/1.5 A

≉140.4 μH

10.2.2.4 Output Capacitance Calculations

Once the filter inductor has been calculated, the value of the output filter capacitor is calculated to meet the

output ripple requirements. An electrolytic capacitor can be modeled as a series connection of an inductance, a

resistance, and a capacitance. To provide good filtering, the ripple frequency must be far below the frequencies

at which the series inductance becomes important. So, the two components of interest are the capacitance and

the effective series resistance (ESR). The maximum ESR is calculated according to the relation between the

specified peak-to-peak ripple voltage and the peak-to-peak ripple current.

(14)

The minimum capacitance of C3 necessary to maintain the VOripple voltage at less than the 100-mV design

objective is calculated according to Equation 15:

(15)

A 220-mF, 60-V capacitor is selected because it has a maximum ESR of 0.074 Ωand a maximum ripple current

of 2.8 A.

10.2.2.5 Transistor Power-Switch Calculations

The transistor power switch was constructed with an NTE153 pnp drive transistor and an NTE331 npn output

transistor. These two power devices were connected in a pnp hybrid Darlington circuit configuration (see

Figure 15).

[ ]

I BE CE

V V (Q1) V (TL494) 32 (1.5 0.7)

R10 i 0.144

R10 207

- + - +

£ =

£ W

FE FE

i 144mA

h (Q2) h (Q1)

³ ³

FE C

h (Q2) at I of 10.0 A 5=

FE C

h (Q1) at I of 3 A 15=

NTE331

TL494

Control

11 10 9

NTE153

32 V

R10

270 W

R12

30 W

R11

100 W

I 10.8 A

+ =

TL494

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Product Folder Links: TL494

Figure 15. Power-Switch Section

The hybrid Darlington circuit must be saturated at a maximum output current of IO+ΔIL/2 or 10.8 A. The

Darlington hFE at 10.8 A must be high enough not to exceed the 250-mA maximum output collector current of the

TL494. Based on published NTE153 and NTE331 specifications, the required power-switch minimum drive was

calculated by Equation 16 through Equation 18 to be 144 mA:

(16)

(17)

(18)

The value of R10 was calculated by:

(19)

Based on these calculations, the nearest standard resistor value of 220 Ωwas selected for R10. Resistors R11

and R12 permit the discharge of carriers in switching transistors when they are turned off.

The power supply described demonstrates the flexibility of the TL494 PWM control circuit. This power-supply

design demonstrates many of the power-supply control methods provided by the TL494, as well as the versatility

of the control circuit.

00 1 2 3 4 5 6 7

VI− Input Voltage − (V)

VREF − Reference V

oltage − (V)

TL494

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10.2.3 Application Curves for Output Characteristics

Figure 16. Reference Voltage vs Input Voltage

TL494

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Product Folder Links: TL494

11 Power Supply Recommendations

The TL494 is designed to operate from an input voltage supply range between 7 V and 40 V. This input supply

should be well regulated. If the input supply is located more than a few inches from the device, additional bulk

capacitance may be required in addition to the ceramic bypass capacitors. A tantalum capacitor with a value of

47 μF is a typical choice, however this may vary depending upon the output power being delivered.

12 Layout

12.1 Layout Guidelines

Always try to use a low EMI inductor with a ferrite type closed core. Some examples would be toroid and

encased E core inductors. Open core can be used if they have low EMI characteristics and are located a bit

more away from the low power traces and components. Make the poles perpendicular to the PCB as well if using

an open core. Stick cores usually emit the most unwanted noise.

12.1.1 Feedback Traces

Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like

the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but

keeping it away from inductor EMI and other noise sources is the more critical of the two. Run the feedback trace

on the side of the PCB opposite of the inductor with a ground plane separating the two.

12.1.2 Input/Output Capacitors

When using a low value ceramic input filter capacitor, it should be located as close to the VCC pin of the IC as

possible. This will eliminate as much trace inductance effects as possible and give the internal IC rail a cleaner

voltage supply. Some designs require the use of a feed-forward capacitor connected from the output to the

feedback pin as well, usually for stability reasons. In this case it should also be positioned as close to the IC as

possible. Using surface mount capacitors also reduces lead length and lessens the chance of noise coupling into

the effective antenna created by through-hole components.

12.1.3 Compensation Components

External compensation components for stability should also be placed close to the IC. Surface mount

components are recommended here as well for the same reasons discussed for the filter capacitors. These

should not be located very close to the inductor either.

12.1.4 Traces and Ground Planes

Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a

standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. The inductor,

output capacitors, and output diode should be as close to each other possible. This helps reduce the EMI

radiated by the power traces due to the high switching currents through them. This will also reduce lead

inductance and resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce

voltage errors. The grounds of the IC, input capacitors, output capacitors, and output diode (if applicable) should

be connected close together directly to a ground plane. It would also be a good idea to have a ground plane on

both sides of the PCB. This will reduce noise as well by reducing ground loop errors as well as by absorbing

more of the EMI radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can

be used to separate the power plane (where the power traces and components are) and the signal plane (where

the feedback and compensation and components are) for improved performance. On multi-layer boards the use

of vias will be required to connect traces and different planes. It is good practice to use one standard via per 200

mA of current if the trace will need to conduct a significant amount of current from one plane to the other.

Arrange the components so that the switching current loops curl in the same direction. Due to the way switching

regulators operate, there are two power states. One state when the switch is on and one when the switch is off.

During each state there will be a current loop made by the power components that are currently conducting.

Place the power components so that during each of the two states the current loop is conducting in the same

direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces

radiated EMI.

GND

TL494

2 1IN±

4 DTC

7 GND

8 9E1

10E2

11C2

12VCC

14REF

152IN±

162IN+

FEEDBACK

1IN+

OUTPUT

CTRL

VIA to Power Plane

Power or GND Plane

VIA to GND Plane

LEGEND

Output

VCC

TL494

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Product Folder Links: TL494

12.2 Layout Example

Figure 17. Operational Amplifier Board Layout for Noninverting Configuration

13 Device and Documentation Support

13.1 Trademarks

All trademarks are the property of their respective owners.

13.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13.3 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser based versions of this data sheet, refer to the left hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TL494CD ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C

TL494CDG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C

TL494CDR ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 TL494C

TL494CDRE4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C

TL494CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C

TL494CN ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL494CN

TL494CNE4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type 0 to 70 TL494CN

TL494CNSR ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494

TL494CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494

TL494CPW ACTIVE TSSOP PW 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494

TL494CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494

TL494CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494

TL494ID ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I

TL494IDG4 ACTIVE SOIC D 16 40 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I

TL494IDR ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 TL494I

TL494IDRE4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I

TL494IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I

PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TL494IN ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL494IN

TL494INE4 ACTIVE PDIP N 16 25 Green (RoHS

& no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TL494IN

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TL494CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

TL494CDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

TL494CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TL494IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

TL494IDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Mar-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL494CDR SOIC D 16 2500 333.2 345.9 28.6

TL494CDR SOIC D 16 2500 367.0 367.0 38.0

TL494CDRG4 SOIC D 16 2500 333.2 345.9 28.6

TL494CPWR TSSOP PW 16 2000 367.0 367.0 35.0

TL494IDR SOIC D 16 2500 333.2 345.9 28.6

TL494IDRG4 SOIC D 16 2500 333.2 345.9 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Mar-2017

Pack Materials-Page 2

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