A H i gh -D en sity M A C a nd CI D R Ta ble P ro cess or iFlowTM Address Processor Product Brief iFlow Address Processor www.siliconaccess.com DESCRIPTION As network data rates have increased to 10 gigabits per second and higher, performance demands on the address lookup function have soared to more than 50 million lookups per second. Software-based solutions cannot keep up, forcing designers to employ expensive and power-hungry, ternary-CAMs (TCAMs). The iFlow Address Processor (iAP) provides a complete subsystem-on-a-chip solution for address lookups that solves many of the problems associated with standard TCAMs and TCAM-based coprocessor products. The iAP is a high-density address and flow search engine for exact or longest-prefix matches on packetized data. With a peak rate of 65 million lookups per second, the iAP can perform more than two lookups per minimum length packet at OC-192 speeds. An onchip table size of 256K IPv4 entries, combined with integrated memory, delivers an unmatched level of integration. FEATURES * Single-chip Layer 2/3/4 lookup coprocessor that integrates the equivalent of a 9-Mbit TCAM, two levels of associated memory, statistics engine and interface FPGA/ASIC * 65 million lookups per second with deterministic result latency and no key-size penalties * Supports 16 independent tables with configurable key sizes * Expandable to as many as eight iAPs providing up to two million IPv4 table entries * Supports MAC, N-tuple flows, IPv4 and IPv6 (with VPN tag) lookups without requiring bank segmentation * Two levels of integrated associated data enables one lookup to provide the search result plus up to 48 bits of per-entry associated data and 256 bits of per-hop associated data * 64 concurrent lookup contexts support multi-threaded NPUs such as the iFlow Packet Processor (iPP) * On-the-fly modification of associated data fields using on-chip ALU (performed in parallel with lookup) * Table management in hardware (transparent to user) * Up to one million inserts or deletes per second with no impact on lookup rates * Innovative power management requires less than 5W (versus up to 20W required for non-integrated solutions) * ECC protection on all memories for unmatched reliability * 32-, 64-, or 96-bit, 83-133MHz Zero Bus Turnaround (ZBT) or Double Cycle Deselect (DCD) synchronous SRAM interface * Standard 0.13 micron, 1.2V CMOS process * 520-ball BGA package BLOCK DIAGRAM Pipelined Lookup Service Rate Manager Lookup Table Associated Memory Per-Hop Associated Memory ALU Request Assembler Memory Result Buffer Memory ZBT or DCD 32-, 64-, 96-bit @ 83-133 MHz Figure 1: iFlow Address Processor Block Diagram A H i gh -D en sity M A C a nd CI D R Ta ble P ro cess or APPLICATIONS The iAP supports a wide range of applications and configurations to address the requirements of nextgeneration Internet switches and routers. Figure 2 shows a generic line-card application where a merchant network processor or in-house ASIC utilizes iAP lookup services over an SRAM interface. The iAP, as a lookaside coprocessor to the main data path processing unit, receives lookup fields extracted by the network processor and returns the result of the lookup and the associated data. Main Table Assoc Data NPU or ASIC Figure 2: Generic Line Card Configuration iFlow 20Gbps Packet Processor iAP iAP AssociMain ated Table Main Assoc Data Table Data Traffic Manager Output Input Fabric Framer or MAC Data Path Figure 3 shows multiple iAPs attached to a Silicon Access Networks iFlow Packet Processor (iPP). The iPP provides the packet header processing and field extraction functions for building iAP request messages. The multi-threaded capability of the iAP is utilized by the iPP to concurrently initiate up to 64 different operations (lookups, table updates, statistics) providing a data path processing throughput of 20 Gbps. iAP iAP AssociMain ated Table Main Assoc Data Table Data iAP Optics iFlowTM Address Processor Product Brief www.siliconaccess.com Figure 3: Multiple iAP Line Card Configuration COMPETITIVE CHIP COUNT COMPARISON FOR 256K IPV4 LOOKUP TABLE Vendor Device Count SRAM Count Total Devices Silicon Access Networks 1 iAP None 1 Lara Networks (Cypress) 1 LNI8010 2 LNI7040 1-4 x32 SSRAM 4-7 Netlogic Microsystems 2 CFP3128 (or equivalent for specific NPU) 1-4 x32 SSRAM 3-6 SiberCore 4 Ultra-2M TCAMs 1-4 x32 SSRAM 5-8 BASIC SPECIFICATIONS Part Number Package iAP SNI20201-C100-B0 520-pin HSBGA CONTACT US Size Frequency Voltage 35 x 35 mm 133 MHz 1.2 V core, 3.3 V input/output NOTICES Information in this document is subject to change without notice. Copyright (c) 2002 Silicon Access Networks, Inc. All rights reserved. S A N J O S E H E A D Q U A RT E R S 211 River Oaks Parkway, Suite 201 San Jose, CA, USA 95134 Phone: +1 (408) 545-1100 | Fax: +1 (408) 577-1940 Silicon Access and iFlow are trademarks of Silicon Access Networks. Other trademarks and trade names found in this document refer either to the entities claiming the trademarks and trade names, or their products. Silicon Access Networks disclaims any proprietary interest in trademarks and trade names other than its own.