iAPSNI20201-C100-B0 - Silicon Access Networks, Inc.

A High-Density MAC and CIDR Table Processor

iFlow™ Address Processor Product Brief

www.siliconaccess.com

Figure 1: iFlow Address Processor Block Diagram

DESCRIPTION

As netwo rk dat a rates ha ve in cre as ed to 1 0 g iga bi ts per

second and higher, performance demands on the

address lookup function have soared to more than 50

million loo ku ps per second. Software-based solu tio ns

cannot keep up, forcing designers to employ expensive

and power-hungry , terna r y-CAM s (TCAM s). The iFl ow

Address Processor (iAP) provides a complete

subsystem-on-a-chip solution for address lookups that

solves many of the problems associated with standard

TCAMs and TCAM-based coprocessor products.

The iAP is a high-density address and flow search

engine for exact or longest-prefix matches on

packetized data. With a peak rate of 65 million lookups

per second, the iAP ca n p erfo r m m or e th an tw o l oo kup s

per minimum length packet at OC-192 speeds. An on-

chip table size of 256K IPv4 entries, combined with

integrated memory, delivers an unmatched level of

integration.

FEATURES

BLOCK DIAGRAM

• Single-chip Layer 2/3/4 lookup coprocessor that

integrates the equivale nt of a 9-Mbit TCAM, tw o levels

of associa ted me mory, statis tic s eng ine and interf ac e

FPGA/ASIC

• 65 mill ion look ups per sec ond with determinis tic resul t

latency and no key-size penalties

• Supports 16 ind ependent ta bles with conf igurab le key

sizes

• Expandable to as many as eight iAPs providing up to

two million IPv4 table entries

• Supports MAC, N-tuple flows, IPv4 and IPv6 (with

VPN tag) lookups without requiring bank

segmentation

• Two lev els of i nteg rate d as s oci ate d da ta enables on e

lookup to provide the search result plus up to 48 bits

of per-entry associated data and 256 bits of per-hop

associated data

• 64 concurre nt look up cont exts supp ort multi -thr eaded

NPUs such as the iFlow Packet Processor (iPP)

• On-the-fl y modifi cation of ass ociat ed data fields us ing

on-chip ALU (performed in parallel with lookup)

• Table management in hardware (transparent to user)

• Up to one mi llion i nserts o r deletes per sec ond with no

impact on lookup rates

• Innova tive powe r manage ment requ ires les s than 5W

(versus up to 20W required for non-integrated

solutions)

• ECC protection on all memories for unmatched

reliability

• 32-, 64-, or 96-bit, 83-133MHz Zero Bus Turnaround

(ZBT) or Double Cycle Deselect (DCD) synchronous

SRAM interface

• Standard 0. 13 micron, 1.2V CMOS process

• 520-ball BGA package

Servi ce Rate

Manager

Request

Assembler

Memory Result Buffer Memory

Lookup

Table

Per-Hop

Associated

Memory

ZBT or DCD 32-, 64-, 96-bit @ 83-133 MHz

Pipelined Lookup

ALU

Associated

Memory

iFlow Address Processor

A High-Density MAC and CIDR Table Processor

iFlow™ Address Processor Product Brief

www.siliconaccess.com

APPLICATIONS

The iAP supports a wide range of applications and

configurations to address the requirements of next-

generation Internet switches and routers. Figure 2

shows a gene ric l ine -ca r d app li cat ion where a merch an t

network processor or in-house ASIC utilizes iAP lookup

services ov er an S RAM interface. T he iAP, as a

lookas ide co proces sor to the ma in data path p roc essin g

unit, receives lookup fields extracted by the network

processor and returns the result of the lookup and the

associated data.

Figure 3 shows multiple iAPs attached to a Silicon

Access Networks iFlow Packet Processor (iPP). The

iPP provides the packet header processing and field

extraction functions for building iAP request messages.

The multi -threade d capabili ty of the iAP is utili zed by the

iPP to concurrently initiate up to 64 different operations

(lookup s, table updates , statis tics) pro viding a dat a pat h

processing throughput of 20 Gbps.

In formati on i n th is do cument is sub j e ct to ch a nge wi thout n o tic e .

Silico n Ac c ess and iFlow are tr adema rk s of S ilic on Acce ss N etwork s .

Other trademarks and trade names found in this document refer either to the entities claiming

the trademarks and trade names, or their products. Silicon Access Networks disclaims any

proprietary int erest in tradema rk s and trad e names other tha n it s ow n.

SAN JOSE HEADQUARTERS

211 River Oa ks Parkway, Suite 201

San Jose, CA, USA 95134

Phone: +1 (408) 545-1100 | Fax: +1 (408) 577 -1940

Figure 2: Generic Line Card Configuration Figure 3: Multiple iAP Line Card Configuration

COMPETITIVE CHIP COUNT COMPARISON FOR 256K IPV4 LOOKUP TABLE

Vendor Device Count SRAM Count Total Devices

Silicon Access Networks 1 iAP None 1

Lara Networks (Cypress) 1 LNI8010

2 LNI704 0 1-4 x32 SSRAM 4-7

Netlogic Microsystems 2 CFP3128 (or equivalent for specific NPU) 1-4 x32 SSRAM 3-6

SiberCore 4 Ultra-2M TCAMs 1-4 x32 SSRAM 5-8

BASIC SPECIFICATIONS

Part Number Package Size Freque ncy Volt age

iAP SNI20201-C100-B0 520-pin HSBGA 35 x 35 mm 133 MHz 1.2 V core, 3.3 V input/output

iAP

Assoc

Data

Main

Table

NPU or ASIC

Optics

Framer or MAC

Fabric

Data

Path

iAP

Associ-

ated

Data

Main

Table

iAP

Assoc

Data

Main

Table

iAP

Associ-

ated

Data

Main

Table

iAP

Assoc

Data

Main

Table

iFlow 20Gbps

Packet

Processor

Input

Output

Traffic

Manager