PRELI M INARY (MS0945-XXXSP/FP) Notice: These are not a final specification. Some parametric limits are subject to change. MITSUBISHI MICROCOMPUTERS M50940-X XXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The M50940-XXXSP, the M50941-XXXSP and the M50945 -XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. All are housed in a 64-pin shrink plastic molded DIP. These single-chip microcomputers are useful for business equipment and other consumer applications. In addition to their simple instruction set, the ROM, RAM, and I/O addresses are placed on the same memory map to enable easy programming. The differences between the M50940-XXXSP, the M50941 -XXXSP and the M50945-XXXSP are noted below. The fol- lowing explanations apply to the M50940-XXXSP. Speci- fication variations for other chips, these are noted accor- dingly. Type name ROM size RAM size M50940-XXXSP 4096 bytes 128 bytes M50941-XXXSP 8192 bytes 192 bytes M50945-XXXSP 16384 bytes 256 bytes The differences between the M50940-XXXSP and the M50940-XXXFP are the package outline and the power dis- sipation ability (absolute maximum ratings). FEATURES @ Number of basic instructions @ instruction execution time rereaes 2us (minimum instructions at 4MHz frequency) @ Single power supply f(Xiy)=4MHZ-er 5V+10% (Xin) =AMHZe 3~5.5V @ Power dissipation normal operation mode (at 4MHz frequency) ---- 15mW low-speed operation mode (at 32kHz frequency for clock function) de ee eee e nescence enee eens ee eee seen eeeen nannies 0.3mW @ Subroutine nesting ----:"""- 64 levels (M50940) 96 levels (M50941, M50945) @ Interrupts 8 types, 5 vectors @ 8-bit timers 3 (2 when used as serial 1/0) @ 16-bit timer 1 (Two 8-bit timers make one set) @ Programmable I/O ports (Ports P3, P4) srr 16 e Input ports (Ports IN, R) rrr Sere eT eCSeeES ee Cte eres, 12 High-voltage output ports (Ports PO, P1) srr 16 @ High-voltage programmable 1/O ports (Port P2) vo 8 Serial I/O (8-bit) dence neces te eee cena ee eee eee seen eee nee eee tae EE 1 @ A-D conversion ::::::- -8-bit, 8 channel e PWM function ence eee eee eee eee rent eee en eee nent eeeeeereaeaneenaaae 1 @ Two clock generator circuits (One is for main clock, the other is for clock function) APPLICATION Microwave oven, Air conditioner, Fan heater Office automation equipment, Copying machine, Medical instruments VCR, TV, Audio-visual equipment PIN CONFIGURATION (TOP VIEW) Reference J voltage input = Veer * UL 64 Voc | IN; > 2] 3) Vee in, ~ BJ fea} P20 | | IN, > [2 Isi]<+ P2, | GE 60) +> i Input port IN Na BI fal Pee High- IN3 Ey 59] ++ P2s t voltage IN, + [7] 8] ++ P2, | VO | IN, > EE is] <> P2, | Port P2 | INo [3] SB)+> P25 P4, + ( 5] +P2, | P4, ++ [1 [24] * PO, pa, > 1 53] + PO, | t oT 2) VO port P4 pa, ++ = = = 2] + PO, High- Page> TE o ogo oj > POs voltage o Oo pa, + [is] Be Bo & (+ PO. | output a2aes | pa, + [i] x x x a5] + PO, ; Port PO | Pao fl] << Kf] POG ae <x x x P3)/Sanv BB] OO HH [7] PO; p3,/cik++ [a] 9 9 % fe] Pt. P3</Sour + 2] [5] Pi, P3./Siv + BU rea] Pi, 1/0 port P3 P3,/T, > EI aay > Pl, vowage P3,/T, 23} [42] Pl, output p3,/INT, ++ Ba fa} Pi, | potrt | P3)/INT; + a] Pt, | CNVss ee} 33) Pt, | Pull-down Reset input RESET EI [38] -Ve voltage jt Clock input Xin [} [37] + Ro | np Clock output Xourt BI [36] -R, | input Clock input for _. _ | port R timer function Xen & fs) Re | Clock output = Xcout El [34] Rs for timer function Vss 32 33) + Timing output Outline 64P4B 00 GBS OSS ES SIMO TOS SZzRRLKLRLELLLaAaaaaaaa tttetrtrptptrtrrttiittt [s7Jsefssfsafss]s2]51 Eleaf efefefspey]eofsofze[37] P2, ++ [58] [36] Vp P2, + [5] NC P2. ++ (60) Ro P2, + [a] R, Pe a M50940-XXX FP a) AVcc or Ra Vv [0]> p Vex M50941-XXXFP Ves AVss or [28] > Xcour Vrer Xen IN; [&] M50945-XXXFP [6] > Xour INg [69] Xn \Ns5.> NC IN, NC (Ny + RESET ne GEV Papel sf of20) ttt teedpegegrgeeret Nr OD POM eONTAxY EES ay 2223 22TF2TH 33 BSc eS | Z Sogeee seo aoe aa Outline 72P6 NC : No connection fe ESMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER yeuBis josyu0D Japooep uononsysuy (8) se1s1B91 YOON sul Od Yod yndjno 1S ddA jndur aBey0a aoUaJaJOY a6ey0A-yuBiy (8) L dawly 8) LL ens SSANOD -AV ld od yndyno 26e}104-y61H SSA lp JO4}U0D WMd (8) SL g seu (8) bb pb sow 3A yndur aBbeyjoa uMOp-1iNg DA @d uod O/| abeyoa-y6iH 1NI (8)S (1 AION) WOu 49yulod yoR]\S saikq_ 960r ASXXX-SPBOGW 40) Sa1Aq QG7 PUB dSXXX-1PEOSW 40) SaxXq 7G}: Z dSXXX-SPEOSW 40} Sa1Kq ~REg] PUL dSXXX-IYBOSW 40) Sa1dq 7618 : | SION bd vod O/| yd vodynduy Ny od ynduy INI 8 (B)A (8) x saqsi6a1 sovejnwnsoy dun e160; \ 419\s1B91 xapul J9\816a1 xapu| smes pue JOSSA901g onewuy 19-8 (8)"0d (8)"Od 49\uNnoo 4ayunoo (2 SION) wei6olq wesbold sardq gz] WV yno19 Bunesauab 490/95 19834 jndul jasay bbb de LNODy NID % Lnoy Ny yoouny UOHOUNY yndyno ydyno yndui yoojo 4390/9 Burt, YOOID yOOID 4JOy yNdjNO 104 yndus 490/19 49019) WVHSVId NOO1E dSXXX-0r60SW oe SES 248MITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONS OF M50940-XXXSP Parameter Functions Number of basic instructions 69 Instruction execution time 2us (minimum instructions, at 4MHz frequency) | Clock frequency 4. 2MHz (main ctock input), 32kHz (for clock function) Memory size ROM 4096bytes (8192bytes for M50941-XXXSP 16384 bytes for M50945-XXXSP) RAM 128bytes (192bytes for M50941-XXXSP 256 bytes for M50945-XXXSP) PO, P1 Output B-bitX 2 P2 vo 8-bitX1 Input/Output ports P3, P4 70 8-bitX2 IN Input 8-ch analog input (This port is in common with 8-bit parallel digital input) R Input 4-bitX1 Serial /O 8-bitX1 8-bit timerX3, (2 when serial [/O is used) Timers 16-bit timerX1, (combination of two 8-bit timers) Subroutine nesting 64 Levels (max.) (96 Levels (max.) for M50941-XXXSP and M50945-XXXSP} Interrupt Two external interrupts, three timer interrupts (or two timers, one serial I/O) Clock generating circuit Two built-in circuits (ceramic or quartz crystal oscillator) Supply voltage 6V+10%(at (Xin) =4MHz), 3.0~5.5V(at f(Xin) S1.0MHz) At high-speed operation 15mW (at f (Xin) =4MHz) Power dissipation At low-speed operation 0.3mW (at f (Xow) =32kHz) At stop mode 1A (at clock stop) 5V (port P3, P4) Input/Output voltage Input/Output Veo 36V (port PO, P1, P2) characteristics \ 12mA (port PO, P1, P2: high-voltage P-channel open drain output) Output current t 5~+10mA (port P3, P4: CMOS tri-state output) Memory expansion Possible Operating temperature range 10~70'C Device structure CMOS silicon gate Package M50940-XXXSP, M50941-XXXSP, M50945-XXXSP 64-pin shrink plastic molded DIP M50940-XXXFP, M50941-XXXFP, M50945-XXXFP 72-pin plastic molded QFP MITSUBISHI 2-49 ELECTRICMITSUBISH! MICROCOMPUTERS MS0940-XXXSP/FP,M50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION T . Input/ Pin Name Functions output Voc Supply voltage Power supply inputs 5V+10% to Voc, and OV to Vs5. Vss CNVss CNVss This is usually connected to Vss. Ve Pull-down voitage input This is the input voltage pin for the pull-down transistor of ports PQ, P1 and P2. RESET Reset input Input To enter the reset state, the reset input pin must be kept at a L" for more than 2us (under normal Voc conditions). if more time is needed for the crystal oscillatior to stabilize, this L condition should be main- tained for the required time. Xin Clock input Input These are |/O pins of internal clock generating circuit for main clock. To contro! generating frequency, an external ceramic or a quartz crystal oscillator is connected between the Xin and Xour pins. If an external Xout Clock output Output clock is used, the clock source should be connected the Xi pin and the Xour pin should be left open. Timing output Output This is the timing output pin. Xcin Clock input for Input This is the I/O pins of the clock generating circuit for the clock function. To control generating frequency, clock function an external ceramic or quartz crystal oscillator is connected between the Xin and Xcout pins. If an external clock is used, the clock source should be connected to the Xcin pin and the Xcour pin shoutd be left open. Xcout Clock output for Output This clock can be used as a program controlled the system clock. clock function P0o~ PO; ; Output port PO Output Port PO is an 8-bit output port. Output structure is high-voltage P-channel open drain. A pull-down transistor is built-in between the Vp pin and this port. At reset, this port is set to a L" level. Ptg~P17 | Output port P1 Output Port P1 is an 8-bit output port and has basically the same functions as port PO. P29~P2z7 | 1/0 port P2 Vo Port P2 is an 8-bit 1/O port with directional registers allowing each 1/0 bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is P-channel open drain. A pull- down transistor is built-in between the Vp pin and this port. P39-~P37 | I/O port P3 0 Port P3 is an 8-bit I/O port with CMOS tri-state output. The other functions are basically the same as port P2. P39, P3,, P32 and P33 pins are in common with INT, INT;, Tz, and Ty, respectively. When serial |/O is used, P37, P3, P35, and P34, work as Sapy, CLK, Sour, and Sin, pins, respectively. P4o~P4z7 | 1/0 port P4 VO Port P4 is an 8-bit I/O port with CMOS tri-state output. The other functions are basically the same as port P2. Ro~R3 Input port R Input Port R is a 4-bit input port. INo~IN7z Analog input port IN Input Port IN is the analog input pin to the A-D converter. It also has a dual function and works as a normal input port. AVoc Voltage input for A-D This is the power supply input pin for the A-D conveter. Vrer Reference voltage Input This is the reference voltage input pin for the A-D conveter. input 250 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER BASIC FUNCTION BLOCKS MEMORY A memory map for the M50940-XXXSP is shown in Figure 1. Addresses F000,, to FFFFi are assigned to the built-in ROM area which consists of 4096 bytes (8192 bytes for M50941-XXXSP and 16384 bytes for M50945-XXXSP) . Addresses FFOQ,, to FFFFig are a special address area (special page). By using the special page addressing mode of the JSR instruction, subroutines addressed on this page can be called with only 2 bytes. Addresses FFF4,. to FFFFy,. are vector addresses used for the reset and inter- rupts (see interrupt chapter). Addresses 0000, to OOFF1 are the zero page address area. By using the zero page addressing mode, this area can also be accessed with 2 bytes. The use of these addressing methods will greatly re- duce the object size required. The RAM, I/O port, timer, etc. addresses are already assigned for the zero page. Addresses 0000,, to 007F 1, are assigned for the built-in RAM which consists of 128 bytes (192 bytes for M50941-XXXSP and 256 bytes for M50945- XXXSP) of static RAM. This RAM is used as the stack dur- ing subroutine calls and interrupts, in addition to data storage. Decimal 0000, RAM (128 bytes) for RAM (192 bytes) for M50941-XXXSP| M50940-XXXSP 0 7 7 0E0:6| Port PO y O0E 115 / 00E2;| Port P1 00E3, and 007F ig Zero page { M50945-XXXSP OOBF 16 Not used / / O0E4164 Port P2 _ 00E5.6[pon P2 Dacia V O0E6 15 OOED.s OOF Fi6 QOE7 6 RAM (64 bytes) for M50945-XXXSP 013F i 255 00E8,,) Port P3 di ti T \ 00E9,,|Port P3 fegister \ OOEA,,| Port P4 C000, E00016 Not used \ _ OOEB.e)Port Pa eect \ OOEC 6] Port IN \ OOED i OOEE.. F000,. \ OOEF,,| A-D register \ 00F 016 [Port R \ 00F 146 O0F2,,] A-D start address \ 00F3,] A-D control register ROM FFO0,. (16384 bytes) for M50945 ~XXXSP ROM ROM (8192 (4096 bytes) bytes) 450941 or -XXXSP xP Special page for FFF4,, \ 00F 44, \ OOFS,,| Timer 4, 5 controi register \ OOF6,,] Serial 1/O mode register \ 00F7,,| Serial 1/0 register \ OOF 816 \ OOF9,6| Timer 1 subroutine Address OOFA,,] Timer 2 call 4 int, + Address H INT. Address Address H L Serial 1/0 or \ OOFB,.6f Timer 3 Address Address H Timer3 \ Timer2 \ H OOFC | Timer 4 Address Address H tl Timert or A-D \ 90FD,6| Timer 5 Address Address H LL FFFFi Address Address H INT; \ OOFE,] Interrupt control register 65535 RESET L \ OOFFi6 Timer control register Fig.) Memory map oe ESMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CENTRAL PROCESSING UNIT (CPU) The CPU consists of 6 registers and is shown in Figure 2. ACCUMULATOR (A) The 8-bit accumulator (A) is the main register of the micro- computer. Data operations such as data transfer, input/out- put, etc., is executed mainly through the accumulator. INDEX REGISTER X (X) The index register X is an 8-bit register. In the index regsi- ter X addressing mode, the value of the OPERAND added to the contents of the index register X specifies the real address. When the T flag in the processor status register is set to 1, the index register X itself becomes the address for the second OPERAND. INDEX REGISTER Y (Y) The index register Y is an 8-bit register. In the index regis- ter Y addressing mode, the value of the OPERAND added to the contents of the index register Y specifies the real address. 7 0 A Accumulator 7 0 x Index register X 7 0 Y Index register Y 7 0 S Stack pointer 15 7 0 PCy PCL Program counter 7 0 es Ni vj T/ Bi] Dy tt] Zz) c Processor status register | L_ Carry flag Zero flag Interrupt disable flag = Decimal mode flag Break flag -_____\-_____-- index X mode flag Overflow flag Negative flag Fig.2 Register structure ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER STACK POINTER (S) The stack pointer is an 8-bit register that contains the address of the next location in the stack. It is mainly used during interrupts and subroutine calls. The stack pointer is not automatically initialized after reset and shouid be initial- ized by the program using the TXS instruction. When an interrupt occurs, the higher 8 bits of the program counter is pushed into the stack first, the stack pointer is decremented, and then the lower 8 bits of the program counter is pushed into the stack. Next the contents of the processor status register is pushed into the stack. When the return from interrupt instruction (RTI) is executed, the program counter and processor status register data is pop- ped off the stack in reverse order from above. The Accumulator is never pushed into the stack automati- cally, so a Push Accumulator instruction (PHA) is provided to execute this function. Restoring the accumulator to its previous value is accopmlished by the Pop Accumulator in- struction (PLA). It is executed in the reverse order of the PHA instruction. The contents of the Processor Status Register (PS) are pushed and popped to and frome the stack with the PHP and PLP instructions, respectively. During a subroutine call, only the Program Counter is pushed into the stack. Therefore, any registers that should not be destroyed should be pushed into the stack manually. To return from a subroutine call, the RTS instruction is used. PROGRAM COUNTER (PC) The 16-bit program counter consists of two 8-bit registers PC,, and PC,. The program counter is used to indicate the address of the next instruction to be executed. PROCESSOR STATUS REGISTER (PS) The 8-bit PS is composed entirely of flags used to indicate the condition of the processor immediately after an opera- tion. Branch operations can be performed by testing the Carry flag (C), Zero flag (Z), Overflow flag (V) or the Negative fiag (N). Each bit of the register is expianined below. 1. Carry flag (C) The carry flag contains the carry or borrow generated by the Arithmetic Logic Unit (ALU) immediately after an op- eration. It is also changed by the shift and rotate instruc- tions. The set carry (SEC) and clear carry (CLC) instruc- tions allow direct access for setting and clearing this flag. 2. Zero flag (Z) This flag is used to indicate if the immediate operation generated a zero result or not. If the result is zero, the zero falg will be set to 0. If the result is not zero, the zero flag will be set to 1. 3. Interrupt disable flag (1) This faig is used to disable all interrupts. This is accom- plished by setting the flag to 1. When an interrupt is accepted, this flag is automatically set to 1 to prevent from other interrupts until the current interrupt is completed. The SEI and CLI instructions are used to set and clear this flag, respectively. 4. Decimal mode flag (D) The decimal mode flag is used to define whether addition and subtraction are executed in binary or decimal. If the decimal mode fiag is set to 1, the operations are ex- ecuted in decimal, if the flag is 0, the operations are ex- ecuted in binary. Decimal correction is automatically ex- ecuted. The SED and CLD instructions are used to set and clear this flag, respectively. 5. Break flag (B) When the BRK instruction is executed, the same operations are performed as in an interrupt. The address of the inter- rupt vector of the BRK instruction is the same as that of the lowest priority interrupt. The contents of the B flag can be checked to determine which condition caused the interrupt. If the BRK instruction caused the interrupt, the B flag will be 1, otherwise it will be 0. 6. Index X mode flag (T) When the T flag is 1, operations between memories are executed directly without passing through the accumulator. Operations between memories involving the accumulator are executed when the T flag is 0 (i.e., operation results between memories 1 and 2 are stored in the accumulator). The address of memory 1 is specified by the contents of the index register X, and that of memory 2 is specified by the normal addressing mode. The SET and CLT instructions are used to set and clear the T flag, respectively. 7. Overflow flag (V) The overflow flag functions when one byte is added or sub- tracted as a signed binary number. When the result ex- ceeds +127 or 128, the overflow flag is set to 1. When the BIT instruction is executed, bit 6 of the memory location is input to the V flag. The overflow flag is reset by the CLV instruction and there is no set instruction. 8. Negative flag (N) The negative flag is set whenever the result of a data trans- fer or operation is negative (bit 7 is 1). Whenever the BIT instruction is executed, bit 7 of the memory location is input to the N flag. There are no instuctions for directly setting or resetting the N flag. oatsMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,MS50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER INTERRUPT The M50940-XXXSP can be interrupted from eight sources; INT,, timer 1 or A-D, timer 2, timer 3 or serial I/O, and the INT, or BRK instruction. The value of bit 2 of the serial 1/O mode register (address OOF6,,) determines whether the interrupt is from timer 3 or from serial I/O. When bit 2 is 1 the interrupt is from serial 1/0, and when bit 2 is 0 the interrupt is from timer 3. Also, when bit 2 is 1, parts of port 3 are used for serial I/O. Bit 3 of the A-D control register (address 00F3,,) determines if an interrupt is from timer 1 or from the A-D. When bit 3 is 0, the interrupt is from timer 1, when bit 3 is 1 the inter- rupt is from the A-D. These interrupts are vectored and their priorities are shown in Table 1. Reset is included in this table since it has the same function as an interrupt. When an interrupt is accepted, the contents of certain reg- isters are pushed into specified locations, (as discussed in the stack pointer section) the interrupt disable flag (I) is set, the program jumps to the address specified by the in- terrupt vector, and the interrupt request bit is cleared auto- matically. The Reset interrupt is the highest priority inter- rupt and can never be inhibited. Except for the Reset inter- rupt, all interrupt are inhibited when the interrupt disable flag is set to 1. All of the other interrupts can further be controlled individually via the interrupt contro! register shown in Figure 3. An interrupt is accepted when the inter- rupt enable bit and the interrupt request bit are both 1 and the interrupt disable flag is O. The interrupt request bits are set when the following conditions occur: (1) When the INT, or INT> pins go from H to L (2) When the contents of timer 1, timer 2, timer 3 (or the serial 1/O counter) go to 0. These request bits can be reset by the program but can not be set. Since the BRK instruction and the INT, interrupt have the same vectored address, the contents of the B flag must be checked to determine if the BRK instruction caused the in- terrupt or if INT, generated the interrupt. 7 | Interrupt control register {Address O0FE,,) Table 1. Interrupt vector address and priority. Interrupt Priority Vector address RESET 1 FFFF 16, FFFEi6 INT, 2 FFFDi6, FFFCi6 Timer 1 or A-D 3 FFFBi6, FFFAig Timer 2 4 FFFQi6, FFF8;6 Timer 3 or serial 1/0 5 FFF716, FFF64 INT2(BRK) 6 FFF5,5, FFF416 0 HCH Interrupt request Interrupt disable flag | Reset Bit 7: INT, pin interrupt request bit Bit6 : INT, pin interrupt enable bit Bit5 Timer 2 interrupt request bit Bit 4: Timer 2 interrupt enable bit Bit 3: Timer 3 interrupt or serial I/O interrupt request bit Bit 2 : Timer 3 interrupt or seruial !/O interrupt enable bit Bit 1 : INT; pin interrupt request bit BitO : INT> pin interrupt enable bit Timer control register (Address OOFF 16) Bit 7 : Timer 1 interrupt or A-D interrupt request bit Bit 6 Timer 1 interrupt or A-D interrupt enable bit Bit5 : Timer} count stop bit Bit 4: Timer 3 count source selection bit Bit 3 : Timer 2 count source selection bit Bit 2 > Timer count source selection bit Bit}: ) . ' Processor mode bit Bito: ! Fig.3 interrupt control 254 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS M50940-X XXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMER The M50940-XXXSP has five timers; timer 1, timer 2, timer 3, timer 4 and timer 5. Since P3 (in serial 1/O mode) and timer 3 use some of the same architecture, they cannot be used at the same time (see serial 1/O section). The count source for each timer can be selected by using bit 2, 3 and 4 of the timer control register (address OOFF,,), as shown in Figure 5. For more details about timer 4 and timer 5, see the PWM section. A block diagram of timer 1 through 5 is shown in Figure 5. All of the timers are down count timers and have 8-bit latches. When a timer counter reaches 0, the contents of the reload latch are loaded into the timer and the next count pulse is input to a timer. The division ratio of the tim- ers is 1/(n+1), where n is the contents of the timer latch. The timer interrupt request bit is set to 1 at the next clock pulse after the timer reaches 0. The interrupt and timer control registers are located at addresses OOFE,. and OOFF,., respectively (see Interrupt section). The starting/ stopping of timer 1 can be controlled by bit 5 of the timer control regsiter. If bit 5 (address OOFF;,) is 0 the timer starts counting and when bit 5 is 1, the timer stops. After a STP instruction is executed, timer 2, timer 1, and the clock ( divided by 4) are connected in series (regardless of the status of the 2 through 3 of the timer control register). This state is canceled if the timer 2 interrupt request bit is set to 1, or if the system is reset. Before the STP instruc- tion is executed, bit 5 of the timer control register (timer 1, count stop bit), and bit 4 of interrupt control register (timer 2 interrupt enable bit) bit 6 of the timer control register (timer 1 interrupt enable bit) must be set to 0. For more PWM The M50940-XXXSP has a pulse width modulated (PWM) output control circuit. The circuit outputs a variable duty cy- cle signal that can be used for a programmable pulse width and frequency. Timers 4 and 5 are used for the PWM. The control of these timers is explained in Figure 6 and the rec- tangular waveform is shown in Figure 7. At reset, the PWM output is in a floating state. When timers 4 and 5 are not used for PWM control, they can be cas- caded and used as a 16-bit timer. However, when used as a 16-bit timer, the interrupt function (such as timer 1 through timer 3) cannot be used. details on the STP instruction, refer to the oscillation circuit section. 7 0 | | | Timer control register (Address OOFF,.) iL Processor mode bit 00 : Singte-chip mode 01 : Memory expanding mode 10 : Microprocessor mode 11 Eva-chip mode Timer 1 count source selection bit 0: ddivided by 4 12 Xen (clock for clock function) Timer 2 count source selection bit 0 Timer overflow signal 1: Xen (clock for clock function) Timer 3 count source selection bit 0: divided by 4 1} Timer 2 overflow signal Timer 1 count stop bit 0 : Count start 1 : Count stop i________ Timer | or A-D interrupt enable bit 0 : Interrupt disable |: Interrupt enable Timer 1 or A-D interrupt request bit 0 : No interrupt request 1: With interrupt request Fig.4 Structure of timer control register Timer 4,5 Control register (address 00F5,) P3,/T2 Output selection bit 0 : P3, (paratlel port) 1! Tz (timer output) Timer 4, 5 function mode select bit 0 : Timer mode 1 | PWM mode Fig.6 Structure of timer 4, 5 contro! register PWM Timer 4 Timer 5 Timer 4+ Timer 5 Fig.7 PWM rectangular wave form oe eeMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,M50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 8 Data bus Timer 1 latch (8) Xcin 1/2 8 i ADM; 1/4 1/4 Timer 1 (8) >) Timer) or A-D interrupt bit Xin SM, TM2 TMs CT 8 j oo Timer 2 latch (8) By e Timer 2 (8) Timer 2 interrupt request bit TM3 L 8 8 Timer 3 latch (8) By SM, Timer 3 (8) Timer 3 or serial !/O interrupt request bit TM, L 8 P3 latch L v2] P3,/T, (> SM SMa SM, 00, 01 : External clock CLK : i P3 10 : 1/2 of timer 3 Selection gate (at reset the shaded 6 1151/4 of , ot side is connected.) Sync. clock Seralvo TM : Timer contro! register counter (3) SM_ : Serial 1/O mode register SM, SM, TC : Timer 4, 5 contro! register Sour ADM: A-D control register SM2 MSB us| Sin Serial 1/0 P34 o= register (8) 8 Snov J Ms +8. P3, +8 ____] Timer 4 latch (8) By Timer 4 (8) F/F 8 watt Timer 5 latch (8) 8 TC, i Timer 5 (8) 1/2 TC, TCo 8 P3,/T, Ow Fig.5 Block diagram of timer 1 through 5 _ atte MTSUBISH ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O A block diagram of the serial 1/O is shown in Figure 8. In the serial 1/O mode, the receive ready signal (Sarpy), syn- chronous input/output clock (CLK), and the serial I/O (Sour, Sin) pins are used as P3;, P3., P35, and P3,4, re- spectively. The serial 1/O mode register (address O0F6,,) is an 8-bit register. Bits 1 and 0 of this register is used to select a syn- chronous clock source. When these bits are (00) or (01), an external clock from P3, is selected. When these bits are (10), the overflow signal (from timer 3) divided by two be- comes the synchronous clock. Therefore, changing the tim- er period wil! change the transfer speed. When the bits are (11), the internai clock divided by 4 (ie. 4us at 4MHz) becomes the clock. Bits 2 and 3 decide whether parts of P3 will be used as a serial |/O or not. When bit 2 is 1, P3. becomes an I/O pin of the synchronous clock. When an internal synchronous is selected, the clock is output from P3,. If an external syn- chronous clock is selected, the clock is input to P3g. And P3, will be a serial output and P3, will be a serial input. To use P3, as a serial input, set the directional register bit which corresponds to P3, to 0. For more information on the directional register, refer to the 1/O pin section. Internal Divider clock by 4 or Srov P3, C) <j : circuit From internal clock 4 timer 2 Prescaler Di] 1/2 Serial |/O counter (3) Transfer clock (address OOFB,,) to timer 3 or serial 1/O interrupt request bit S P3,(.)}* >|mse Serial |/O register (8) LSB (address 00F7,.) igi f Data bus J _ | | | | | | | Serial |/O mode register (address 00F6,.) internal system clock Synchronous clock selection bit source selection bit 00 : External clock 0 Xw Ole; 12 Xen 10 : Timer 3 overflow signal divided by 2 11 : Timing divided by 4 Clock (Xin-Xour) stop bit Serial |/O port selection bit (P35, P35) 0: oscillation 0: Normai I/O port 1: stop 1: Seriai 1/O port P3,/T1 output selection bit Sroy signal output selection bit (P37) 0: Normal I/O port 0: Normal 70 port 1: Timer 3 overflow signal divided by 2 1+ Sry signal output pin Fig.8 Block diagram of serial 1/O MITSUBISHI 9-57 ELECTRICMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,M50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER To use:the serial I/O, bit 2 needs to be set to 1, if it is O P3g will function as a normal I/O. Interrupts will be gener- ated from the serial I/O counter instead of timer 3. bit 3 de- termines if P37 is used as an output pin for the receive data ready signal (bit 3=1, Spoy) or used as a normal I/O pin (bit 3=0"). The function of the serial I/O differs depending on the clock source; external clock or internal clock. internal clockThe Spoy signal becomes H during trans- mission or while dummy data is stored in the serial I/O reg- ister. After the falling edge of the write signal, the Sapy sig- nal becomes low signaling that the M50940-XXXSP is ready to receive the external serial data. The Saoy signal goes H at the next falling edge of the transfer clock. The serial |/O counter is set to 7 when data is stored in the serial I/O register. At each falling edge of the transfer clock, serial data is output to P3;. During the rising edge of this clock, data can be input from P3, and the data in the serial |/O register will be shifted 1-bit. Data is output starting with the LSB. After the transfter clock has counted 8 times, the se- rial 1/O register will be empty and the transfter clock will remain at a high level. At this time the interrupt request bit will be set. External clock If an external clock is used, the interrupt request will be set after the transfter clock has counted 8 times but the transfter clock will not stop. Due to this reason, the externa! clock must be controlled from the out- side. The external clock should not exceed 250kHz at a duty cycle of 50%. Timing diagrams are shown in Figure 9, and connections between two M50940-XXXSPs are shown in Figure 10. Serial {/O register write signa! Synchronous wo LELILILIU UU UU UU UU) Serial I/O output Sour \ EXD EEN NEY D, Serial 1/O input Sin Pf | ||) X_X_XX_X_X_X_X Receivable signal Srov L_} I | + | T | | | | t | y I Interrupt request bit set Fig.9 Serial {/O timing Sending side Receiving side Serial 1/O mode register Serial 1/O mode register P3, P3, bit 3 bit 0 bit3 bit 0 pop dye BREE Set the directional Set the directional register for P3, pin Synchronous clock register for P3, pin ni P36 P35 in input mode. in input mode. Serial data P35 P3, Fig.10 Example of serial I/O connection oe aSMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER The A-D converter circuitry is shown in Figure 11. The ana- log input ports of the A-D converter (INo~IN7) are in com- mon with the input ports of the data bus. The 6-bit A-D control register is located at address 00F3;.. One of the eight analog inputs is selected by bits 0, 1 and 2 A-D control register (address 00F3,) Analog input select bit of this register. bit 3 selects the interrupt source, either from oor nN timer 1 or the A-D itself. it bit 3 is O, then the interrupt re- O10 : IN quest is from timer 1, if it is 1, then it is from the A-D. 011 2 INg A-D conversion is accomplished by first selecting the ana- 100: IN, log channel (bit 0, 1) to be converted. bit 3 should also be 101 - INs set to 1 to select the A-D as the interrupt source. The " Ne conversion is started when dummy data is written into address 00F2,.. When the conversion is finished, an inter- A-D/timer 1 input select bit rupt is generated by the A-D and the digital data can be 0: Timer 1 read from the A-D register (address OOEF,,.). The end of 1. A-D the conversion is determined by either the A-D conversion A-D conversion speed switch bit end bit (bit 5 of the A-D contro! regiser) or an A-D interrupt 0: High speed * request bit (Address OOFFi). 1: Low speed The A-D conversion can also be programmed for high or A-D conversion end bit low speed conversions. This is accomplished by using the Q Under conversion A-D conversion speed switch bit (bit 4 of the A-D control 1: End conversion register). For more information on the electrical character- * High speed at =1MHz Low speed at =1MHz Convert speed; tan=72u5 Convert speed: tap = 28845 istics of the high and low speed conversions, refer to the electrical characteristics section. Port IN can also be used as an input port by reading data into address O0EC,,. However, this cannot be done during Fig.12 Structure of A-D control register A-D conversions. The A-D control register is shown in Figure 12. 5 Data bus 5 4 A-D control VAN register Timer 1 0 1 2 3 4 5 | address 00F3. (address 00EC;) TT ( va) Le ( __ a to timer 1 or " A-D control A-D interrupt request bit gs circuit IN; O--4 8 : 4 IN> O4 g | & Successive x approximation i INs 5 Comparator register (A-D register) (address OOEF 16) ' O4 = Na 3 s 2 Switch tree INs O- 4 2 4 Ns 4 3 | Ladder resistor IN7 C Z| AV, Vss Vrer cc Fig.11 A-D conversion circuit ne ES vsMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,MS0941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET CIRCUIT The M50940-XXXSP is reset according to the sequence shown in Figure 15. And starts the program from the address formed by using the content of address FFFF,, as the high order address and the content of the address FFFE, as the low order address when the RESET pin is held at L level for more than 2s while the power voltage is in the recommended operating condition and the crystal oscillator oscillation is stable and then returned to H level. Address (E O16) 906 (E 246) 0016 | (4) Port P3 directional register (E 946) -- 0 O46 oo - 0 O16 (F 6 a6) 00.6 | (F3s6)~| | |1[olojolo/o| (1) Port PO register (2) Port P1 register (3) Port P2 directional register (E 546) > (5) Port P4 directional register (E Big): (6) Serial 1/O mode register (7) A-D control register (8) Timer 4, 5 control register (F 546) - PLE LE fol 0 (9) Interrupt control register = (F E4,) -- 0 O16 | Sm CF Fug) 0 O16 (1 interrupt disable (pg) suse [TELE EL flag for precessor - status register 18 Progam citer PGy)orn es Contents of (PCy Since the contents of both registers other than those listed above (including timer 1, timer 2, timer 3, and the serial 1/O register) and the RAM are undefined at reset, it is necessary to set initial values. (10) Timer cotrol register Fig.13 Internal state of microcomputer at reset The internal initializations following reset are shown in Fig- ure 13. An example of the reset circuit is shown in Figure 14. When the power on reset is used, the RESET pin must be held L until the oscillation of Xin-Xour becomes stable. Power on M50940-XXXSP jan 4.5V RESET Voc ov 27 64 +_orx 0. i av 6v M50940-XXXSP ESET Voc 27 64 Supply voltage is ie oO detection circuit wl I | I t | | | | | Fig.14 Example of reset circuit ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,MS0941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER JW - - - _ SU 6 --4--- fou _JSLEFLILIL UL LL Lu aeser J Internal RESET [| SYNC mess - \ / GD, FF) 28") Reset address from the 8~12 clock cycles Note : Frequency relation of f(Xin) and dis f(Xiy) =4- The mark ? " means that the address is changing depending upon the previous state Fig.15 Timing diagram at reset VO PORTS (1) Port PO Port PO is an 8-bit output port with P-channel open drain and high voltage outputs (Vec-36V). Each pin has a built-in pull-down transistor connected to Vp. As shown in the memory map (Figure 1), port PO can be accessed at zero page memory address 00E0,. previously output vaiue to be read correctly even though the output voltage level is shifted up or down. Pins set as input are Vpp level and the signal levels can thus be read. When data is written into the input port, the data is latched only to the output register and the pin still remains in the high impedance state. Depending on the status of the processor status regis- (4) Port P3 ter (bit 0 and bit 1 of address OOFF,,), four different Port P3 is an 8-bit I/O port having CMOS outputs. Each modes can be selected; single-chip mode, memory ex- pin is shared with serial I/O, timer overflow (T1, T2) panding mode, microprocessor mode, and eva-chip and external interrupt input functions. These functions mode. These modes (excluding single-chip mode) remain the same even if the device is used in other have a multiplexed address output function in addition modes. to the I/O function. For more details, see the processor (5) Port P4 mode section. Port P4 is an 8-bit 1/O port with CMOS outputs. During Port P1 all modes except single chip mode, P4, and P4, func- In the single-chip mode, Port P1 has the same function tion as both SYNC and R/W outputs as well as I/O as PO. In the other modes, P1s functions are slightly ports (see processor mode section). different from PO's. For more details, see the processor (6) Port R mode section. Port R is a 4-bit input port. Port P2 (7) Port.IN Port P2 is an 8-bit |/O port with P-channel open drain Port IN is an 8-bit input port to the A-D converter. It can outputs. As shown in the memory map of Figure 1, port also be used as an input port by reading the input data P2 can be accessed as memory at address 00E4, of into address 00EC,,. However, this port cannot be read zero page. Port P2 has a directioan! register (address _ during A-D conversion. 00E5,,) which can be used to program each individual (8) Clock output pin bit as input (0) or as output (1). If the pins are programmed as output, the output data is latched to the port register and then output. When data is read from the output port the output pin level is not read, only the latched data in the port register is read. This allows a This is the timing output pin. When selected the main clock (Xiy-Xour) as the internal system clock, the clock frequency divided by four is outputed. However, when selected the clock for clock function (Xgw-Xcour), the clock frequency divided by two is outputed. are SEHMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,MS0941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Ports PO,P1 P-channel open drain high voltage port with pull-down resistors Data bus ~- Port latch Pe * Ponts PO, PI Vp Port P2 Directional register ] High voltage I/O port * with pull-down resistors Data bus Port latch H t__~--< [ Port P2 a <1 ~ O Vp Ports P3, P4 CMOS tri-state output Directional register * Ok d 1 1 Ports P3, P4 Data bus + Port latch Vss | Port R Input % P-channel open drain high voltage transistor Data bus %* & Mask option Port R Fig.16 Block diagram of port PO~P4 and port R (single-chip mode) a ate MTSURSH ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROCESSOR MODE By changing the contents of the processor mode bit (bit 0 and 1 of address OOFF,,), four different operation modes can be selected; single chip mode, memory expanding mode, microprocessor mode and evaluation chip (eva- chip) mode. In the memory expanding mode, microp- rocessor mode and eva-chip mode, PO~P2 can be used as multiplexed 1/O for address, data and control signals, as well as the normal functions of the I/O ports. Figure 18 shows the functions of ports PO~P2, and P4 corresponding to each mode. The memory map of the single-chip mode is illustrated in Figure 1, and the other modes are shown in Figure 17. By connecting the CNVss to Vgs, all four modes can be selected through software by changing the processor mode regsiter. Connecting CNVsg to Vcc automatically forces the microcomputer into microprocessor mode. Supplying 10V to CNVsg places the microcomputer in the eva-chip mode. The four different modes are explained as follows: FFFF Internal ROM (Note 1) _- wee F000. 010016 Timers, port P3 | . oes, P2 00E0, Port PO~ _ (Note 2) -- 007F x6) internal RAM 0000.6 Memory Eva-chip Microprocessor expanding mode mode mode Note 1 : E000,, for M50941 and C000,, for M50945. 2: OOBF,, for M50941 and MS0945. The shaded area is external memory area. 3: The 64 bytes from 0100,,_ to 013F,,_ are also internal RAM for M50945. Fig.17 External memory area in processor mode (1) Single-chip mode [00] The microcomputer will automatically be in the single- chip mode when started from reset, if CNVsgs is con- nected to Vss. Ports PO ~ P4 will work as original |/O ports. (2) Memory expanding mode [01] The microcomputer will be placed in the memory ex- panding mode when CNVsgg is connected to Vsg and the processor mode bits are set to 01. This mode is used to add external memroy when the internal mem- ory is not sufficient. (3) The lower 8 bits of address data for port PO is output when goes to the H state. When goes to the L state, PO retains its original !/O functions. Port P1s higher 8 bits of address data are output when goes to the H state and as it changes back to the L state it retains its original I/O functions. Port P2 retains its original output functions while is at the H state, and works as a data bus of D7 ~ Dy (including instruction code) while at the L state. Pins P4, and P4) output the SYNC and R/W control signals, respectively while is in the H state. When in the L state, P4, and P4p retain their original (/O functins. The R/W output is used to read/write from/to the out- side. When this pin is in the H state, the CPU reads data, and when in the L state, the CPU writes data. The SYNC is a synchronous signal which goes to the H state when it fetches the OP CODE. Microprocessor mode (10) After connecting CNVss to Vcc and initiating a reset, the microcomputer will automatically default to this mode. The relationship between the input level of CNVggs and the processor mode is shown in Table 2. In this mode, port PO and P1 are used as the system address bus and the original function of the I/O pin is lost. Port P2 becomes the data bus (D7~Dg) and loses its normal I/O functions. Port P4, and P4, become the SYNC and R/W pins, respectively and the normal I/O functions are lost. Eva-chip mode [11] When 10V is supplied to the CNVss pin, the micro- computer is forced into the eva-chip mode. This mode has almost the same function as the memory expanding mode except that it needs all its programs to come from the outside (including ROM programs). The main purpose of this mode is to evaluate ROM programs prior to masking them into the microcomputers internal ROM. JoesMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M5S0941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER , 0 0 1 1 \ TMs 0 1 1 0 Moce Singie-chip mode Memory expanding mode Eva-chip mode Microprocessor mode Port $ Port PO Ports P0;~ PO, Ports P0;~P0p Same as left Ports P0;~ PO, Address Output Address J LSI 2 Port P1 Ports Pt1;>~P1 Ports P1;~P1 Same as left Ports P1;~P19 Address Output Address \Comer | XEEXRENC TO ST Port P2 Ports P2)~P24 Ports P2;~P2, Same as left Ports P2,~P2p Output Data wn Data 1/0 Port Port D;~Do D;~Do | | Ports P47~P4 Ports P47~P42 Ports P4;~P4, xX 1/0 Port xX 1/0 Port 1/0 Port Port P4 Port P4, Same as left Port P4, Port P4o Port P4, Fig.18 Processor mode and functions of ports PO~P2, P4 Table 2. Relationship between CNVs, Pin Input Level and Processor Mode CNVss Mode Explanation Vss Single-chip mode The single-chip mode is set by the reset. * Memory expanding mode | All modes can be selected by changing the processor mode bit with the program. + Eva-chip mode * Microprocessor mode Voc * Eva-chip mode The microprocessor mode is set by the reset. * Microprocessor mode Eva-chip mode can be also selected by changing the processor mode bit with the program. 10V * Eva-chip mode Eva-chip mode only. 64 aie MTSURISH ELECTRICMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,M5S0941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The M50940-XXXSP has two internal clock generating cir- cuit. Figure 21 shows a block diagram of the clock generat- ing circuit. Normally, the frequency applied to the clock in- put pin X\, divided by four is used as the internal clock (timing output) . Bit 7 of serial |/O mode register can be used to switch the internal clock to 1/2 the frequency ap- plied to the clock input pin Xen. Figure 19 shows a circuit example using a ceramic (or crystal) oscillator. Use the manufactures recommended values for constants such as capacitance which will differ depending on each oscillator. When using an external clock signal, input form the Xw (Xen) pin and leave the Xour (Xcour) pin open. A circuit example is shown in Figure 20. The M50940-XXXSP has two low power dissipation modes; stop and wait. The microcomputer enters a stop mode when the STP instruction is executed. The oscillator (both Xin Clock and Xciw clock) stops with the internal clock held at H level. In this case timer 1 and timer 2 are forc- ibly connected and /4 is selected as timer 1 input. Before executing the STP instruction, appropriate values must be set in timer 1 and timer 2 to enable the oscillator to stabil- ize when restarting oscillation. Before executing the STP instruction, the timer 1 count stop bit must be set to supply (0), timer 1 interrupt enable bit and timer 2 interrupt en- able bit must be set to disable (0), and timer 2 interrupt request bit must be set to no request (0). Oscillation is restarted (release the stop mode) when INT,, INT2, or serial 1/O interrupt is received. The interrupt en- able bit of the interrupt used to release the stop mode must be set to 1. When restarting oscillation with an interrupt, the internal clock is held H until timer 2 overflows and is not supplied to the CPU. When oscillation is restarted by reset, L level must be kept to the RESET pin until the oscillation stabilizes because no wait time is generated. The microcomputer enters a wait mode when the WIT in- struction is executed. The internal clock stops at H level, but the oscillator does not stop. is re-supplied (wait mode release) when the microcomputer is reset or when it receives an interrupt. Instructions can be executed im- mediately because the oscillator is not stopped. The inter- rupt enable bit of the interrupt used to reset the wait mode must be set to 1 before executing the WIT instruction. Low power dissipation operation is also achieved when the Xiw clock is stopped and the internal clock is generated from the Xow clock (1204A max. at f( Xow) = 32kHz). Xin clock oscillation is stopped when the bit 6 of serial I/O mode register (address 00F6,,) is set and restarted when it is cleared. However, the wait time until the oscillation sta- bilizes must be generated with a program when restarting. An L level must be kept to the RESET pin until the oscillation stabilizes when resetting while the Xj clock is stopped. Figure 22 shows the transition of states for the system clock. MS50940-XXXSP Xin Xout Xcin Xcout 28 29 30 31 MQ Rf Rd 0 0 yon Joo 3c J Scour Fig.19 External ceramic resonator circuit MS50940-XXXSP Xin Xour Xen Xcour 284 29 30f 31 External OP" External Open oscillating oscillating circuit circuit Fig.20 External clock input circuit oe ReMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Xcin Xcout TMs pH 1/2 1/2 1/4 Timert b+ Timer2 Timer 1 count Internal system source selection TM2 System clock clock source stop bit selection SM, t SMe Internal clock SM; timing output STP instruction wiT R R |~ STP instruction Rr- . : instruction Interrupt control register (Address O0FE,,) Interrupt O disable flag | _ INT, interrupt enable INT, interrupt request Timer | interrupt enable Timer 1 interrupt request (or A-D} r- Timer 2 interrupt enable Timer 2 interrupt request Timer 3 interrupt enable (or serial 1/0) | Timer 3 interrupt request (or serial /O) INT, interrupt enable INT> interrupt request Fig.21 Block diagram of clock generating circuit 5-66 aie MTSuBSH ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RESET WIT instruction ___ STP inst 4MHz osciilation instruction 32kHz oscitlation 4MHz oscillation 4MHz oscillation STOP $=STOP (H") 32kHz oscillation 32kHz oscillation STOP Timer action =1MHz we $=STOP 38 Interrupt Interrupt (Note 1) External interrupt i Externat in : timer interrupt [ interrupt seriat |/O interr serial (/O interrupt L upt SM;=0 SM;=1 WIT instruction 4MHz oscillation < 32kHz oscillation =STOP Timer action (Note 3) STP instruction 4MHz oscillation a 32kHz oscillation =16kHz 4MH#z oscitlation STOP 32kHz oscillation STOP __ @=STOP Interrupt Interrupt (Note 1} SM,s=1 SMs=0 (Note 2) 4MHz STOP STP instruction 4MHz STOP 32kH2z oscillation 32kHz oscillation @ =16kHz 4MHz oscillation STOP =STOP Timer action (Note 3) 32kHz oscillation STOP =STOP Interrupt . Interrupt (Note 1) Note 1. At recovery from the STP instruction, wait time occurs automatically by connecting timer 1 and timer 2. This time is set by the program. 2. When SMe=1, and unsystem clock is operated, a programmed wait time may be necessary to allow the oscila- tor stabilize. 3. When connected the clock divided by four as the count source of timer, frequency of count source is 4kHz. Fig.22 Transition of states for the system clock oe ES 8MITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER <An example of flow for system> Power on reset Clock X and clock for clock function X oscillation . Internal system clock start (X -+1/4 ) Normal operation 4 Program start from RESET vector 5 Normal program +-Operation at 4 MHz 5 Internal clock source switching X( 4 MHz)-*XeiKk (32. 768kHz)(SM; : 0-1) Clock X halt (X_ in operation)(SMgz : 1) Interna! clock halt (WIT instruction) Operation on the Timer 3 (clock count) overflow clock function J only Internal clock operation start (WIT instruction) s Ciock processing routine + Operating at 32. 768kHz internal clock halt (WIT instruction) Interrupts from INT, timer 2, timer 3 or serial 1/O, INT2 (BRK instruction) Internal clock operation start (WIT instruction released) Program start from interrupt vector Clock X oscillation start (SM, : 0) Return from clock function [ Oscillation rise time routine (software) Operating at 32. 768kHz 4 Internal clock souc switching (Xe>X)(SM;: 170) Normal program | Operating at 4MHz STP instruction preparation (pushing registers) Timer \ Timer 2 interrupt disable, Timer 2 interrupt request bit reset (TMs = 0, IMs= 0, IM4= 0 ) R AM backu function Timer 1 count stop bit resetting (TMs = 0 ) Clock X and clock function X halt (STP instruction) RAM backup status Interrupts from INT, or serial 1/O, INT2 Clock X and clock for clock function X_ oscillation start Timer 2 overflow (X/16 or X-/8-+timer 1+timer 2) RAM return (Automatically connected by the hardware) from RAM internal system clock start (X/4 or X/2-+) backup function Program start from interrupt vector 5 Normal program Lo s 268 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PROGRAMING NOTES (1) The frequency ratio of the timer is 1/(n+1). (n=0~ 255) (2) Even though the BBC and BBS instructions are ex- ecuted after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. Also, at least one in- struction cycle must be used (such as NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) When the timer 1, timer 2, or timer 3 is input the clock except /4 or it divided by timer, read the contents of these timers either while the input of these timers are not changing or after counting of timers are stoped. (4) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as a NOP) is needed befoer the SEC, CLC, or CLD intructions are executed. (5) A NOP instruction must be used after the execution of a PLP instruction. Notes on serial I/O Set O in the serial !/O interrupt enable bit (bit 2 of address O0OFE,) before setting the serial |1/O mode. Insert at least one instruction and set 0 in the serial I/O interrupt request bit (bit 3 of address OOFE,,) after setting the serial |/O mode. Set 1 in the serial I/O interrupt enable bit after the operation described in @. The timer 1 and the timer 2 must be set the necessary value immediately before the execution of a STP in- struction. Notes. on A-D conversion Set 0 in the A-D interrupt enable bit (bit 6 of address OOFF,.) before setting A-D conversion. Insert at least one instruction and set 0 in the A-D in- terrupt request bit (bit 7 of address OOFF,) after set- ting the A-D conversion. Set 1 in the A-D ihterrupt enable bit after the opera- tion described in @. Set 0 in bit 3 of the A-D control register (address 00F3,,) before using a STP instruction. Notes on timer 4 and timer 5 using as watchdog timer Do not use these timers when using STP instruction or stopping or switching the clock. It does not operate collectly in some writing timing to timer 4 and timer 5. (10) The Vrer pin must be kept open or connected to Vsg at the low power dissipation mode. ees oe + Os DATA REQUIRED FOR MASK ORDERING Please send the following data for mask orders. (1) mask ROM confirmation form (2) mark specification form (3) ROM data secret eter etree EPROM 3 sets Write the following option on the mask ROM confirmation form Port P3 pull-up transistor bit Port P4 pull-up transistor bit ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions : Ratings Unit Voc Supply voltage : 0.3-~7 Vv Ve Puli-down input voltage i Voo38~Vec +0. 3 | vo Vv, Input voltage CNVss pi 0. 3~13 | _ Vv vi Input voltage Ro~Rs, Xin, Xciw, RESET With respect to Vss 0.3~7 Vv Vi Input voltage P39p~P37, P4o9~P4z, INo~INz, Vrer output transistors are at OFF state. : ~=0.3~Voot0.3 | Vv, Input voltage P2>~P27 Veco 38~Veco +0. 3 Vv Vo Output voltage P3y~P3;,P4~P47, Xcour, Xour, # ; -0.3~Veo +03 | Vv Vo Output voltage P0g~PO;, P1p~P17, P2p~P2; Vee 38~Vec +0. 3 V Pq Power dissipation Tg =25T 1000( Note 1) mw Topr Operating temperature 10~70 c Tstg Strage temperature 40~125 To Note 1. 600mW for QFP type. RECOMMEND OPERATING CONDITIONS =10~70C, unless otherwise noted) (Vec= 5 V110%, Ta Symbol Parameter ~ Limits Unit Min. Typ. Max. (Xin) =4MHz 4.5 5 5.5 Vee Supply volage (Xin) S1MHz 3 5 5.5 V Vp Puli-down supply voltage Veo 36 Voc Vv Vss Supply voltage 0 Vv Vin H" input voltage P3p~P37, P4g~ P47, INo~IN7,CNVss 0. 8Vec Voc Vv Vin H input voltage Ro~ Rg 0. 4Voc Voc Vv View H input voltage RESET, Xin, Xcin 0. 8Vcc Veo v Vie H" input voltage P29~ P27 0. 8Vec Vec Vv Vit L input voltage P3p~P37, P4g~P4z7, INo~IN7, CNVss 0 0. 2Vec Vv Vin L" input voltage Ro~Rs 0 0.12Vec Vv Vin L input voltage RESET 0 0.12Vec v Vin L input voltage Xi, Xcin 0 0. 16Vec v Vit L input voltage P29>~P27 Veco 36 0. 2Vce Vv longum) | H" sum output current PQp~ P07, Plo~P17, P29~P27 120 mA lon(sum) | H sum output current P3p~P37, P4o~P47 30 mA lotcsum) | L sum output current P3p~P37, P4o~ P47 60 mA lon(peak)| H peak output current POg~PO;, Plo~Pt7, P2o~P27 24 mA lonipeak)| H peak output current P39~P37, P4o~P47 10 mA lou(peak) | L peak output current P3o~P37, P4o~ P47 20 mA lon(avg) H average output current POg~ P07, Plo~P17, P2o~P2z 12 mA lontavg) | H" average output current P3g~P37, P4o~P4z a) mA loriave> L" average output current P39~P37, P4y~ P47 10 mA a Vec=5V 4.3 f(Xin) Clock oscillating frequency Voo=3V a MHz (Xin) Clock oscillating frequency Vcc=5V 500 kHz for clock function Voc=3V 300 Note 1. The maximum H input voltage for CNVsg is +12V. 2. The duty cycle for these oscillation frequency is 50%. 3. When the low speed mode is used, the clock input oscillation frequency for the timer must satisfy the following expression : (Kein) < f%qy/3 4. The avarage output current loucavg) and loiavg) are the average value during a 100ms cycle. 5. f(Xin~) must be less than 50kHz when the external clock is to be used. ELECTRICMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS (Vec=5V10%, Ves=0V, Ta=25C, 1(Xin)= 4MHz, unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. Vec=5V, lon= SmA 3 Vv H" output voltage P3g~P37, P4g~P4- Vv oH p ge PSo~ P37, Pao~ Par Voc=3V, low=1. 5mA 2 . Voo=5V, lon=2. SMA 3 Vv H output voltage Vv on P 9 Voo=3V, lon=0. 8mA 2 Vv H" output voltage P0y~P0;, Plo~Pt7, P2o~P2 Voo SV, low=12mA 3 Vv H" output voltage ~ PO?, ~P Az, ~ oH Pp ig 0 i 0 7 0 7 Vec=3V, fon=3mA 2 Veco=5V, lor=10mA 2 v L output voltage Pag~P3;, P4g~P4 Vv OL p ge P3o 7, Pag 7 Vooun3V, lo.=3mA 1 Voc=5V, loL=2.5mA 2 Vv L output voltage Vv ou 9 Vec=3V, lor =0. 8mA 1 Vv Vv Hyst is P3p/INTs, P3 Ants use as interrupt Vec=5V 0.3 1 Vv _ steresis a THT Nr ry area input Voo=3V 0.15 0.7 oe Vec=5V 0.5 0.7 V14Vr- | Hysteresis RESET Vv Vec=3V 0. 35 | use as CLK Veo=5V 0.3 1 Vr+V1 | Hysteresis P3e/CLK Vv input Voc=3V i 0.15 | 0.7 Vee-v Hysteresis X Vec=5V ; O01 | 0.5 Vv Vr steresis reer py " Voo=3V 0. 06 0.3 v v Hysteresis X Vec=5V 0.1 0.5 Vv Vr- steresi rere | iy on Voc=3V 0. 06 0.3 V.=0V without Voc=5V 5 pull-up Ty. Vec=3V 4 1 L input current P39~P37, P4g~P4- A ie P one ees Vi=OV, with Voc=5V 35 | 70 | 140,; pull-up Ty. Vec=3V 12 25 40 i L" input Jt INo~IN V;=0V Voor OV = A input curren ~ = IL P lo 7 1 Veo=3V 4 1 *L" input t RESET, Xin. Xciw, Ro~R vi=0V VooW 8V 8 A "L input curren! + AIns Rom = iL Pi IN: ACIN, Fig Fg | Voo=3V 4 rad \ L" input t P2p~P2 vie A L" input curren ~ u u P ~ Vi=Veo36V 30 fiw H input current P3p~P37, P49~P47 V,=5V, without pull-up transistor 5 HA fi H input current INo~IN7 V,=5V, not use as analog input 5 HA , reading operation V,=5V 100 he H input current P29>~P27 . uA normal operation V,=5V 5 lin H input current RESET, Xin, Xcin. Ro~ Aa V=5V 5 uA hin H input current Veer Vi=5V 5 mA lo. L output current PQp~PO7, Plop~P17, P2o~ P27 Ve=Voc36V, Vot=Vec 150 500 300 HA Open output ports, Xiw=4MHz, Voc=5V 3 6 Vp=Voc. input pott is Vss, at normal operation. Xin=IMHz, Voo3V 0.4 mA Open output ports, | X.=4MHz, Voc=5V 1 Vp=Vec, input port is Vss, at wait mode. Xin= 1MHz, Voc=3V 0.2 Open output ports, Pen ouput Ps Voc=5V 6o | 200 Vp=Voc. input port is Vg. at normal operation, stop 1 Supply current Voc=3V 25 ce pey Xiwand Xour. Xon=B2kH2, | Open output ports, Pen oupure Voo=5 40 Vp=Voc, input pottis Vss, A at wait mode, stop # Voec=3V 15 Xin and Xgur, Xcin=32kHz. Vec=5V Q.1 Ta=e ices Veco=3V 0. 06 Stop all oscillation. Voc=5V 1 10 Tag=70T Voc=3V 0.6 lace Supply current for A-O at A-D converting time 2 4 mA Vram RAM retension voltage Oscillation stops 2 5.5 Vv Pe ES" znMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER cr xX; Veo aa i Xin RESET CoESR, Output pins open {-o Xout oe P X, =4MHz Ceramic resonator ; = Quartz crystal Cs x, Input pins X2 32. 768kKHz fesonator IH Xoin Cy =C. =150pF CER. Pp R, =IMQ jp bw Xcout C, =100F Ry CNVsg. 3 = Up C, =30pF Vss R, =10MQ 77 Rs =100k2 Fig.23 Test circuit for measuring supply current A-D CONVERTER CHARACTERISTICS (Vcc=5v, Vss=0V, Ta=25, f(Xiy)=4MHz, unless otherwise noted) Symbol Parameter Test conditions Limits Unit Min. Typ. Max. _- Resolution . 8 bits - Absolute accuracy Veco=AVec=Vaer=5. 12V +3 LSB Riapoer | Ladder resistor value 1 kQ tconv Conversion time High-speed * #=1MHz 72 us Low-speed : =1MHz 288 Vrer Reference input voltage Veco Vv Via Analog input voltage . Vrer Vv 2-72 MITSUBISHI ELECTRICMITSUBISHI MICROCOMPUTERS MS50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Single-chip mode (Vcc=5V+10%, Vss=0V, Ta=25, 1(Xw)= 4MHz unless other wise noted) Symbol Parameter : Test conditions Limits Unit Min. Typ. Max. tsu(p204) Port P2 input setup time 270 ns tsu(eap) | Port P3 input setup time 270 ns tsu(pan) | Port P4 input setup time 270 ns tsu(ap#) Port R input setup time 270 ns tsucinn#) Port IN input setup time 270 ns thi s_pep) Port P2 input hold time 20 ns thi g_pap) Port P3 input hold time 20 ns thi ap4p) Port P4 input hold time 20 ns thcs_erRb) Port R input hold time 20 ns th (#-IND) Port IN input hold time 20 ns teouy) External clock input cycle time (Xi) 230 ns two) External clock input pulse width (Xin) 75 ns tooxeiny External clock input cycle time (Xow) 2 ms twoxon) External clock input pulse width (Xow) 1 ms tr External clock rising edge time 25 ns tf External clock falling edge time ; 25 ns Memory expanding mode and eva-chip mode , (Vec=5V410%, Ves= OV, Ta=25C, f(Xin) = 4 MHz unless otherwise noted) Limits Symbol Parameter Test conditions " Unit Min. Typ. Max. tsu(p20) | Port P2 input setup time 270 ns thc s_r2p) Port P2 input hold time 20 ns Microprocessor mode (vcc=5V+10%, Vss=0V, Ta=25C, t(Xin)= 4 MHz unless otherwise noted) Limits Symbol Parameter Test conditions ~ Unit Min. Typ. Max. tsu(p2p) | Port P2 input setup time 270 ns thi sp2p) Port P2 input hold time 20 ns MITSUBISHI 2-73 ELECTRICMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,M50941-XXXSP/FP MS0945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS Single-chip mode (Vcc=5v+10%, Vss=0V, Ta=25C, f(Xw)= 4 MHz unless otherwise noted) Symbol Parameter Test conditions Limits Unit Min. Typ. Max tdi gPoa) Port PO data output delay time 230 ns td(gPia) Port P1 data output delay time Fig. 25 230 ns tdi gp2a) Port P2 data output delay time 230 ns td(P3a) Port P3 data output delay time | i 230 ns td(4Pp4a) Port P4 data output delay time Fig. 24 | 230 ns Memory expanding mode and eva-chip mode (Voc=5V410%, Ves= OV, Ta=25C, f(Xin) = 4 MHz unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. td(epoa) Port PO address output delay time 250 ns tdcgpoar) | Port PO address output delay time 250 ns td(gpoa) Port PG data output delay time 200 ns tdceroar) | Port PO data output delay time 200 - ns tdipi1a) Port P1 address output delay time Fig. 25 250 ns td(gpiar) | Port P1 address output delay time 250 ns tdigeia) Port P1 data output delay time 200 ns tdigriar) | Port P1 data output delay time 200 ns tdi p2a) Port P2 data output delay time 300 ns td(p2ar) | Port P2 data output delay time 300 ns tdisr/w) R/W signal output delay time 250 ns tdi(gr/wr) | R/W signal output delay time 250 ns tdcae4pa) _| Port P4o data output delay time 200 ns tdcgpagar) | Port P4p data output delay time Fig. 24 200 ns td(gsync) | SYNC signal output delay time 250 ns tdcgsyncr) | SYNC signal output delay time 250 ns tdcgpa,q)__| Port P4; data output delay time 200 ns | tdigpa,ar) | Port P4: data output delay time 200 ns Microprocessor MOdEe (Voc=5V+10%, Vss= OV, Ta=25C, f(Xinw)= 4 MHz unless otherwise noted) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. tdi gpoa) Port PO address output delay time 250 ns td(ePpia) Port P1 address output delay time Fig. 25 250 ns td(ep2a) Port P2 data output delay time 300 ns tdigp2ar) | Port P2 data output delay time 300 ns tdigrw) R/W signat output delay time Fig, 24 250 ns tdigsync) | SYNC signal output delay time 250 ns Vee ka P3 Pt P4 P2 I 100pF yor 1k 0 t 100pF lore Fig.24 Test circuit of ports P3 and P4 Fig.25 P1, and P2 Test circuit of ports PO, owaeMITSUBISHI MICROCOMPUTERS M50940-X XXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING DIAGRAMS In single-chip mode | , _Y a, td (~poa! Port PO output | td ce-pra) Port P1 output td (e-p2a) Port P2 output t Su (P2D) Port P2 input __ P th (s-eep: td i-P3q) Port P3 output tsu iesp 9) , th (s-p30) Port P3 input | td (-Psa} Port P4 output tsu (pa0: y_ Port P4 input /S t . th .6-pap SU: AD- Port R input S| _N th ee tsu (inD-) h te-ap _/ Port IN input th .@-inD: tery) OF toixcin? twin? OF twixein) | (Xi) or _ (Xen) tt MITSUBISHIMITSUBISHI MICROCOMPUTERS MS0940-XXXSP/FP,MS50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER in memory expanding mode and eva-chip mode *_Y/ ee td ca-Poa) td (-PoarF) afd (4POQF) Port PO output _ td (9-Poa) td (eP1a) td Ce-PiAF) hattg (@-P10F) Port P1 output td (pia: td (gp2q) td (e-pear) Port P2 output tsu (p204) o Port P2 input / th (s-p20) td te-arw) td Co-nywe) td (-Pagar) Port P4, output (R/W) td (Papa) k= td .e-sync) td (e-syncF) peat td (opa,aF) Port P4, output (SYNC) ! x eS q td (Pa,a) 2-76 MITSUBISHIMITSUBISHI MICROCOMPUTERS M50940-XXXSP/FP,M50941-XXXSP/FP M50945-XXXSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER In microprocessor mode / \ td (-Poa) Port PO output tac> td (pt) Port P1 output td (-P2a) td (ep2aF: Port P2 output x Floating _ tsu (e20- 4) Port P2 input th (e-ez0! td (e-R/wW) Port P4p output (R/W) x td (s-sync) Port P4, output (SYNC) MITSUBISHI 2-77