GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Revision Date: January 2001 Document No. 521 - 96 - 05
DATA SHEET
GS9032
FEATURES
• SMPTE 259M and 540Mb/s compliant
• serializes 8-bit or 10-bit data
• autostandard, adjustment free operation
• minimal external components (no loop filter
components required)
• isolated, quad output, adjustable cable driver
• power saving secondary cable driver disable
• 3.3V and 5.0V CMOS/TTL compatible inputs
• lock detect indication
• SMPTE scramble and NRZI coding bypass option
• EDH support with GS900 1, GS90 21 or EDH FPG A co de
APPLICATION
SMPTE 259M and 540Mb/s parallel to serial interfaces for
video cameras, VTRs, and signal generators; generic
parallel to serial conversion.
DESCRIPTION
The GS9032 encodes and serializes SMPTE 125M and
244M bit parallel digital video signals, and other 8-bit or
10-bit parallel formats. This device performs sync
detection, parallel to serial conversion, data scrambling
(using the X9 + X4 + 1 algorithm), 10x parallel clock
multiplication and conversion of NRZ to NRZI serial data.
The GS9032 features auto standard and adjustment free
operation for data rates to 540Mb/s with a single VCO
resistor. Other features include a lock detect output, NRZI
encoding, SMPTE scrambler bypass, a sync detect disable,
and an isolated quad output cable driver suitable for driving
75Ω loads. The complementary cable driving output swings
can be adjusted independently or the secondary differential
cable driver can be powered down.
The GS9032 requires a single +5 volt or -5 volt supply and
typically consumes 675mW of power while driving four 75Ω
loads.
BLOCK DIAGRAM
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE
GS9032 - CVM 44 pin TQFP 0°C to 70°C
GS9032 - CTM 44 pin TQFP Tape 0°C to 70°C
AUTO/MANUAL SELECT
(AUTO/MAN)
LOCK
DETECT
(LOCK DET)
SDO1
ENABLE
SERIAL
DIGITAL
OUTPUTS
PARALLEL CLOCK
INPUT (PCLKIN)
PLOAD
SCLK
SCLK/10
LOOP BANDWIDTH
CONTROL (LBWC)
RVCO+ RVCO-
DATA RATE SELECT
SS[2:0]
MUTE
RESET
RESET
SYNC DETECT DISABLE (SYNC DIS)
BYPASS
BYPASS
PARALLEL
to SERIAL
CONVERTER
&
NRZ to NRZI
DATA
IN
(PD0-PD9)
10
3
10
8
INPUT
LATCH
2
10
SYNC
DETECT
SMPTE
SCRAMBLER
PLL
SDO0
SDO0
SDO1
SDO1
GENLINX ™II GS9032
Digital Video Serializer
GENNUM CORPORATION 521 - 96 - 05
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GS9032
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE
Supply Voltage (VS = VCC-VEE)5.5V
Input Voltage Range (any input) VEE<VIN<VCC
DC Input Current (any one input) 5mA
Power Dissipation (VCC = 5.25V) 1200mW
θj-a 42.5°C/W
θj-c 6.4°C/W
Maximum Die Temperature 125°C
Operating Temperature Range 0°C ≤ TA ≤ 70°C
Storage Temperature Range -65°C ≤ TS ≤ 150°C
Lead Temperature (soldering, 10 sec) 260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA =0°C to 70°C unless otherwise specified.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES TEST
LEVEL
Positive Supply Voltage VCC Operating Range 4.75 5.00 5.25 V 1
Power (System Power) P VCC = 5.0V, T = 25°C (4 outputs) - 675 - mW 5
Supply Current ΙCC VCC = 5.25V (4 outputs) - - 180 mA 1
VCC = 5.0V, T = 25°C (4 outputs) - 135 - 1
VCC = 5.25V (2 outputs) - - 160 1
VCC = 5.0V, T = 25°C (2 outputs) - 110 - 7
Data & Clock Inputs
(PD[9:0] PCLKIN)
SYNC DIS
VIH Logic Input High (wrt VEE)2.4--V 1
VIL Logic Input Low (wrt VEE)--0.8V
ΙLInput Current - - 8.0 µA
Logic Input Levels
(Auto/Man, SS[2:0]
Bypass, RESET)
VIH Logic Input High (wrt to VEE)2.4--V 1
VIL Logic Input Low (wrt to VEE)--0.8V
ΙLInput Current - - 5.0 µA
Lock Detect Output VOL Sinking 500µA - - 0.4 V 1
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
GENNUM CORPORATION 521 - 96 - 05
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GS9032
AC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA =0°C to 70°C unless otherwise specified.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES TEST
LEVEL
Serial Data Bit Rate BRSDO RVCO = 374Ω143 - 540 Mb/s SMPTE
259M
1
Serial Data Outputs Signal
Swing
VSDO RLOAD = 37.5Ω, RSET = 54.9Ω740 800 860 mVp-p 1
Min. Swing (adjusted) VSDOMIN RLOAD = 37.5Ω, RSET = 73.2Ω- 600 - mVp-p 7
Max. Swing (adjusted) VSDOMAX RLOAD = 37.5Ω, RSET = 43.2Ω-1000-mVp-p 1
SD Rise/Fall Times tr, tf20% - 80% 400 - 700 ps 7
SD Overshoot/Undershoot - - 7 % 1 7
Output Return Loss ORL at 540MHz 15 - - dB 1 7
Lock Time tLOCK Worst case - - 5 ms 6
Min. Loop Bandwidth BWMIN 270Mb/s
LBWC = Grounded : BWMIN
- 220 - kHz 7
Typical Loop Bandwidth BWTYP 270Mb/s
LBWC = Floating : BWMIN
- 500 - kHz 7
Max. Loop Bandwidth BWMAX 270Mb/s
LBWC = VCC : 10 BWMIN
-1.7-MHz 7
Intrinsic Jitter (6σ) 143Mb/s LBWC = floating - 0.07 - UI 1
177Mb/s LBWC = VCC -0.07-
270Mb/s - 0.08 -
360Mb/s - 0.09 -
540Mb/s - 0.11 -
Data & Clock Inputs
(PD[9:0] PCLKIN)
tSU Setup Time at 25°C2.5--ns 1
tHHold Time at 25°C2.0--ns 1
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for
supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
NOTES
1. Depends on PCB layout.
10
GENNUM CORPORATION 521 - 96 - 05
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GS9032
PIN CONNECTIONS
GS9032
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
R
VCO+
LF+
VEE
R
VCO-
LF-
VCC1
LBWC
NC
SYNC DIS
VEE
VEE1
33
32
31
30
29
28
27
26
25
24
23
AUTO/MAN
BYPASS
RSET1
VEE
SDO1
SDO1
VEE
SDO0
SDO0
VEE
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLKIN
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 21 22
VCC2
V
EE
2
COSC
RSET0
SS1
SS2
SDO1 ENABLE
LOCK DET
VEE3
SSO
VCC3
RESET
PIN DESCRIPTIONS
NUMBER SYMBOL TYPE DESCRIPTION
1-10 PD9 - PD0 I CMOS or TTL compatible parallel data inputs. PD0 is the LSB and PD9 is the MSB.
11 PCLKIN I CMOS or TTL compatible parallel clock input.
12 VEE3 - Most negative power supply connection for parallel data and clock inputs.
13 VCC3 - Most positive power supply connection for parallel data and clock inputs.
14 COSC I Master Timer Capacitor. A capacitor should be added to decrease the system clock
frequency when an external capacitor is used across LF+ and LF- (NC if not used).
15, 16, 21 SS2, SS1, SS0 I Data rate selection when in manual mode. These pins are not used in auto mode.
17 VCC2 - Most positive power supply connection for internal logic and digital circuits.
18 VEE2 - Most negative power supply connection for internal logic and digital circuits.
19 SDO1 ENABLE I Enable pin for the secondary cable driver (SDO1 and SDO1). Connect to most negative
power supply to enable. Leave open to disable (do NOT connect to VCC).
20 LOCK DET O TTL level which is high when the internal PLL is locked.
22 RSET0 I External resistor used to set the data output amplitude for SDO0 and SDO0.
23, 26, 29 VEE - Most negative power supply connection for shielding (not connected).
24, 25 SDO0, SDO0 O Primary, current mode, 75Ω cable driving output (inverse and true)
27, 28 SDO1, SDO1 O Secondary, current mode, 75Ω cable driving output (inverse and true)
30 RSET1 I External resistor used to set the data output amplitude for SDO1 and SDO1.
GENNUM CORPORATION 521 - 96 - 05
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GS9032
TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25°C unless otherwise shown. Guard band tested to 70°C only.)
Fig. 1 Rise/Fall Times vs. Temperature Fig. 2 Supply Current vs. Temperature (SDO0 & SDO1 ON)
31 BYPASS I When high, the SMPTE Scrambler and NRZ encoder are bypassed.
32 AUTO/MAN I Autostandard or manual mode selectable operation.
33 RESET I Resets the scrambler when asserted.
34 VCC1 - Most positive power supply connection for analog circuits.
35 VEE1 - Most negative power supply connection for analog circuits.
36, 38 RVCO+, RVCO- I Differential VCO current setting resistor that sets the VCO frequency.
37 NC I No Connect.
39, 43 VEE - Most negative power supply connection (substrate).
40 LBWC I TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest
jitter. If the pin is set to ground the loop bandwidth is BWMIN. If the pin is left floating, the
loop bandwidth is approximately 3 BWMIN, if the pin is tied to VCC the loop bandwidth is
approximately10 BWMIN
41, 42 LF+, LF- I Differential loop filter pins to optimize loop transfer performance at low loop bandwidths
(NC if not used).
44 SYNC DIS I Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation
by mapping 000-003 to 000 and 3FC-3FF to 3FF.
PIN DESCRIPTIONS
NUMBER SYMBOL TYPE DESCRIPTION
5.25 FALL
4.75 RISE
5.0 RISE
5.0 FALL
5.25 RISE
4.75 FALL
020406080
500
490
480
470
460
450
440
430
420
RISE / FALL TIME (ps)
TEMPERATURE (˚C)
4.75
5.0
5.25
020406080
155
150
145
140
135
130
125
CURRENT (mA)
TEMPERATURE (˚C)
GENNUM CORPORATION 521 - 96 - 05
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GS9032
Fig. 3a O utput S wing v s. Temperature (1000 mV)
Fig. 3b Output Swing vs. Temperature (800mV)
Fig. 4 Wavefor ms
Fig. 5 T iming Diagram
Fig. 6a Loop Filter Voltage v s. Temperature (360 Mode)
Fig. 6b Loop Filter Voltage v s. Temperature (540 Mode)
4.75
5.0
5.25
020406080
1.01
1.005
1.000
0.995
0.99
OUTPUT SWING (V)
TEMPERATURE (˚C)
4.75
5.0
5.25
020406080
0.8075
0.805
0.8025
0.800
0.7975
0.795
0.7925
OUTPUT SWING (V)
TEMPERATURE (˚C)
t
SU
t
HOLD
t
CLKL
= t
CLKH
PARALLEL
CLOCK
PLCK
50%
PARALLEL
DATA
PDn
E
A
V
S
A
V
4ƒsc
DATA
STREAM ACTIVE VIDEO
& H BLANKING
T
R
S
ACTIVE
VIDEO
T
R
S
T
R
S
ACTIVE VIDEO
& H BLANKING
4:2:2
DATA
STREAM
E
A
V
S
A
V
H
BLNK H
BLNK
SYNC
DETECT
SYNC
DETECT
SYNC
DETECT
XXX 3FF 000 000 XXX ••• ••• XXX 3FF 000 000 XXX •••
PCLK IN
PDN
020406080
160
140
120
100
80
60
40
20
0
LF+ — LF- (mV)
TEMPERATURE (˚C)
020406080
40
20
0
-20
-40
-60
LF+ — LF- (mV)
TEMPERATURE (˚C)
GENNUM CORPORATION 521 - 96 - 05
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GS9032
Fig. 7 Loop Bandwidth vs. Data R ate
Fig. 8 O utp ut Jitter v s. LBWC
Fig. 9 Output Jitter vs. Data Rate
(Optimum LBW Setting)
Fig. 10 Output Eye Diagram (270Mb/s)
Fig. 11 Output Eye Diagram (540Mb/s)
LBWC to V
CC
LBWC FLOATING
LBWC GROUNDED
0 143 177 270 360 540
3500
3000
2500
2000
1500
1000
500
0
LOOP BANDWIDTH (kHz)
DATA RATE (Mb/s)
GROUNDED FLOATING V
CC
600
500
400
300
200
100
0
JITTER p-p (ps)
LOOP BANDWIDTH CONTROL (LBWC)
For a data rate of 270Mb/s
0 100 200 300 400 500 600
500
400
300
200
100
0
JITTER p-p (ps)
DATA RATE (Mb/s)
GENNUM CORPORATION 521 - 96 - 05
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GS9032
DETAILED DESCRIPTION
The GS9032 Serializer is a bipolar integrated circuit used to
convert parallel data into a serial format according to the
SMPTE 259M standard. The device encodes both eight and
ten bit TTL-compatible parallel signals producing serial
data rates up to 540Mb/s. It operates from a single five volt
supply and is packaged in a 44 pin TQFP.
Functional blocks within the device include the input
latches, sync detector, parallel to serial converter, SMPTE
scrambler, NRZ to NRZI converter, internal cable driver, PLL
for 10x parallel clock multiplication and lock detect. The
parallel data (PD0-PD9) and parallel clock (PCLKIN) are
applied via pins 1 through 11 respectively.
1. SYNC DETECTOR
The sync detector makes the system compatible with eight
or ten bit data. It looks for the reserved words 000-003 and
3FC-3FF in ten bit hexadecimal, or 00 and FF in eight bit
hexadecimal, used in the TRS-ID sync word. When the
occurrence of either all zeros or all ones at inputs PD2-PD9
is detected, the lower two bits PD0 and PD1 are forced to
zeros or ones respectively. For non-SMPTE standard
parallel data, the sync detector can be disabled through a
logic input, Sync Detect Disable (44).
2. SCRAMBLER
The scrambler is a linear feedback shift register used to
pseudo-randomize the incoming serial data according to
the fixed polynomial (X9+X4+1). This minimizes the DC
component in the output serial data stream. The NRZ to
NRZI converter uses another polynomial (X+1) to convert a
long sequence of ones to a series of transitions, minimizing
polarity effects. These functions can be disabled by setting
the BYPASS pin (31) high.
3. PHASE LO CK ED L OO P
The PLL performs parallel clock multiplication and provides
the timing signal for the serializer. It is composed of a
phase/frequency detector (with no dead zone), charge
pump, VCO, a divide-by-ten counter, and a divide-by-two
counter.
The phase/frequency detector allows a wider capture range
and faster lock time than with a phase discriminator alone.
The discrimination of frequency eliminates harmonic
locking. With this type of discriminator, the PLL can be over-
damped for good stability without sacrificing lock time.
The charge pump delivers a 'charge packet' to the loop
filter which is proportional to the system phase error.
Internal voltage clamps are used to constrain the loop filter
voltage between approximately 1.8 and 3.4 volts.
The VCO is a differential low phase noise, factory trimmed
design that provides increased immunity to PBC noise and
precise control of the VCO centre frequency. The VCO can
operate in excess of 800MHz and has a pull range of ±15%
about the centre frequency. The single external resistor,
RVCO, sets the VCO frequency
(see Figure 12)
.
4. VC O CENTRE FREQUENCY SELECTION
For a given RVCO value, the VCO can oscillate at one of two
frequencies. When SS0=logic 1, the VCO centre frequency
corresponds to the ƒL curve. For SS0=logic 0, the VCO
centre frequency corresponds to the ƒH curve (ƒH is
approximately 1.5 x ƒL).
Fig. 12
The recommended RVCO value for auto rate SMPTE 259M
applications is 374Ω (
see the Typical Application Circuit
).
This value prevents false standards indication in auto mode.
For non-SMPTE applications (where data rates are x2
harmonically related) use Figure 12 to determine the RVCO
values.
The VCO and an internal divider generate the PLL clock.
Divider moduli of 1, 2, and 4 allow the PLL to lock to data
rates from 143Mb/s to 540Mb/s. The divider modulus is set
by the AUTO/MAN, and SS[2:0] pins (
see Truth Table for
further details
). In addition, a manually selectable modulus
8 divider allows operation at data rates as low as 18Mb/s
when RVCO is increased to 1kΩ.
When the loop is not locked, the lock detect circuit mutes
the serial data outputs. When the loop is locked, the Lock
Detect output is available from pin 20 and is HIGH.
The true and complement serial data, SDO and SDO, are
available from pins 24, 25, 27 and 28. These outputs drive
four 75Ω co-axial cables with SMPTE level serial digital
video signals. To disable the outputs from pins 27 and 28
(SDO1, SDO1), remove the resistor connected to the RSET1
pin (30) and float the SDO1 ENABLE pin (19).
NOTE: Do NOT connect pin 19 to VCC.
RSET calculation:
where RLOAD = RPULL-UP || Z
0
100
200
300
400
500
600
700
800
0 200 400 600 800 1000 1200 1400 1600 1800
VCO FREQUENCY (MHz)
R
VCO
(Ω)
ƒ
H
ƒ
L
SSO=1
SSO=0
RSET
1.154 RLOAD
×
VSDO
---------------------------------------=
GENNUM CORPORATION 521 - 96 - 05
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GS9032
TYPICAL APPLICATION CIRCUIT (SMPTE Auto Mode)
TRUTH TABLE (M anual Mode)
DATA RAT E
(Mb/s) SS2 SS1 SS0 DIVIDER
MODULI VCO
FREQUENCY
143 0 0 0 4 ƒH
177 0 0 1 2 ƒL
270 0 1 0 2 ƒH
360 0 1 1 1 ƒL
540 1 0 0 1 ƒH
451018ƒL
681108ƒH
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
GS9032
VEE3
VCC3
NC (COSC)
SS2
SS1
VCC2
VEE2
SDO1_EN
LOCK
SS0
RSET0
SYNC_DIS
VEE
LF-
LF+
LBWC
VEE
RVCO
NC
RVCO+
VEE1
VCC1
RESET
AUTO/MAN
BYPASS_EN
RSET1
VEE
SDO1
SDO1
VEE
SDO0
SDO0
VEE
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PCLKIN
VCC
J2
J1
J3
J4
VCC
VCC
VCC
SS0*
SS1*
SS2*
VCC
VCC
374
100n
54.9
75
75
L
R
L
R
L
R
L
R
1µ
1µ
1µ
1µ
75
75
100n
54.9
220
J1
LBWC
100n
100n
10k
0
* See Truth Table for settings. NC in auto mode.
PARALLEL
CLOCK
INPUT
PARALLEL
DATA
INPUTS
L = 8.2nH
R = 75Ω
LOCK
100n
All resistors on ohms,
all capacitors in farads,
unless otherwise stated.
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 VCC
RESET
VCC
521 - 96 - 05
10
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright May 1998 Gennum Corporation. All rights reserved. Printed in Canada.
GS9032
PACKAGE DIMENSIONS
10.00
12.00
10.00
0.80 0.30
12.00
0.20 MAX
RADIUS
0.08 MIN.
RADIUS
0.60
±0.15
0.20 MIN
12˚ TYP
12˚ TYP
1.00
0.10
1.10
0.127
7˚ MAX
0˚ MIN
0 MIN
PIN 1
0.20 MIN
All dimensions in millimetres
44 pin TQFP
REVISION NOTES:
Updated the electrical characteristics tables.
For latest product information, visit www.gennum.com.
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGE S OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
