AP1280AGN3-HF - Advanced Power Electronics Corp. USA

Advanced Power

Electronics Corp. AP1280AGN

2A SINK/SOURCE BUS TERMINATION REGULATOR

FEATURES DESCRIPTIOON

Ideal for DDR-I, DDR-II and DDR-III VTT Applications

Sink and Source up to 2Amp

Integrated Power MOSFETs

Generates Termination Voltage for SSTL_2, SSTL_18,

HSTL, SCSI-2 and SCSI-3 Interfaces.

High Accuracy Output Voltage at Full-Load

Output Adjustment by Two External Resistors

Built-in Soft-start Function

Shutdown for Suspend to RAM (STR) Functionality

with High-Impedance Output

Current Limiting Protection

On-Chip Thermal Protection

Available in DFN 3x3-8L Packages

VIN and VCNTL Under Voltage Protection

RoHS Compliant and 100% Lead (Pb)-Free

APPLICATION

Desktop PCs, Notebooks, and Workstations

Graphics Card Memory Termination

Set Top Boxes, Digital TVs, Printers

Embedded Systems

Active Termination Buses

DDR-I, DDR-II and DDR-III Memory Systems

Data and specifications subject to change without notice

201205172FC

TYPICAL APPLICATION

The AP1280AGN3 is a simple, cost-effective and

high-speed linear regulator designed to generate

termination voltage in double data rate (DDR) memory

system to comply with the JEDEC SSTL_2 and

SSTL_18 or other specific interfaces such as HSTL,

SCSI-2 and SCSI-3 etc. devices requirements. The

regulator is capable of actively sinking or sourcing up to

2A while regulating an output voltage to within 40mV.

The output termination voltage cab be tightly regulated

to track 1/2VDDQ by two external voltage divider resistors

or the desired output voltage can be pro-grammed by

externally forcing the REFEN pin voltage.

The AP1280AGN3 also incorporates a high-speed

differential amplifier to provide ultra-fast response in

line/load transient. Other features include extremely low

initial offset voltage, excellent load regulation, current

limiting in bi-directions and on-chip thermal shut-down

protection.Built-in softstart function avoids a

misoperation by inrush current.

The AP1280AGN3 are available in the DFN 3x3-8L

surface mount packages.

VIN

Shutdown

Enable

VCNTL

VOUT

VIN

REFEN

VCNTL

VOUT

GND

R2 CSS

CIN CCNTL

COUT RDUMMY

RTT

AP1280AGN3

R1 = R2 = 100KΩ, RTT = 50Ω/ 33Ω/ 25Ω

COUT = 10uF ( + 100 uF under the worst case testing condition )

CSS = 1uF , CIN = 470uF (Low ESR) , CCNTL = 47uF

Advanced Power

Electronics Corp. AP1280AGN

ABSOLUTE MAXIMUM RATINGS

(Note1)

Input Voltage (VIN) -----------------------------------------

CNTL Pin Voltage (VCNTL) -------------------------------

Power Dissipation (PD) -----------------------------------

Internally Limited

Storage Temperature Range (TST) --------------------

-65 to +150°C

Lead Temperature (Soldering, 10sec.) --------------- 260°C

40°C/W

Note1 : Exceeding the absolute maximum rating may damage the device.

OPERATING RATING(Note2)

Input Voltage (VIN) -----------------------------------------

2.5V to 1.5V +3%

CNTL Pin Voltage (VCNTL) -------------------------------

5.5V or 3.3V +5%

Junction Temperature Range (TJ) --------------------- -40 to +125°C

Ambient Temperature Range (TA) --------------------- -40 to +85°C

Note2 : The device is not guaranteed to function outside its operating conditions.

ORDERING / PACKAGE INFORMATION

(VIN=1.8V/1.5V, VCNTL=5V, VREFEN=0.9V/0.75V, COUT=10uF(Ceramic), T

=25oC, unless otherwise specified)

Parameter SYM TEST CONDITION MIN TYP MAX UNITS

VCNTL Operation Current ICNTL IOUT = 0A - 1 2.5 mA

Standby Current ISTBY VREFEN= 0V (Shutdown) - 25

VIN Shutdown Current IVIN VREFEN= 0V (Shutdown) - - 5uA

VCNTL UVP Rising Threshold VCOP VCNTL Rising 2.4 2.55 2.7 V

VCNTL UVP Hysteresis VCHYS -0.35 -V

VIN UVP Rising Threshold VIOP VIOP Rising 0.8 0.95 1.1 V

VIN UVP Hysteresis VIHYS -0.15 -V

IOUT = 10mA -13 - 13

IOUT = -10mA -13 - 13

IOUT = 10mA ~ 2A -13 - 13

IOUT = -10mA ~ -2A -13 - 13

ELECTRICAL SPECIFICATIONS

Input

Thermal Resistance from Junction to Case (Rthjc)

Output (DDR / DDRII / DDRIII)

Load Regulation(Note4) ΔVLoad

UVP Function

Output Offset Voltage(Note3) ΔVOS

Rth

a = 150oC/W

AP1280 AX-HF

Package Type

Halogen-Free

GN3 : DFN 3x3-8L

( Top View )

DFN 3x3-8L

GND

VIN 1

GND

REFEN

VOUT NC

VCNTL

Advanced Power

Electronics Corp. AP1280AGN

Parameter SYM TEST CONDITION MIN TYP MAX UNITS

Current Limit ILIM 2.2 - - A

Thermal Shutdown Temperature TSD 3.3V < VCNTL < 5V - 150 -

Thermal Shutdown Hysteresis ΔTSD 3.3V < VCNTL < 5V - 20 -

REFEN Threshold VEN 0.15 - 0.4 V

Soft-Start Interval TSS ∆VOUT=1V - 0.8 - ms

Note3. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.

Note4. Regulation is measured at constant junction temperature by using a 1ms(on) / 9ms(off) current pulse. Devices are tested for load regulation

in the load range from 10mA to 2A for source and -10mA to -2A for sink capability.

PIN DESCRIPTIONS

PIN SYMBOL PIN DESCRIPTION

VIN Power Input Voltage.

GND Ground Pin

VOUT Output Voltage

VCNTL Gate Drive Voltage

REFEN Reference Voltage Input and Chip Enable

BLOCK DIAGRAM

ELECTRICAL SPECIFICATIONS (CONTINUED

)

ENABLE and Soft-Start

Protection

VCNTL

ENABLE

FUNCTION

Soft-Start

Function

GATE

CONTROL

LOGIC

OCP

Function

UVP

Function

OTP

Function

REFEN

VIN

VOUT

GND

ERROR

AMPLIFIER

Advanced Power

Electronics Corp. AP1280AGN3

APPLICATION INFORMATIO

Input Capacitor and Layout Consideration

Consideration while designs the resistance of voltage divider

Thermal Consideration

Make sure the sinking current capability of pull-down NMOS if the lower resistance was

chosen so that the voltage on VREFEN is below 0.15V. In addition, the capacitor and voltage divide

form the lowpass filter. There are two reasons doing this design; one is for output voltage soft-start

while another is for noise immunity.

AP1280AGN3 regulators have internal thermal limiting circuitry designed to protect the device

during overload conditions.For continued operation, do not exceed maximum operation junction

temperature 125oC. The power dissipation definition in device is:

P D = (VIN - VOUT) x IOUT + VIN x IQ

The maximum power dissipation depends on the thermal resistance of IC package, PCB

layout, the rate of surroundings airflow and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by following formula:

P D(MAX) = ( TJ(MAX) -TA ) / Rthja

Where TJ(MAX) is the maximum operation junction temperature 125oC, TAis the ambient

temperature and the Rthja is the junction to ambient thermal resistance. The junction to ambient

thermal resistance (Rthja is layout dependent) for DFN 3x3-8L is 150oC/W on standard JEDEC 51-7

(4 layers, 2S2P) thermal test board. The maximum power dissipation at TA=25

oC can be

calculated by following formula:

P D(MAX) = (125oC - 25oC) / 150oC/W = 0.66W

The thermal resistance Rthja of DFN 3x3-8L is determined by the package design and the PCB

design. However, the package design has been decided. If possible, it's useful to increase thermal

performance by the PCB design. The thermal resistance can be decreased by adding copper unde

the expose pad of DFN 3x3-8L package. We have to consider the copper couldn't stretch infinitely

and avoid the tin overflow.

Place the input bypass capacitor as close as possible to the AP1280AGN3. A low ESR

capacitor larger than 470uF is recommended for the input capacitor. Use short and wide traces to

minimize parasitic resistance and inductance.

Inappropriate layout may result in large parasitic inductance and cause undesired oscillation

between AP1280AGN3 and the preceding powe converter.

Advanced Power

Electronics Corp. AP1280AGN3

MARKING INFORMATION

DFN 3x3-8L

1280A

YWWSSS

Part Number

Date Code (YWWS)

Y：Last Digit Of The Year

WW：Week

SSS：Sequence