LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 LM4934 BoomerTM Audio Power Amplifier Series 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and Mono Line Level Outputs Check for Samples: LM4934 FEATURES DESCRIPTION * * * * * * The LM4934 is an integrated audio sub-system designed for stereo cell phone applications. Operating on a 3.3V supply, it combines a stereo speaker amplifier delivering 520mW per channel into an 8 load, a stereo headphone amplifier delivering 36mW per channel into a 32 load, a mono earpiece amplifier delivering 55mW into a 32 load, and a line output for an external powered handsfree speaker. It integrates the audio amplifiers, volume control, mixer, power management control, and Texas Instruments 3D enhancement all into a single package. In addition, the LM4934 routes and mixes the stereo and mono inputs into multiple distinct output modes. The LM4934 features an I2S serial interface for full range audio and an I2C/SPI compatible interface for control. 1 23 * * * * * 18-bit Stereo DAC Multiple Distinct Output Modes Stereo Speaker Amplifier Stereo Headphone Amplifier Mono Earpiece Amplifier Mono Line Output for External Handsfree Carkit Independent Left, Right, Headphone and Mono Speaker Volume Controls Texas Instruments 3D Enhancement with Programmable Effect Level I2C/SPI (Selectable) Compatible Interface Ultra Low Shutdown Current Click and Pop Suppression Circuit APPLICATIONS * * Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. Cell Phones PDAs KEY SPECIFICATIONS * * * * * POUT, Stereo BTL, 8, 3.3V, 1% THD+N, 520mW (Typ) POUT HP, 32, 3.3V, 1% THD+N, 36mW (Typ) POUT Mono Earpiece, 32, 3.3V, 1% THD+N, 55mW (Typ) Shutdown Current, 0.6A (Typ) DAC SNR, 95dB (Typ) 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Boomer is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2005-2013, Texas Instruments Incorporated LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Block Diagram R3DIN LIN Ch A* -6 dB to 15 dB 2 I S_CLK 2 I S_SDI 2 I S_WS I S Interface and DAC 2 I C VDD SDA/SDI SCL/SCK ADDR/ENB MODE DAC gain -3 dB to 6 dB 2 Mono* -6 dB to 15 dB National 3D RIN PLL L3DIN MIN L3DOUT R3DOUT MCLK PLL_IN PLL_OUT VoL# 5~-56 dB +6 dB VoL# 5~-56 dB +6 dB Stereo Speaker 520 mW/ch 8: Class AB VoL# 5~-56 dB Mixer and Mode Select Capless Output External Stereo headphone 36 mW/32: VoL# 5~-56 dB 2 I C / SPI Interface Internal Mono Earpiece 55 mW/32: Mono VoL# 5~-56 dB +6 dB Power and Bias AVDD Line Out Bypass Cap Figure 1. Audio Sub-System Block Diagram with OCL HP Outputs R3DIN LIN I S_CLK 2 I S_SDI 2 I S_WS Ch A* -6 dB to 15 dB 2 I S Interface and DAC 2 I C VDD SDA/SDI SCL/SCK ADDR/ENB MODE DAC gain -3 dB to 6 dB 2 Mono* -6 dB to 15 dB National 3D RIN PLL L3DIN MIN L3DOUT R3DOUT MCLK PLL_IN PLL_OUT Mixer & Mode Select VoL# 5~-56 dB +6 dB VoL# 5~-56 dB +6 dB Stereo Speaker 520 mW/ch 8: Class AB VoL# 5~-56 dB Cap-Coupled External Stereo headphone 36 mW/32: VoL# 5~-56 dB 2 I C / SPI Interface VoL# 5~-56 dB Power and Bias AVDD Internal Mono Earpiece 55 mW/32: Mono +6 dB Line Out Bypass Cap Figure 2. Audio Sub-System with SE HP Outputs 2 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Connection Diagram 6 5 4 3 2 1 A B C D E F G Figure 3. 42-Bump DSBGA Top View (Bump Side Down) See Package Number YPG0042 PIN FUNCTIONS PIN PIN NAME D/A I/O DESCRIPTION A1 DGND D P DIGITAL GROUND A2 MCLK D I MASTER CLOCK A3 I2S_WS D I/O I2S WORD SELECT A4 GPIO D O TEST PIN (MUST BE LEFT FLOATING) A5 ADDR/ENB D I I2C_ADDR OR SPI_ENB DEPENDING ON I2C or SPI MODE SELECT A6 DVDD D P DIGITAL SUPPLY VOLTAGE B1 PLLVDD D P PLL SUPPLY VOLTAGE B2 I2S_SDI D I I2S SERIAL DATA INPUT B3 I2S_CLK D I/O I2S CLOCK SIGNAL B4 MODE D I SELECTS BETWEEN SPI AND I2C CONTROL INTERFACE B5 I2C_VDD D P I2C SUPPLY VOLTAGE B6 VDDIO D P I/O SUPPLY VOLTAGE C1 PLL_IN D I PLL FILTER INPUT C2 PLL_OUT D O PLL FILTER OUTPUT C3 PLLGND D P PLL GND C4 SDA/SDI D I/O I2C SDA OR SPI SDI C5 SCL/SCK D I I2C_SCL OR SPI_SCK C6 AVDD A P ANALOG SUPPLY VOLTAGE D1 AGND A P ANALOG GROUND D2 RIN A I RIGHT ANALOG IN D3 NC A D4 BYPASS A I HALF-SUPPLY BYPASS D5 LINEOUT A O MONO LINE OUT D6 RHP A O RIGHT HEADPHONE OUTPUT E1 EP- A O MONO EARPIECE OUT- E2 MIN A I MONO ANALOG IN E3 LIN A I LEFT ANALOG IN E4 R3DOUT A I RIGHT CHANNEL 3D OUTPUT E5 LHP A O LEFT HEADPHONE OUTPUT E6 CHP A O HEADPHONE CENTER PIN OUTPUT (1/2 VDD) F1 AGND A P ANALOG GND F2 EP+ A O MONO EARPIECE OUT+ NO CONNECT Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 3 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com PIN FUNCTIONS (continued) F3 L3DIN A I LEFT CHANNEL 3D INPUT F4 L3DOUT A I LEFT CHANNEL 3D OUTPUT F5 R3DIN A I RIGHT CHANNEL 3D INPUT F6 AGND A P ANALOG GND G1 LLS- A O LEFT SPEAKER OUT- G2 AVDD A P ANALOG SUPPLY VOLTAGE G3 LLS+ A O LEFT SPEAKER OUT+ G4 RLS- A O RIGHT SPEAKER OUT- G5 AVDD A P ANALOG SUPPLY VOLTAGE G6 RLS+ A O RIGHT SPEAKER OUT+ These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Analog Supply Voltage 6.0V Digital Supply Voltage 6.0V Storage Temperature -65C to +150C Input Voltage -0.3V to VDD +0.3V (4) Internally Limited ESD Susceptibility (5) 2000V ESD Susceptibility (6) 200V Power Dissipation Junction Temperature Thermal Resistance 150C JA (YPG0042) 61C/W See AN-1279 (Literature Number SNOA430) (1) (2) (3) (4) (5) (6) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. Human body model: 100pF discharged through a 1.5k resistor. Machine model: 220pF - 240pF discharged through all pins. Operating Ratings Temperature Range TMIN TA TMAX -40C TA +85C 2.7V AVDD 5.5V 2.7V DVDD 4.0V Supply Voltage 2.4V I2CVDD 4.0V 4 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Audio Amplifier Electrical Characteristics AVDD = 3.0V, DVDD = 3.0V (1) (2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol IDD Supply Current ISD Shutdown Current PO VFS Parameter THD+N VOS Offset Voltage VIN = 0, No Load All Amps On + DAC, OCL 18.5 26.5 mA (max) Headphone Mode Only, OCL 5.6 8 mA (max) Stereo Speaker Mode Only 12 19.5 mA (max) Mono Speaker Mode Only 5.9 8 mA (max) DAC Off, All Amps On, OCL 14.6 22 mA (max) 0.6 2 A (max) 420 370 mW (min) Headphone; THD = 1%; f = 1kHz, 32 SE 27 24 Earpiece; THD = 1%; f = 1kHz, 32 BTL 45 40 Vpp 0.04 % Headphone; PO = 10mW; f = 1kHz, 32 SE 0.01 % Earpiece; PO = 20mW; f = 1kHz, 32 BTL 0.04 % Line Out; VO = 1Vrms; f = 1kHz, 10k SE 0.004 % Speaker 8 55 mV (max) Earpiece 8 50 mV (max) HP (OCL) 8 40 mV See Table 1 PSRR Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P CB = 2.2F; See Table 2 See Table 2 (1) (2) (3) (4) (5) (6) Wake-Up Time mW (min) 2.4 A = weighted; 0dB gain; See Table 1 TWU mW (min) Speaker; PO = 200mW; f = 1kHz, 8 BTL Output Noise Crosstalk ) Speaker; THD = 1%; f = 1kHz, 8 BTL O Xtalk Units (Limits) Limits (4) (5 Full Scale DAC Output Total Harmonic Distortion LM4934 Typical (3) (6) Output Power DAC Conditions Loudspeaker; PO= 200mW f = 1kHz -84 dB Headphone; PO= 10mW f = 1kHz; SE -85 dB Headphone; PO= 10mW f = 1kHz; OCL -60 dB CB = 2.2F, CD6 = 0 35 ms CB = 2.2F, CD6 = 1 85 ms All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Shutdown current is measured in a normal room environment. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 5 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Audio Amplifier Electrical Characteristics AVDD = 5.0V, DVDD = 3.3V (1) (2) The following specifications apply for the circuit shown in Figure 1 with all programmable gain set at 0dB, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4934 Typical (3) IDD Supply Current ISD Shutdown Current PO VFS DAC THD+N VOS Offset Voltage mA (max) Headphone Mode Only 5.8 mA Stereo Speaker Mode Only 17 mA Mono Speaker Mode Only 7 mA DAC Off, All Amps On 19 mA 1.6 A Speaker; THD = 1%; f = 1kHz, 8 BTL 1.2 W Headphone; THD = 1%; f = 1kHz, 32 SE 80 Earpiece; THD = 1%; f = 1kHz, 32 BTL 175 Vpp 0.03 % Headphone; PO = 30mW; f = 1kHz, 32 SE 0.01 % Earpiece; PO = 40mW; f = 1kHz, 32 BTL; CD4 = 0 0.04 % Line Out; VO = 1Vrms; f = 1kHz, 10k SE 0.003 % Speaker 8 mV Earpiece 8 mV HP (OCL) 8 mV A = weighted; 0dB gain; See Table 1 See Table 1 PSRR Power Supply Rejection Ratio f = 217Hz; Vripple = 200mVP-P CB = 2.2F; See Table 3 See Table 3 TWU (1) (2) (3) (4) (5) (6) 6 Wake-Up Time mW 2.4 Output Noise Crosstalk mW Speaker; PO = 500mW; f = 1kHz, 8 BTL O Xtalk ) 24 Full Scale DAC Output Total Harmonic Distortion Units (Limits) VIN = 0, No Load All Amps On - DAC (6) Output Power Limits (4) (5 Loudspeaker; PO= 400mW f = 1kHz -86 dB Headphone; PO= 15mW f = 1kHz; OCL -56 dB Headphone; PO= 15mW f = 1kHz, SE -80 dB CB = 2.2F, CD6 = 0 45 ms CB = 2.2F, CD6 = 1 130 ms All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Shutdown current is measured in a normal room environment. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Volume Control Electrical Characteristics (1) (2) The following specifications apply for 3V AVDD 5V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4934 Typical (3 Limits (4) ) PGR VCR ACH-CH minimum gain setting -6 maximum gain setting 15 Stereo or Mono Analog Inputs PreAmp Gain Setting Range Output Volume Control for Stereo Speakers, Headphone Output, or Mono Output Range minimum gain setting, Vol = 00001 maximum gain setting Stereo Channel to Channel Gain Mismatch -56 5 Units (Limits) (5) -6.5 dB (min) -5.5 dB (max) 15.5 dB (max) 14.5 dB (min) -56.5 dB (min) -55.5 dB (max) 4.5 dB (min) 5.5 dB (max) 0.3 dB Headphone <-90 dB Line Out <-90 Vin = 1Vrms, Gain = 0dB with load, Vol = 00000 AMUTE Mute Attenuation RINPUT MIN, LIN and RIN Input Impedance (1) (2) (3) (4) (5) 23 dB 18 k (min) 28 k (max) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 7 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Digital Section Electrical Characteristics (1) (2) The following specifications apply for 3V AVDD 5V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4934 Typical (3 Limits (4) Digital Shutdown Current (6) DISD DIDD Digital Power Supply Current PLLIDD PLL Quiescent Current Units (Limits) ) (5) 0.01 1 A ALL MODES EXCEPT 0 5.3 8 mA fMCLK = 12MHz, DVDD = 3.0V 4.8 6 mA Mode 0, DVDD = 3.0V No MCLK fMCLK = 12MHz, DVDD = 3.0V Audio DAC (Typical numbers are with 6.144MHz audio clock and 48kHz sampling frequency RDAC Audio DAC Ripple 20Hz - 20kHz through headphone output PBDAC Audio DAC Passband width -3dB point SBADAC Audio DAC Stop band Attenuation Above 24kHz Audio DAC Dynamic Range SNR SNRDAC DRDAC +/-0.1 dB 22.6 kHz 76 dB DC - 20kHz, -60dBFS; AES17 Standard See Table 4 See Table 4 dB Audio DAC-AMP Signal to Noise Ratio A-Weighted, Signal = VO at 0dBFS, f = 1kHz Noise = digital zero, A-weighted, See Table 4 See Table 4 dB Internal DAC SNR A-weighted (7) 95 dB PLL fIN Input Frequency on MCLK pin 12 10 26 MHz SPI/I2C fSPI Maximum SPI Frequency 4000 kHz (max) tSPISETD SPI Data Setup Time 100 ns (max) tSPISETENB SPI ENB Setup Time 100 ns (max) tSPIHOLDD SPI Data Hold Time 100 ns (max) tSPIHOLDENB SPI ENB Hold Time 100 ns (max) tSPICL SPI Clock Low Time 125 ns (max) tSPICH SPI Clock High Time 125 ns (max) fCLKI2C I2C_CLK Frequency 400 kHz (max) tI2CHOLD I2C_DATA Hold Time 100 ns (max) tI2CSET I2C_DATA Setup Time 100 ns (max) I2C/SPI Input High Voltage VIH I2CVDD I2C/SPI Input Low Voltage VIL 0 0.7 x I2CVDD V (min) 0.3 x I2CVDD V (max) 2 I S fCLKI2S I2S_CLK Frequency I2S_RES = 0 1536 6144 I2S_RES = 1 3072 12288 I2S_WS Duty Cycle VIH (1) (2) (3) (4) (5) (6) (7) 8 50 Digital Input High Voltage kHz (max) 40 % 0.7 x DVDD V (min) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at 25C and represent the parametric norm. Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design, test, or statistical analysis. Shutdown current is measured in a normal room environment. Internal DAC only with DAC modes 00 and 01. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Digital Section Electrical Characteristics(1)(2) (continued) The following specifications apply for 3V AVDD 5V and 2.7V DVDD 4.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4934 Units (Limits) Typical (3 Limits (4) ) Digital Input Low Voltage VIL (5) 0.3 x DVDD V (max) Table 1. Output Noise AVDD = 5V and AVDD = 3V. All gains set to 0dB. Units in V. A - weighted MODE EP LS HP OCL or SE Lineout Units 1 22 22 11 9 V 2 22 22 11 9 V 3 22 22 11 9 V 4 68 88 46 35 V 5 38 48 24 20 V 6 29 34 18 15 V 7 38 48 24 20 V Table 2. PSRR AVDD = 3V. f = 217Hz; Vripple = 200mVp-p; CB = 2.2F. MODE EP (Typ) LS (Typ) LS (Limit) HP OCL or SE (Typ) 1 69 71 2 69 71 3 69 71 72 4 63 62 5 69 6 69 7 69 HP OCL or SE (Limit) Lineout (Typ) Units 70 dB 70 dB 70 dB 55 68 dB 68 61 69 dB 70 64 70 dB 68 61 69 dB 72 67 72 68 Table 3. PSRR AVDD = 5V. All gains set to 0dB. f = 217Hz; Vripple = 200mVp-p; CB = 2.2F MODE EP (Typ) LS (Typ) HP OCL or SE (Typ) Lineout (Typ) Units 1 68 72 71 70 dB 2 68 72 71 70 dB 3 68 72 71 70 dB 4 68 66 69 70 dB 5 68 69 70 70 dB 6 69 72 71 71 dB 7 68 69 70 70 dB Table 4. Dynamic Range and SNR. 3V AVDD 5V. All programmable gain set to 0dB. Units in dB. DR (Typ) SNR (Typ) Units LS 95 85 dB Lineout 100 87 dB HP 95 85 dB EP 97 87 dB Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 9 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com System Control The LM4934 is controlled via either a three wire SPI or a two wire I2C compatible interface, selectable with the MODE pin. When MODE is cleared the device is in I2C mode, when MODE is set the device is in SPI mode. This interface is used to configure the operating mode, interfaces, data converters, mixers and amplifiers. The LM4934 is controlled by writing 8 bit data into a series of write-only registers, the device is always a slave for both type of interfaces. THREE WIRE, SPI INTERFACE (MODE = 1) Three Wire Mode Write Bus Transaction ENB SCK SDI 7 0 7 0 Register Address Data Three Wire Mode Write Bus Timing TSPISETENB TSPIHOLDENB ENB TSPICL TSPIT SCK TSPICH SDI TSPISETD TSPIHOLDD Figure 4. Three Wire Mode Write Bus When the part is configured as an SPI device and the enable (ENB) line is lowered the serial data on SDI is clocked in on the rising edge of the SCK line. The protocol used is 16bit, MSB first. The upper 8 bits (15:8) are used to select an address within the device, the lower 8 bits (7:0) contain the updated data for this register. TWO WIRE I2C COMPATIBLE INTERFACE (MODE = 0) Two Wire Mode Write Bus Transaction SDA SCL S Start Condition 6-0 Host Address 7-1 W ACK Register Address 0 7-1 ACK 0 Data P ACK Stop Condition Two Wire Mode Write Bus Timing SDA TI2CSET TI2CSET TI2CHOLD TI2CSET SCL Start Condition Data ACK Stop Condition Figure 5. Two Wire Mode Write Bus 10 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 When the part is configured as an I2C device then the LM4934 will respond to one of two addresses, according to the ADDR input. If ADDR is low then the address portion of the I2C transaction should be set to write to 0010000. When ADDR is high then the address input should be set to write to 1110000. Table 5. Chip Address A6 A5 A4 A3 A2 A1 A0 Chip Address EC (1) EC (1) 1 0 0 0 0 ADR = 0 0 0 1 0 0 0 0 ADR = 1 1 1 1 0 0 0 0 (1) EC -- Externally configured by ADR pin Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 11 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Table 6. Control Registers Address Register 00h 01h (1) D7 D6 D5 D4 D3 D2 D1 D0 Mode Control 0 CD_6 0 OCL CD_3 CD_2 CD_1 CD_0 Output Control 0 0 HP_R_ OUTPUT HP_L_ OUTPUT LS_R_ OUTPUT LS_L_ OUTPUT MONO_ OUTPUT LINEOUT_ OUTPUT 02h Mono Volume Control 0 0 0 MONO_VOL_4 MONO_VOL_3 MONO_VOL_2 MONO_VOL_1 MONO_VOL_0 03h Loud Speaker LeftVolume and 3D Gain 0 3D_LEVEL_1 3D_LEVEL_0 LS_L_VOL_4 LS_L_VOL_3 LS_L_VOL_2 LS_L_VOL_1 LS_L_VOL_0 04h Loud Speaker RightVolume and 3D Control 0 3D_MODE 3D_ENABLE LS_R_VOL_4 LS_R_VOL_3 LS_R_VOL_2 LS_R_VOL_1 LS_R_VOL_0 05h Headphone Left Volume Control 0 0 0 HP_L_VOL_4 HP_L_VOL_3 HP_L_VOL_2 HP_L_VOL_1 HP_L_VOL_0 06h Headphone Right Volume Control 0 0 0 HP_R_VOL_4 HP_R_VOL_3 HP_R_VOL_2 HP_R_VOL_1 HP_R_VOL_0 07h Analog R & L Input Gain Control 0 0 ANA_R_ GAIN_2 ANA_R_ GAIN_1 ANA_R_ GAIN_0 ANA_L_ GAIN_2 ANA_L _GAIN_1 ANA_L _GAIN_0 08h Analog Mono & DAC Input Gain Control 0 DIG_R_ GAIN_1 DIG_R_ GAIN_0 DIG_L_ GAIN_1 DIG_L_ GAIN_0 MONO_IN_ GAIN_2 MONO_IN_ GAIN_1 MONO_IN_ GAIN_0 09h Clock Configu ration R_DIV_3 R_DIV_2 R_DIV_1 R_DIV_0 PLL_ ENABLE AUDIO _CLK_SEL PLL_INPUT FAST_ CLOCK 0Ah PLL M Divider 0 PLL_M_6 PLL_M_5 PLL_M_4 PLL_M_3 PLL_M_2 PLL_M_1 PLL_M_0 0Bh PLL N Divider PLL_N_7 PLL_N_6 PLL_N_5 PLL_N_4 PLL_N_3 PLL_N_2 PLL_N_1 PLL_N_0 0Ch PLL N_MOD Divider and Dither Level VCO_FAST PLL_DITH_LEV_1 PLL_DITH_LEV_0 PLL_N_MOD_4 PLL_N_MOD_3 PLL_N_MOD_2 PLL_N_MOD_ 1 PLL_N_MOD_0 0Dh PLL_P Divider 0 0 0 0 PLL_P_3 PLL_P_2 PLL_P_1 PLL_P_0 0Eh DAC Setup 0 CUST_COMP DITHER_ALW_ON DITHER_OFF MUTE_R MUTE_L DAC_MODE_1 DAC_MODE_0 0Fh Interface 0 0 0 0 I2C_FAST I2S_MODE I2S_RESOL I2S_M/S 10h COMPENSATION _C OEFF0_LSB COMP0_7 COMP0_6 COMP0_5 COMP0_4 COMP0_3 COMP0_2 COMP0_1 COMP0_0 11h COMPENSATION _C OEFF0_MSB COMP0_15 COMP0_14 COMP0_13 COMP0_12 COMP0_11 COMP0_10 COMP0_9 COMP0_8 12h COMPENSATION _C OEFF1_LSB COMP1_7 COMP1_6 COMP1_5 COMP1_4 COMP1_3 COMP1_2 COMP1_1 COMP1_0 13h COMPENSATION _C OEFF1_MSB COMP1_15 COMP1_14 COMP1_13 COMP1_12 COMP1_11 COMP1_10 COMP1_9 COMP1_8 14h COMPENSATION _C OEFF2_LSB COMP2_7 COMP2_6 COMP2_5 COMP2_4 COMP2_3 COMP2_2 COMP2_1 COMP2_0 (1) 12 All registers default to 0 on initial power-up. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Table 6. Control Registers (continued) Address Register (1) D7 D6 D5 D4 D3 D2 D1 D0 15h COMPENSATION _C OEFF2_MSB COMP2_15 COMP2_14 COMP2_13 COMP2_12 COMP2_11 COMP2_10 COMP2_9 COMP2_8 16h TEST_ REGISTER RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 13 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com System Controls Table 7. Stereo or Mono, Left or Right Volume Control MONO_VOL_4, LS_L_VOL_4, LS_R_VOL_4, HP_L_VOL_4, HP_R_VOL_4 MONO_VOL_3, LS_L_VOL_3, LS_R_VOL_3, HP_L_VOL_3, HP_R_VOL_3 MONO_VOL_2, LS_L_VOL_2, LS_R_VOL_2, HP_L_VOL_2, HP_R_VOL_2 MONO_VOL_1, LS_L_VOL_1, LS_R_VOL_1, HP_L_VOL_1, HP_R_VOL_1 MONO_VOL_0, LS_L_VOL_0, LS_R_VOL_0, HP_L_VOL_0, HP_R_VOL_0 Gain (dB) 0 0 0 0 0 Mute 0 0 0 0 1 -56 0 0 0 1 0 -52 0 0 0 1 1 -48 0 0 1 0 0 -45 0 0 1 0 1 -42 0 0 1 1 0 -39 0 0 1 1 1 -36 0 1 0 0 0 -33 0 1 0 0 1 -30 0 1 0 1 0 -28 0 1 0 1 1 -26 0 1 1 0 0 -24 0 1 1 0 1 -22 0 1 1 1 0 -20 0 1 1 1 1 -18 1 0 0 0 0 -16 1 0 0 0 1 -14 1 0 0 1 0 -12 1 0 0 1 1 -10 1 0 1 0 0 -8 1 0 1 0 1 -6 1 0 1 1 0 -4 1 0 1 1 1 -3 1 1 0 0 0 -2 1 1 0 0 1 -1 1 1 0 1 0 0 1 1 0 1 1 +1 1 1 1 0 0 +2 1 1 1 0 1 +3 1 1 1 1 0 +4 1 1 1 1 1 +5 Table 8. Mixer Code Control (1) Mode CD3 CD2 CD1 CD0 Mono Lineout Mono Earpiece LoudSpeaker L LoudSpeaker R Headphone L Headphone R 0 0 0 0 0 SD SD SD SD SD SD (1) SD -- Shutdown M -- Mono Input AL -- Analog Left Channel AR -- Analog Right Channel DL -- I2S DAC Left Channel DR -- I2S DAC Right Channel MUTE -- Mute Note: Power-On Default Mode is Mode 0 14 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Table 8. Mixer Code Control(1) (continued) 1 1 0 0 1 M M M M M M 2 1 0 1 0 AL+AR AL+AR AL AR AL AR 3 1 0 1 1 M+AL+AR M+AL+AR M+AL M+AR M+AL M+AR 4 1 1 0 0 DL+DR DL+DR DL DR DL DR 5 1 1 0 1 DL+DR+ AL+AR DL+DR+ AL+AR DL+AL DR+AR DL+AL DR+AR 6 1 1 1 0 M+DL+AL+ DR+AR M+DL+AL+ DR+AR M+DL+AL M+DR+AR M+DL+AL M+DR+AR 7 1 1 1 1 M+DL+DR M+DL+DR M+DL M+DR M+DL M+DR Table 9. Output Control (01h) Loudspeaker Left Channel Loudspeaker Right Channel LS_L_OUTPUT = 1 LS_L_OUTPUT = 0 Output On Output Off LS_R_OUTPUT = 1 LS_R_OUTPUT = 0 Output On Output Off HP_L_OUTPUT = 1 Headphone Left Channel HP_L_OUTPUT = 0 Output On OCL = 1, Output Mute HP_R_OUTPUT = 1 Headphone Right Channel HP_R_OUTPUT = 0 Output On Mono Speaker Output Lineout OCL = 0, Output Mute OCL = 1, Output Mute OCL = 0, Output Mute MONO_OUTPUT = 1 MONO_OUTPUT = 0 Output On Output Off LINEOUT_OUTPUT = 1 LINEOUT_OUTPUT = 0 Output On Output Mute OCL = 1 OCL = 0 Headphone Output Mode Headphone Output set to Capless (CHP = 1/2 AVDD) Headphone Output Set to Cap-coupled CD3 = 1 CD3 = 0 All Outputs Outputs Toggled Via Register Control All Outputs Off Table 10. Texas Instruments 3D Enhancement Level Select (03h) 3D_LEVEL_1 3D_LEVEL_0 MIX RATIO 0 0 25% 0 1 40% 1 0 55% 1 1 70% Table 11. Texas Instruments 3D Mode Control (04h) (1) (1) 3D_MODE MODE 0 3D type 1 1 3D type 2 3D type 1: ROUT = Ri - G * LOUT3D, LOUT = Li - G * ROUT3D 3D type 2: ROUT = -Ri - G * LOUT3D, LOUT = Li + G * ROUT3D Ri = Right Input Li = Left Input G = 3D gain level (Mix Ratio) ROUT3D = Ri through the high-pass filter R3D and C3D LOUT3D = Li through the high-pass filter R3D and C3D Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 15 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Table 12. Analog Input Amplifier Gain Select MONO_IN_GAIN_2 ANA_L_GAIN_2 ANA_R_GAIN_2 MONO_IN_GAIN_1 ANA_L_GAIN_1 ANA_R_GAIN_1 MONO_IN_GAIN_0 ANA_L_GAIN_0 ANA_R_GAIN_0 Input Gain Setting 0 0 0 -6dB 0 0 1 -3dB 0 1 0 0dB 0 1 1 3dB 1 0 0 6dB 1 0 1 9dB 1 1 0 12dB 1 1 1 15dB Table 13. DAC Gain Select DIG_L_GAIN_1 DIG_R_GAIN_1 DIG_L_GAIN_1 DIG_R_GAIN_1 Input Gain Setting 0 0 -3dB 0 1 0dB 1 0 3dB 1 1 6dB PLL Configuration Registers PLL M DIVIDER CONFIGURATION REGISTER This register is used to control the input divider of the PLL. Table 14. PLL_M (0Ah) (Set = logic 1, Clear = logic 0) (1) Bits Register Description 6:0 PLL_M Programs the PLL input divider to select: (1) 16 PLL_M Divide Ratio 0 Divider Off 1 1 2 1.5 3 2 4 2.5 ... 3 126 63.5 127 64 NOTES: The M divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The divider of the M divider is derived from PLL_M as such: M = (PLL_M+1) / 2 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 PLL N DIVIDER CONFIGURATION REGISTER This register is used to control PLL N divider. Table 15. PLL_N (0Bh) (Set = logic 1, Clear = logic 0) (1) (1) Bits Register Description 7:0 PLL_N Programs the PLL feedback divider: PLL_N Divide Ratio 0 Divider Off 1 10 10 11 11 12 12 ... ... 248 248 249 249 250 255 250 NOTES: The divider should be set such that the output of the divider is between 0.5 and 5MHz. See the PLL setup section for details. The N divider should never be set so that (Fin/M) * N > 55MHz (or 80MHz if FAST_VCO is set in the PLL_N_MOD register). The non-sigma-delta division of the N divider is derived from the PLL_N as such: N = PLL_N Fin /M is often referred to as Fcomp (Frequency of Comparison) or Fref (Reference Frequency). In this document, Fcomp is used. PLL P DIVIDER CONFIGURATION REGISTER This register is used to control the PLL's P divider. Table 16. PLL_P (0Dh) (Set = logic 1, Clear = logic 0) (1) (1) Bits Register Description 3:0 PLL_P Programs the PLL input divider to select: PLL_P Divide Ratio 0 Divider Off 1 1 2 1.5 3 2 ... -> 2.5 13 7 14 7.5 15 8 NOTES: The division of the P divider is derived from PLL_P as such: P = (PLL_P+1) / 2 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 17 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com PLL N MODULATOR AND DITHER SELECT CONFIGURATION REGISTER This register is used to control the Fractional component of the PLL. Table 17. PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0) (1) Bits Register Description 4:0 PLL_N_MOD This programs the PLL N Modulator's fractional component: 6:5 DITHER_LEVEL 7 (1) PLL_N_MOD Fractional Addition 0 0/32 1 1/32 2 30 2/32 30/32 31 31/32 Allows control over the dither used by the N Modulator FAST_VCO DITHER_LEVEL DAC Sub-system Input Source 00 Medium (32) 01 Small (16) 10 Large (48) 11 Off If set the VCO maximum and minimum frequencies are raised: FAST_VCO Maximum FVCO 0 40-55MHz 1 55-80MHz NOTES: The complete N divider is a fractional divider as such: N = PLL_N + (PLL_N_MOD/32) If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula: Fout = (Fin * N) / (M * P) Please see over for more details on the PLL and common settings. Further Notes on PLL Programming The sigma-delta PLL is designed to drive audio circuits requiring accurate clock frequencies of up to 25MHz with frequency errors noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample rates from any common clock source when the oversampling rate of the audio system is 125fs. In systems where 128x oversampling must be used (for example with an isochronous I2S data stream) a clock synchronous to the sample rate should be used as input to the PLL (typically the I2S clock). If no isochronous source is available then the PLL can be used to obtain a clock that is accurate to within typical crystal tolerances of the real sample rate. PLL_P M = 0, 1 + 0/2 0.5 - 26 MHz %M 4 64 Phase Comparator and Charge Pump VCO 0 256 x FS OR 250 x FS 40 to 80 MHz %P 0.5 < 5 MHz P = 0, 1 + 0/2 8 External Loop Filter 7 PLL_M %N 6'M 8 N = 0, 1, 2, .., 255 8 5 PLL_N PLL_N_MOD 18 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Table 18. Example Of Pll Settings For 48Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MO D PLL_P f_out (MHz) 11 48 11 60 5 21 60 0 9 12 12 48 5 25 5 9 25 0 9 12 12.288 48 4 19.53125 5 7 19 17 9 12 13 48 13 60 5 25 60 0 9 12 14.4 48 9 37.5 5 17 37 16 9 12 16.2 48 27 100 5 53 100 0 9 12 16.8 48 14 50 5 27 50 0 9 12 19.2 48 13 40.625 5 25 40 20 9 12 19.44 48 27 100 6 53 100 0 11 12 19.68 48 20.5 62.5 5 40 62 16 9 12 19.8 48 16.5 50 5 32 50 0 9 12 PLL_P f_out (MHz) Table 19. Example Pll Settings For 44.1Khz Sample Rates f_in (MHz) fsamp (kHz) M N P PLL_M PLL_N PLL_N_MO D 11 44.1 11 55.125 5 21 55 4 9 11.025000 11.2896 44.1 8 39.0625 5 15 39 2 9 11.025000 12 44.1 5 22.96875 5 9 22 31 9 11.025000 13 44.1 13 55.125 5 25 55 4 9 11.025000 14.4 44.1 12 45.9375 5 23 45 30 9 11.025000 16.2 44.1 9 30.625 5 17 30 20 9 11.025000 16.8 44.1 17 55.78125 5 33 55 25 9 11.025000 19.2 44.1 16 45.9375 5 31 45 30 9 11.025000 19.44 44.1 13.5 38.28125 5 26 38 9 9 11.025000 19.68 44.1 20.5 45.9375 4 40 45 30 7 11.025000 19.8 44.1 11 30.625 5 21 30 20 9 11.025000 These tables cover the most common applications, obtaining clocks for sample rates such as 22.05kHz and 192kHz should be done by changing the P divider value or the R divider in the clock configuration diagram. If the user needs to obtain a clock unrelated to those described above, the following method is advised. An example of obtaining 11.2896 from 12.000MHz is shown below. Choose a small range of P so that the VCO frequency is swept between 45 and 55MHz (or 60-80MHz if VCOFAST is used). Remembering that the P divider can divide by half integers. So for P = 4.0 7.0 sweep the M inputs from 2.5 24. The most accurate N and N_MOD can be calculated by: N = FLOOR(((Fout/Fin)*(P*M)),1) N_MOD = ROUND(32*((((Fout)/Fin)*(P*M)-N),0) (1) This shows that setting M = 11.5, N = 75 N_MOD = 47 P = 7 gives a comparison frequency of just over 1MHz, a VCO frequency of just under 80MHz (so VCO_FAST must be set) and an output frequency of 11.289596 which gives a sample rate of 44.099985443kHz, or accurate to 0.33 ppm. Care must be taken when synchronization of isochronous data is not possible, i.e. when the PLL has to be used in the above mode. The I2S should be master on the LM4934 so that the data source can support appropriate SRC as required. This method should only be used with data being read on demand to eliminate sample rate mismatch problems. Where a system clock exists at an integer multiple of the required DAC clock rate it is preferable to use this rather than the PLL. The LM4934 is designed to work in 8,12,16,24,32, and 48kHz modes from a 12MHz clock without the use of the PLL. This saves power and reduces clock jitter. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 19 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Clock Configuration Register This register is used to control the multiplexers and clock R divider in the clock module. Table 20. CLOCK (09h) (Set = logic 1, Clear = logic 0) Bits Register Description 0 FAST_CLOCK If set master clock is divided by two. FAST_CLOCK 1 PLL_INPUT MCLK Frequency 0 Normal 1 Divided by 2 Programs the PLL input multiplexer to select: PLL_INPUT PLL Input Source 0 MCLK 1 I2S Input Clock Selects which clock is passed to the audio sub-system 2 20 DAC_CLK_SEL DAC Sub-system Input Source 0 PLL Input 1 PLL Output AUDIO_CLK_SEL 3 PLL_ENABLE If set enables the PLL. (MODES 4-7 only) 7:4 R_DIV Programs the R divider R_DIV Divide Value 0000 1 0001 1 0010 1.5 Submit Documentation Feedback 0011 2 0100 2.5 0101 3 0110 3.5 0111 4 1000 4.5 1001 5 1010 5.5 1011 6 1100 6.5 1101 7 1110 7.5 1111 8 Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 fast_clock %2 MCLK 1 0 audio_dk_sel pll_input 0 1 PLL input clock PLL output clock I2S Interface R Div input clock %R Clock Gen input clock DAC Clock Gen I2S_INT_CLK I2S_INPUT_CLK I2S_CLK 0 1 PLL Stereo DAC 125/128 DSP CLK I2S_OUTPUT_CLK By default the stereo DAC operates at 250*fs, i.e. 12.000MHz (at the clock generator input clock) for 48kHz data. It is expected that the PLL be used to drive the audio system unless a 12.000MHz master clock is supplied. The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL. Common Clock Settings for the DAC The DAC can work in 4 modes, each with different oversampling rates, 125,128,64 & 32. In normal operation 125x oversampling provides for the simplest clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or USB) at 48kHz exactly. The other modes are useful if data is being provided to the DAC from an uncontrollable isochronous source (such as a CD player, DAB, or other external digital source) rather than being decoded from memory. In this case the PLL can be used to derive a clock for the DAC from the I2S clock. The DAC oversampling rate can be changed to allow simpler clocking strategies, this is controlled in the DAC SETUP register but the oversampling rates are as follows: DAC MODE Oversampling Ratio Used 00 125 01 128 10 64 11 32 The following table describes the clock required at the clock generator input for various clock sample rates in the different DAC modes: Fs (kHz) DAC Oversampling Ratio Required CLock at DAC Clock Generator Input (MHz) 8 125 2 8 128 2.048 11.025 125 2.75625 11.025 128 2.8224 12 125 3 12 128 3.072 16 125 4 16 128 4.096 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 21 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Fs (kHz) DAC Oversampling Ratio Required CLock at DAC Clock Generator Input (MHz) 22.05 125 5.5125 22.05 128 5.6448 24 125 6 24 128 6.144 32 125 8 32 128 8.192 44.1 125 11.025 44.1 128 11.2896 48 125 12 48 128 12.288 88.2 64 11.2896 96 64 12.288 176.4 32 22.5792 192 32 24.576 Methods for producing these clock frequencies are described in the PLL section. The R divider can be used when the master clock is exactly 12.00 MHz in order to generate different sample rates. The Table below shows different sample rates supported from 12.00MHz by using only the R divider and disabling the PLL. In this way we can save power and the clock jitter will be low. R_DIV Divide Value DAC Clock Generator Input Frequency <MHz> Sample Rate Supported <KHz> 11 6 2 8 9 5 2.4 9.6 7 4 3 12 5 3 4 16 4 2.5 4.8 19.2 3 2 6 24 2 1.5 8 32 0 1 12 48 The R divider can also be used along with the P divider in order to create the clock needed to support low sample rates. DAC Setup Register This register is used to configure the basic operation of the stereo DAC. Table 21. DAC_SETUP (0Eh) Bits Register Description 1:0 DAC_MODE The DAC used in the LM4934 can operate in one of 4 oversampling modes. The modes are described as follows: DAC_MODE 2 22 (Set = logic 1, Clear = logic 0) Oversampling Rate Typical FS Clock Required 00 125 48KHz 12.000MHz (USB Mode) 01 128 44.1KHz 48KHz 11.2896MHz 12.288MHz 10 64 96KHz 12.288MHz 11 32 192KHz 24.576MHz MUTE_L Mutes the left DAC channel on the next zero crossing. 3 MUTE_R Mutes the right DAC channel on the next zero crossing. 4 DITHER_OFF If set the dither in DAC is disabled. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Table 21. DAC_SETUP (0Eh) (Set = logic 1, Clear = logic 0) (continued) Bits Register Description 5 DITHER ALWAYS_ON If set the dither in DAC is enabled all the time. 6 CUST_COMP If set the DAC frequency response can be programmed manually via a 5 tap FIR "compensation" filter. This can be used to enhance the frequency response of small loudspeakers or provide a crude tone control. The compensation Coefficients can be set by using registers 10h to 15h. Interface Control Register This register is used to control the I2S and I2C compatible interface on the chip. Table 22. INTERFACE (0Fh) (Set = logic 1, Clear = logic 0) (1) Bits Register Description 0 I2S_MASTER_SLAVE If set the LM4934 acts as a master for I2S, so both I2S clock and I2S word select are configured as outputs. If cleared the LM4934 acts as a slave where both I2S clock and word select are configured as inputs. 1 I2S_RESOLUTION If set the I2S resolution is set to 32 bits. If clear, resolution is set to 16 bits. This bit only affects the I2S Interface in master mode. In slave mode the I2S Interface can support any I2S compatible resolution. In master mode the I2S resolution also depends on the DAC mode as the note below explains. 2 I2S_MODE If set the I2S is configured in left justified mode timing. If clear, the I2S interface is configured in normal I2S mode timing. 3 I2C_FAST If set enables the I2C to run in fast mode with an I2C clock up to 3.4MHz. If clear the I2C speed gets its default value of a maximum of 400kHz (1) NOTES: The master I2S format depends on the DAC mode. In USB mode the number of bits per word is 25 (i.e. 2.4MHz for a 48kHz sample rate). The duty cycle is 40/60. In non-USB modes the format is 32 or 16 bits per word, depending on I2S_RESOLTION and the duty cycle is always 50-50. In slave mode it will decode any I2S compatible data stream. LEFT CHANNEL RIGHT CHANNEL 2 I S_WS 2 I S_CLK 2 1 I S_SDO 2 3 n-1 MSB n 1 LSB MSB 2 3 n-1 n LSB Figure 6. I2S Mode Timing LEFT CHANNEL RIGHT CHANNEL 2 I S_WS 2 I S_CLK 2 I S_SDO 1 2 3 MSB n-1 n 1 LSB MSB 2 3 n-1 n LSB Figure 7. Left Justified Mode Timing Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 23 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com FIR Compensation Filter Configuration Registers These registers are used to configure the DAC's FIR compensation filter. Three 16 bit coefficients are required and must be programmed via the I2C/SPI Interface in bytes as follows: Table 23. COMP_COEFF (10h 15h) (Set = logic 1, Clear = logic 0) (1) (1) Address Register Description 10h COMP_COEFF0_LSB Bits [7:0] of the 1st and 5th FIR tap (C0 and C4) 11h COMP_COEFF0_MSB Bits [15:8] of the 1st and 5th FIR tap (C0 and C4) 12h COMP_COEFF1_LSB Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3) 13h COMP_COEFF1_MSB Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3) 14h COMP_COEFF2_LSB Bits [7:0] of the 3rd FIR tap (C2) 15h COMP_COEFF2_MSB Bits [15:8] of the 3rd FIR tap (C2) NOTES: The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half. -1 -1 Z C0 -1 Z C1 -1 Z C2 Z C3 C4 If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC into the analog mixer, these values are: DAC_OSR C0, C4 C1, C3 C2 00 68 -412 28526 01, 10, 11 112 -580 27551 If using 96 or 192kHz data then the custom compensation may be required to obtain flat frequency responses above 24kHz. The total power of any custom filter must not exceed that of the above examples or the filters within the DAC will clip. The coefficient must be programmed in 2's complement. 24 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Typical Performance Characteristics 10 THD+N vs Frequency 3V Lineout, RL = 10k, VO = 850mV 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 20 THD+N vs Frequency 3V EP Out, RL = 32, PO = 20mW 0.1 0.01 100 1k 0.001 20 10k 20k 100 FREQUENCY (Hz) Figure 8. 10 THD+N vs Frequency 3V HP Out, RL = 16, PO = 20mW 10 THD+N (%) THD+N (%) THD+N vs Frequency 3V LS Out, RL = 8, PO = 200mW 1 0.1 0.01 0.1 0.01 100 1k 0.001 20 10k 20k 100 FREQUENCY (Hz) 10 10k 20k Figure 10. Figure 11. THD+N vs Frequency 5V EP, RL = 32, PO = 40mW THD+N vs Frequency 5V HP Out, RL = 16, PO = 60mW 10 1 THD+N (%) THD+N (%) 1k FREQUENCY (Hz) 1 0.1 0.01 0.001 20 10k 20k Figure 9. 1 0.001 20 1k FREQUENCY (Hz) 0.1 0.01 100 1k 10k 20k 0.001 20 FREQUENCY (Hz) 100 1k 10k 20k FREQUENCY (Hz) Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 25 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 10 THD+N vs Frequency 5V HP Out, RL = 32, PO = 30mW 10 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 20 0.1 0.01 100 1k 0.001 20 10k 20k THD+N vs Output Power 3V EP Out, RL = 16, f = 1kHz THD+N vs Output Power 3V EP Out, RL = 32, f = 1kHz 10 1 1 0.1 0.1 0.01 10m 0.001 1m 50m 100m OUTPUT POWER (W) 10m 50m 100m OUTPUT POWER (W) Figure 16. Figure 17. THD+N vs Output Power 3V HP Out, RL = 16, f = 1kHz THD+N vs Output Power 3V HP Out, RL = 32, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) 10k 20k Figure 15. 0.01 0.1 0.01 0.1 0.01 10m 50m 100m 0.001 1m OUTPUT POWER (W) 10m 50m 100m OUTPUT POWER (W) Figure 18. 26 1k Figure 14. 10 0.001 1m 100 FREQUENCY (Hz) THD+N (%) THD+N (%) FREQUENCY (Hz) 0.001 1m THD+N vs Frequency 5V LS Out, RL = 8, PO = 500mW Figure 19. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Typical Performance Characteristics (continued) THD+N vs Output Power 5V EP Out, RL = 16, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) THD+N vs Output Power 3V LS Out, RL = 8, f = 1kHz 0.1 0.01 0.1 0.01 0.001 10m 100m 0.001 1m 500m Figure 21. THD+N vs Output Power 5V EP Out, RL = 32, f = 1kHz THD+N vs Output Power 5V HP Out, RL = 16, f = 1kHz 10 1 1 0.1 0.01 0.1 0.01 10m 0.001 1m 100m 200m 10m 100m 200m OUTPUT POWER (W) Figure 22. Figure 23. THD+N vs Output Power 5V HP Out, RL = 32, f = 1kHz THD+N vs Output Power 5V LS Out, RL = 8, f = 1kHz 10 10 1 1 THD+N (%) THD+N (%) OUTPUT POWER (W) 0.1 0.01 0.001 1m 100m 200m OUTPUT POWER (W) 10 0.001 1m 10m Figure 20. THD+N (%) THD+N (%) OUTPUT POWER (W) 0.1 0.01 10m 100m 200m 0.001 10m 100m 2 OUTPUT POWER (W) OUTPUT POWER (W) Figure 24. Figure 25. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 27 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) THD+N vs I2S Level HP Out 10 10 1 1 THD+N (%) THD+N (%) THD+N vs I2S Level EP Out 0.1 0.1 0.01 0.01 0.001 1m 10m 100m 0.001 1m 1 Figure 27. THD+N vs I2S Level Line Out THD+N vs I2S Level LS Out 10 10 1 1 0.1 0.01 0.001 1m 10m 100m 0.001 1m 1 10m Figure 28. PSRR vs Frequency 3V EP Out Mode 1 PSRR vs Frequency 3V EP Out Mode 4 -10 -10 -20 -20 -30 -30 PSRR (dB) 0 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 1k 1 Figure 29. 0 100 100m I2S INPUT LEVEL (FFS) I2S INPUT LEVEL (FFS) PSRR (dB) 1 0.1 0.01 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. 28 100m Figure 26. THD+N (%) THD+N (%) 10m I2S INPUT LEVEL (FFS) I2S INPUT LEVEL (FFS) Figure 31. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Typical Performance Characteristics (continued) PSRR vs Frequency 3V HP Out Mode 4 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) PSRR vs Frequency 3V HP Out Mode 2 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 100 1k 10k 100k 100 Figure 33. PSRR vs Frequency 3V Line Out Mode 1 PSRR vs Frequency 3V Line Out Mode 4 0 0 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 100 1k 10k -100 20 100k 100 1k 10k Figure 34. Figure 35. PSRR vs Frequency 3V LS Out Mode 2 PSRR vs Frequency 3V LS Out Mode 4 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 1k 10k 100k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) 100 100k -40 -70 -100 20 10k Figure 32. -10 -100 20 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) 100k -100 20 FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 36. Figure 37. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 29 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) PSRR vs Frequency 5V HP Out Mode 4 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) PSRR vs Frequency 5V HP Out Mode 2 -40 -50 -60 -40 -50 -60 -70 -70 -80 -80 -90 -90 -100 20 -100 20 100 1k 10k 100k 100 Figure 39. PSRR vs Frequency 5V Line Out Mode 1 PSRR vs Frequency 5V Line Out Mode 4 0 0 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 100 1k 10k -100 20 100k 100 10k Figure 40. Figure 41. PSRR vs Frequency 5V LS Out Mode 4 PSRR vs Frequency 5V LS Out Mode 2 0 0 -10 -10 -20 -20 -30 -30 -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 1k 10k 100k -40 100k -100 20 FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 42. 30 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) 100 100k -40 -70 -100 20 10k Figure 38. -10 -100 20 1k FREQUENCY (Hz) PSRR (dB) PSRR (dB) FREQUENCY (Hz) Figure 43. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 Typical Performance Characteristics (continued) XTalk vs Frequency 5V LS Out Mode 2, RL = 8, 1VRMS 0 0 -10 -10 -20 -20 -30 -30 PSRR (dB) PSRR (dB) XTalk vs Frequency 5V HP Out Mode 2, RL = 32, 1VRMS, SE -40 -50 L to R -60 -70 -40 -50 -60 -70 R to L -80 -80 -90 -90 -100 20 100 1k L to R R to L -100 20 10k 20k 100 1k 10k 20k FREQUENCY (Hz) Figure 44. Figure 45. Output Power vs Supply Voltage EP Out, RL = 32, 1% THD+N Output Power vs Supply Voltage HP Out, RL = 32, 1% THD+N 280 150 240 130 OUTPUT POWER (mW) OUTPUT POWER (mW) FREQUENCY (Hz) 200 160 120 80 40 0 2.7 110 90 70 50 30 3 3.5 4 4.5 5 10 2.7 5.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 46. Figure 47. Output Power vs Supply Voltage LS Out, RL = 8, 1% THD+N 2 1.8 OUTPUT POWER (W) 1.6 1.4 1.2 1 800m 600m 400m 200m 0 2.7 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) Figure 48. Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 31 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION I2S The LM4934 supports both master and slave I2S transmission at either 16 or 32 bits per word at clock rates up to 3.072MHz (48kHz stereo, 32bit). The basic format is shown below: TEXAS INSTRUMENTS 3D AUDIO ENHANCEMENT The LM4934 utilizes a programmable gain version of Texas Instruments' 3D audio enhancement circuit. This allows 3D gain only (not frequency response) to be controlled via I2C/SPI in the Texas Instruments 3D Enhancement Level Select registers (3D1 and 3D0). Also, this circuit uses the same 3D path for both the headphone and stereo loudspeaker outputs, so the 3D effect remains constant when switching from headphone to stereo loudspeaker outputs unless changed in the registers. An added benefit of this is that the gain of the original signal is unaffected when 3D is turned on/off. 3D gain is established internally with R3D (approximately 30k) and externally with C3D. Typical values for C3D are around 0.22F, but may varied for altered 3D response. Gain Considerations When using the mixer and 2,3,4, or 5 channels are summed into the stereo output (headphone or speaker), the gain of each individual input is automatically reduced by 1/N, where N is the number of channels being summed. This has the effect of maintaining the total signal output level for different modes (i.e.; when LIN and RIN are summed for a mono output, gain for RIN and LIN will each be reduced by 6dB). This is not true for mono output modes, like EP and lineout. For these cases, stereo inputs are treated as one input with a -6dB gain for each input before summing this with a mono input. An example of relative output levels for each mode is given below: Mode Mono Out Stereo R Out Stereo L Out 1 M M M 2 (AL/2)+(AR+2) AR AL 3 [M+(AL/2)+(AR/2)]/2 (M+AR)/2 (M+AL)/2 4 (DL/2)+(DR/2) DR DL 5 [(AL/2)+(AR/2)+(DL/2)+(DR/2)]/2 (AR+DR)/2 (AL+DL)/2 6 [M+(AL/2)+(AR/2)+(DL/2)+(DR/2) ]/2 (M+AR+DR)/3 (M+AL+DL)/3 7 [M+(DL/2)+(DR/2)]/2 (M+DR)/2 (M+DL)/2 LM4934 DEMOBOARD OPERATION BOARD LAYOUT DIGITAL SUPPLIES JP14 -- Digital Power DVDD JP14 -- I/O Power IOVDD JP14 -- PLL Supply PLLVDD JP14 -- USB Board Supply BBVDD JP14 -- I2C VDD 32 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 All supplies may be set independently. All digital ground is common. Jumpers may be used to connect all the digital supplies together. S9 - connects VDD_PLL to VDD_D S10 - connects VDD_D to VDD_IO S11 - connects VDD_IO to VDD_I2C S12 - connects VDD_I2C to Analog VDD S17 - connects BB_VDD to USB3.3V (from USB board) S19 - connects VDD_D to USB3.3V (from USB board) S20 - connects VDD_D to SPDIF receiver chip ANALOG SUPPLY JP11 -- Analog Supply S12 -- connects Analog VDD with Digital VDD (I2C_VDD) S16 -- connects Analog Ground with Digital Ground S21 -- connects Analog VDD to SPDIF receiver chip INPUTS Analog Inputs JP2 -- Mono Input JP6 -- Left Input JP7 -- Right Input Digital Inputs JP19 -- Digital Interface Pin 1 -- MCLK Pin 2 -- I2S_CLK Pin 3 -- I2S_SDI Pin 4 -- I2S_WS JP20 -- Toslink SPDIF Input JP21 -- Coaxial SPDIF Input Coaxial and Toslink inputs may be toggled between by use of S25. Only one may be used at a time. Must be used in conjunction with on-board SPDIF receiver chip. OUTPUTS JP4 -- Right BTL Loudspeaker Output JP5 -- Left BTL Loudspeaker Output JP1 -- Left Headphone Output (Single-Ended or OCL) JP3 -- Right Headphone Output (Single-Ended or OCL) P1 -- Stereo Headphone Jack (Same as JP1, JP2, Single-Ended or OCL) JP12 -- Mono BTL Earpiece Output JP8 -- Single-Ended Line Level Output Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 33 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com CONTROL INTERFACE X1, X2 - USB Control Bus for I2C/SPI X1 Pin 9 - Mode Select (SPI or I2C) X2 Pin 1 - SDA Pin 3 - SCL Pin 15 - ADDR/END Pin 14 - USB5V Pin 16 - USB3.3V Pin 16 - USB GND MISCELLANEOUS I2S BUS SELECT S23, S24, S26, S27 - I2S Bus select. Toggles between on-board and external I2S (whether on-board SPDIF receiver is used). All jumpers must be set the same. Jumpers on top two pins selects external bus (JP19). Jumpers on bottom two pins selects on-board SPDIF receiver output. HEADPHONE OUTPUT CONFIGURATION Jumpers S1, S2, S3, and S4 are used to configure the headphone outputs for either cap-coupled outputs or output capacitorless (OCL) mode in addition to the register control internal to the LM4934 for this feature. Jumpers S1 and S3 bypass the output DC blocking capacitors when OCL mode is required. S2 connects the center amplifer HPCOUT to the headphone ring when in OCL mode. S4 connects the center ring to GND when cap-coupled mode is desired. S4 must be removed for OCL mode to function properly. Jumper settings for each mode: OCL S1 = ON S2 = ON S3 = ON S4 = OFF Cap-Coupled S1 = OFF S2 = OFF S3 = OFF S4 = ON PLL FILTER CONFIGURATION The LM4934 demo board comes with a simple filter setup by connecting jumpers S5 and S6. Removing these and connecting jumpers S7 and S8 will allow for an alternate PLL filter configuration to be used at R2 and C23. 34 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 LM4934 www.ti.com SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 ON-BOARD SPDIF RECEIVER The SPDIF receiver present on the LM4934 demo board allows quick demonstration of the capabilities of the LM4934 by using the common SPDIF output found on most CD/DVD players today. There are some limitations in its useage, as the receiver will not work with digital supplies of less than 3V and analog supplies of less than 4V. This means low analog supply voltage testing of the LM4934 must be done on the external digital bus. The choice of using on-board or external digital bus is made usign jumpers S23, S24, S26, and S27 as described above. S25 selects whether the Toslink or Coaxial SPDIF input is used. The top two pins connects the toslink, the bottom two connect the coaxial input. Power on the digital side is routed through S20 (connecting to the other digital supplies), while on the analog side it is interrupted by S21. Both jumpers must be in place for the receiver to function. The part is already configured for I2S standard outputs. Jumper S28 allows the DATA output to be pulled either high or low. Default is high (jumper on right two pins). It may be necessary to quickly toggle S29 to reset the receiver and start it working upon initial power up.. A quick short across S29 should clear this condition. LM4934 I2C/SPI INTERFACE SOFTWARE Convenient graphical user interface software is available for demonstration purposes of the LM4934. It allows for either SPI or I2C control via either USB or parallel port connections to a Windows computer. Control options include all mode and output settings, volume controls, PLL and DAC setup, FIR setting and on-the-fly adjustment by an easy to use graphical interface. An advanced option is also present to allow direct, register-level commands. Demonstration Board Schematic VDD_D C1 1 uF C2 VDD_A 0.1 uF C3 VDD_I2C 0.1 uF C4 1 uF VDD_PLL C5 1 uF C8 0.1 uF C6 C7 0.22 uF 0.22 uF C9 1 uF E2 0.47uF E3 C14 D2 B3 B2 A3 0.47uF Header 2 BBVDD JP16 VDD_A S17 S18 BB_VDD C4 C5 A5 B4 USB_5V 2 1 USB_3.3V EXTERNAL DIGITAL INTERFACE JP19 14 7 13 6 VDD_A 12 5 11 4 10 3 SW SPST 9 2 S21 8 1 S19 VDD_D L1 S20 JP20 47 uH C20 S7 C21 R7 47k R5 9 8 S29 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 X2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 F4 F3 G2 G5 C6 L3D_OUT L3D_IN PLL_VDD I2C_VDD DVDD R3D_OUT R3D_IN AVDD AVDD AVDD HPROUT HPCOUT HPLOUT EPOUTP EPOUTM BP 1 2 D6 E6 E5 C12 220 uF S2 1 2 GPIO VDD_I/O NC C15 D5 220 uF A4 B6 VDD_IO 1 2 R1 10k P1 C13 220 uF JP12 F2 E1 S3 JP8 LINEOUT SDA/SDI SCL/SCK ADDR/ENBL MODE 1 2 S1 JP5 Stereo Headphone Jack S4 JP9 1 2 C16 D3 1 uF 150 nF R3 422 C23 0.1 uF MCLK I2S_WS I2S_CLK I2S_DOUT U2 CS8415A CHS RST FILT C27 0.33 uF X1 USB_SDA USB_SCL H/S EMPH ORIG R9 1.6k C26 4.7 nF USB_SPI_M RXN 6 2 27 23 14 R8 47k RXP AVDD 5 24 3 28 AGND 4 0.01 uF C25 0.01 uF 47k DVDD DVDD DVDD C24 2 3 R4 75 U1 LM4934RL I2S_CLK I2S_SDI I2S_WS 1 2 G1 G3 S24 0.1 uF DGND DGND DGND S2 5 1 JP21 S/PDIF IN R_IN C18 C19 10 nF R2 C22 L_IN C17 2.2 uF S8 S23 0.1 uF 2 TOSLINK RECEIVER USB_CS S5 S26 10 17 16 18 R6 AUDIO C U NVERR PRO RCBL RERR COPY 19 26 25 15 13 12 11 1 S10 S9 VDD_PLL JP13 S27 1 2 47k S28 VDD_D JP14 1 2 S11 VDD_IO JP10 1 2 S12 VDD_I2C JP15 1 2 VDD_A JP11 1 2 3 2 1 S16 BBVDD R11 7 GND 3 1 20 21 22 VCC OUTPUT D4 S6 LSLOUTM LSLOUTP C3 VDD_D LSROUTM LSROUTP M_IN AGRND AGRND AGRND 1 2 C11 1 2 JP3 JP4 G4 G6 D1 F1 F6 Header 2 JP7 0.47uF DGND 1 2 PLL_GND Header 2 JP6 A1 1 2 JP2 MCLK PLL_IN PLL_OUT E4 F5 B1 B5 A6 JP1 A2 C1 C2 C10 R10 USB_SPIDO USB_SCL USB_SDA USB_CS 5k 5k R12 5k USB_SPI_M S22 USB_5V USB_SPIDO USB_3.3V USB INTERFACE Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 35 LM4934 SNAS343F - OCTOBER 2005 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Rev Date Description 1.0 9/22/05 Started D/S by copying LM4931 (DS201009). Did major edits. 1.1 9/27/05 Input some text/Typical/Limits on the EC tables. 1.2 10/6/05 Added Table 1, Table 2, and Table 3. Input some text edits also. 1.3 10/11/05 Input more edits. 1.4 10/12/05 First WEB release of the D/S. 1.5 10/13/05 D/S was taken out of the WEB per Daniel. 1.6 10/19/05 Text edits and curves. 1.7 10/21/05 Added K6 (by Diane T.), will release to the per Daniel. 1.8 10/24/06 Fixed typos, then released to the WEB. 1.9 11/10/05 Added the internal DAC SNR (with 95dB typ) under Key Spec and into the Digital EC table. 2.0 11/15/05 Added the SNR DAC, then re-webd per Daniel. 2.1 12/14/05 Removed the WL package and replaced it with the RL. 2.2 12/19/05 Removed the WL package and replaced it with the RL package (per Veronica and Daniel A.), then released D/S to the WEB. 2.3 1/19/06 Edited 20166956 (board schem, changed WL to RL), X1, X2,and X3 values. 2.4 2/13/06 Switched the labels of B3 and B2 on the Demo Board Schematic (pg 37) per Daniel. Changes from Revision E (April 2013) to Revision F * 36 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 35 Submit Documentation Feedback Copyright (c) 2005-2013, Texas Instruments Incorporated Product Folder Links: LM4934 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Top-Side Markings (3) (4) LM4934RL/NOPB ACTIVE DSBGA YPG 42 250 Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GG9 LM4934RLX/NOPB ACTIVE DSBGA YPG 42 1000 Green (RoHS & no Sb/Br) SNAG Level-1-260C-UNLIM -40 to 85 GG9 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM4934RL/NOPB DSBGA YPG 42 250 178.0 12.4 LM4934RLX/NOPB DSBGA YPG 42 1000 178.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.43 3.99 0.76 8.0 12.0 Q1 3.43 3.99 0.76 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4934RL/NOPB DSBGA YPG LM4934RLX/NOPB DSBGA YPG 42 250 210.0 185.0 35.0 42 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YPG0042xxx D 0.6500.075 E RLA42XXX (Rev B) D: Max = 3.818 mm, Min =3.757 mm E: Max = 3.267 mm, Min =3.206 mm 4214896/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. 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