Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 LMH6702 1.7-GHz Ultra-Low Distortion Wideband Op Amp 1 Features 3 Description VS = 5 V, TA = 25C, AV = 2V/V, RL = 100 , VOUT = 2 VPP, Typical Unless Noted: 1 * * * * * * * * * 2nd and 3rd Harmonics (5 MHz, SOT-23) -100/-96 dBc -3-dB Bandwidth (VOUT = 0.5 VPP) 1.7 GHz Low Noise 1.83 nV/Hz Fast Settling to 0.1% 13.4 ns Fast Slew Rate 3100 V/s Supply Current 12.5 mA Output Current 80 mA Low Intermodulation Distortion (75 MHz) -67 dBc Improved Replacement for CLC409 and CLC449 2 Applications * * * * * * Flash A-D Driver D-A Transimpedance Buffer Wide Dynamic Range IF Amp Radar and Communication Receivers Line Driver High Resolution Video The LMH6702 is a very wideband, DC-coupled monolithic operational amplifier designed specifically for wide dynamic range systems requiring exceptional signal fidelity. Benefitting from current feedback architecture, the LMH6702 offers unity gain stability at exceptional speed without need for external compensation. With its 720-MHz bandwidth (AV = 2 V/V, VO = 2 VPP), 10-bit distortion levels through 60-MHz (RL = 100 ), 1.83-nV/Hz input referred noise and 12.5-mA supply current, the LMH6702 is the ideal driver or buffer for high-speed flash A-D and D-A converters. Wide dynamic range systems such as radar and communication receivers that require a wideband amplifier offering exceptional signal purity will find the low input referred noise and low harmonic and intermodulation distortion of the LMH6702 an attractive high speed solution. The LMH6702 is constructed using VIP10TM complimentary bipolar process and proven current feedback architecture. The LMH6702 is available in SOIC and SOT-23 packages. Device Information(1) PART NUMBER LMH6702 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm x 3.91 mm SOT-23 (5) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Inverting Frequency Response 1 AV = -1 GAIN -180 -230 -3 AV = -4 -4 -5 -280 -6 -7 1M 10M 100M Frequency (Hz) -65 -70 HD2, RL = 100 : -75 -80 HD3, RL = 100 : -330 -85 -380 -90 -95 AV = -10 -430 1G HD2, RL = 1 k: -60 HD (dBc) PHASE Phase () -130 -1 Gain (dB) -40 -45 -50 -55 AV = -2 -80 0 -2 Harmonic Distortion vs Load and Frequency -30 -100 -105 1M HD3, RL = 1 k: 10M Frequency (Hz) 100M 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Feature Description................................................. 11 7.3 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 15 10 Layout................................................................... 15 10.1 Layout Guidelines ................................................. 15 10.2 Layout Example .................................................... 16 11 Device and Documentation Support ................. 17 11.1 11.2 11.3 11.4 11.5 Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 17 17 17 17 17 12 Mechanical, Packaging, and Orderable Information ........................................................... 17 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (October 2014) to Revision H Page * Updated Thermal Information................................................................................................................................................. 4 * Changed non-inverting input bias (with no test conditions) current maximum value from 15 A to -15 A........................ 6 * Changed non-inverting input bias (-40 TJ 85) current maximum value from 21 A to -21 A ...................................... 6 * Added Community Resources section ................................................................................................................................. 17 Changes from Revision F (March 2013) to Revision G Page * Added, updated, or renamed the following sections: Device Information; Specifications; Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information .................................................................................................................................... 1 * Changed 5 V to 4 V in Recommended Operating Conditions............................................................................................ 4 Changes from Revision E (March 2013) to Revision F * 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View D Package 8-Pin SOIC Top View 1 5 OUT + V N/C -IN V - 2 8 - 7 + 6 N/C V + 2 + +IN 1 +IN 4 3 -IN V - 3 4 5 OUT N/C NC: No internal connection Pin Functions PIN NAME NUMBER I/O DESCRIPTION D DBV -IN 2 4 I Inverting input voltage +IN 3 3 I Non-inverting input voltage N/C 1, 5, 8 - - No connection OUT 6 1 O Output V- 4 2 I Negative supply V+ 7 5 I Positive supply Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 3 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN VS IOUT MAX UNIT 6.75 V See Common mode input voltage V- to V+ V 150 C Maximum junction temperature -65 Storage temperature Soldering information (1) (2) (3) (3) 150 C Infrared or convection (20 s) 235 C Wave soldering (10 s) 260 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. The maximum output current (IOUT) is determined by device power dissipation limitations. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Machine Model (MM), per JEDEC specification JESD22-C101, all pins (2) 200 UNIT V Human body model: 1.5 k in series with 100 pF. JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 2000-V HBM is possible with the necessary precautions. Pins listed as 2000 V may actually have higher performance. Machine model: 0 in series with 200 pF. JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 200-V MM is possible with the necessary precautions. Pins listed as 200 V may actually have higher performance. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) Operating temperature Nominal supply voltage (1) MIN MAX -40 85 UNIT C 4 6 V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. 6.4 Thermal Information LMH6702 THERMAL METRIC (1) DBV (SOT-23) D (SOIC) 5 PINS 8 PINS UNIT RJA Junction-to-ambient thermal resistance 182 133 C/W RJC(top) Junction-to-case (top) thermal resistance 139 79 C/W RJB Junction-to-board thermal resistance 40 73 C/W JT Junction-to-top characterization parameter 28 28 C/W JB Junction-to-board characterization parameter 40 73 C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953). Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 6.5 Electrical Characteristics at AV = 2, VS = 5 V, RL = 100 , RF = 237 (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT FREQUENCY DOMAIN PERFORMANCE SSBWSM VOUT = 0.5 VPP SSBWLG VOUT = 2 VPP 720 VOUT = 4 VPP 480 VOUT = 2 VPP, AV = +10 140 LSBWLG -3-dB Bandwidth SSBWHG 1700 MHz GF0.1dB 0.1-dB gain flatness VOUT = 2 VPP 120 MHz LPD Linear phase deviation DC to 100 MHz 0.09 deg DG Differential gain DP Differential phase RL =150 , 3.58 MHz 0.024% RL =150 , 4.43 MHz 0.021% RL = 150 , 3.58 MHz 0.004 RL = 150 , 4.43 MHz 0.007 deg TIME DOMAIN RESPONSE tR Rise time tF Fall time OS Overshoot 2-V Step, TRS 0.87 2-V Step, TRL 0.77 6-V Step, TRS 1.70 6-V Step, TRL 1.70 2-V Step ns ns 0% SR Slew rate 6 VPP, 40% to 60% Ts Settling time to 0.1% 2-V Step (4) 3100 V/s 13.4 ns DISTORTION AND NOISE RESPONSE 2 VPP, 5 MHz (5) (SOT-23) HD2L HD2 2nd Harmonic distortion HD2H HD3L HD3 -87 2VPP, 20 MHz (5) (SOT-23) -79 2VPP, 20 MHz (5) (SOIC) -72 2VPP, 60 MHz (5) (SOT-23) -63 2VPP, 60 MHz (5) (SOIC) -64 2VPP, 5 MHz (5) (SOT-23) -96 2VPP, 5 MHz 3rd Harmonic distortion HD3H -100 2 VPP, 5 MHz (5) (SOIC) (5) (SOIC) dBc dBc dBc dBc -98 2VPP, 20 MHz (5) (SOT-23) -88 2VPP, 20 MHz (5) (SOIC) -82 2VPP, 60 MHz (5) (SOT-23) -70 2VPP, 60 MHz (5) (SOIC) -65 dBc dBc OIM3 IMD -67 dBc VN Input referred voltage noise >1 MHz 1.83 nV/Hz IN Input referred inverting noise current >1 MHz 18.5 pA/Hz INN Input referred non-inverting noise current >1 MHz 3.0 pA/Hz SNF Total input noise floor >1 MHz -158 dBm1Hz INV Total integrated input noise 1 MHz to 150 MHz (1) (2) (3) (4) (5) 75 MHz, PO = 10dBm/ tone 35 V Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise specified. All limits are ensured by testing or statistical analysis. Typical numbers are the most likely parametric norm. Slew Rate is the average of the rising and falling edges. Harmonic distortion is strongly influenced by package type (SOT-23 or SOIC). See Application Note section under Harmonic Distortion for more information. Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 5 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com Electrical Characteristics (continued) at AV = 2, VS = 5 V, RL = 100 , RF = 237 (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN (2) TYP (3) MAX (2) UNIT STATIC, DC PERFORMANCE 1.0 VIO Input offset voltage DVIO Input offset voltage average See (6) drift IBN Input bias current Non-Inverting (7) DIBN Input bias current average drift Non-Inverting (6) IBI Input bias current Inverting (7) DIBI Input bias current average drift Inverting (6) PSRR Power supply rejection ratio DC CMRR Common mode rejection ration DC ICC Supply current RL = -40 TJ 85 4.5 6.0 -13 -6 -40 TJ 85 V/C -15 -21 +40 -8 -40 TJ 85 30 -10 -40 TJ 85 52 dB 48 dB 44 11.0 -40 TJ 85 12.5 10.0 A nA/C 45 45 -40 TJ 85 A nA/C 34 47 mV 16.1 17.5 mA MISCELLANEOUS PERFORMANCE RIN Input resistance Non-Inverting 1.4 CIN Input capacitance Non-Inverting 1.6 pF ROUT Output resistance Closed Loop 30 m VOL Output voltage range RL = 100 CMIR Input voltage range Common Mode IO Output current (6) (7) 6 3.3 -40 TJ 85 3.5 3.2 1.9 2.2 50 80 M V V mA Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Negative input current implies current flowing out of the device. Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 6.6 Typical Characteristics TA = 25C, VS = 5 V, RL = 100 , Rf = 237 (unless otherwise noted) 150 AV = +1 GAIN AV = +2 -1 0 50 -1 -50 AV = +4 -4 -100 -180 -230 -3 AV = -4 -4 AV = +2 -5 PHASE -2 Gain (dB) 0 -3 AV = -2 -80 -130 AV = +4 -2 -30 AV = -1 GAIN Phase () Gain (dB) PHASE 1 100 -150 -5 -200 -6 Phase () 1 0 -280 -330 AV = -10 AV = +1 -6 -380 AV = +10 -7 1M V0 = 2 Vpp -7 1M -250 1G 10M 100M Frequency (Hz) -430 1G 100M Frequency (Hz) RF = 237 RL = 100 VOUT = 2 VPP Figure 1. Non-Inverting Frequency Response 1 10M RL = 100 RF = 237 Figure 2. Inverting Frequency Response 1 GAIN 150 GAIN 0 100 : 0 100 -1 -1 50 PHASE -4 0 -5 -54 -6 -108 -7 -162 100M 1G -50 -4 -100 1 k: 1 k: -5 -150 100 : -216 -270 10G -7 -200 50 : 0 200M Frequency (Hz) VOUT = 0.5 VPP 0 50 : -3 -6 -8 -9 10M -2 Gain (dB) -3 Phase () PHASE Phase () Gain (dB) -2 400M 600M 800M -250 1G Frequency (Hz) RF = 232 AV = 2 Figure 3. Small Signal Bandwidth 1 AV = 2 RF = 237 VO = 2 VPP Figure 4. Frequency Response for Various RLs, AV = 2 150 1.5 GAIN 0 100 -1 50 1 50 : -3 0.5 0 -50 -4 VOUT (V) 1 k: Phase () Gain (dB) PHASE -2 -100 50 : -5 -0.5 AV = -2 -1 -200 100 : -7 100M 0 -150 -6 0 AV = +2 200M 300M 400M -250 500M -1.5 0 Frequency (Hz) AV = 4 VO = 2 VPP 2 4 6 8 10 12 14 Time (ns) RF = 237 VO = 2 VPP Figure 5. Frequency Response for Various RLs, AV = 4 RL = 100 Figure 6. Step Response, 2 VPP Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 7 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com Typical Characteristics (continued) TA = 25C, VS = 5 V, RL = 100 , Rf = 237 (unless otherwise noted) 4 1 3 2 0.1 Settling Error (%) VOUT (V) 1 0 -1 -2 0.01 -3 -4 0.001 0 10 20 30 40 50 1 60 10 AV = 2 RL = 100 VOUT = 6 VPP Figure 8. Percent Settling vs Time -40 -50 HD2, RL = 1 k: HD2, RL = 100 : -75 -80 HD3, RL = 100 : PS (dBc) HD (dBc) -65 -70 -85 -70 -80 -90 -90 -95 HD3, RL = 1 k: -100 -105 1M 50 MHz -100 25 MHz 10M Frequency (Hz) 2 VPP -110 -5 100M 100 -3 -1 1 3 RL = 100 AV = 2 -50 25 80 60MHz -60 15 50 0.1% SETTLING 40 RS 10 30 20 -80 -90 5 -100 10 0 1 10 100 1k -110 -10 0 10k 10MHz 5MHz -5 0 5 10 15 20 POUT (dBm) CL (pF) AV = -1 20MHz -70 HD (dBc) 70 Settling Time (ns) 20 60 RF = 237 Figure 10. 2 Tone 3rd Order Spurious Level (SOIC Package) 0.05% SETTLING 90 5 Test Tone Power at 50 : Load (dBm) RF = 237 AV = 2 Figure 9. Harmonic Distortion vs Load and Frequency (SOIC Package) RS (:) 75 MHz -60 -60 AV = 2 RL = 1 k Figure 11. RS and Settling Time vs CL 8 1k RL = 100 Figure 7. Step Response, 6 VPP -40 -45 -50 -55 100 Time (ns) Time (ns) RF = 237 RL = 100 Figure 12. HD2 vs Output Power (Across 100 ) (SOIC Package) Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 Typical Characteristics (continued) TA = 25C, VS = 5 V, RL = 100 , Rf = 237 (unless otherwise noted) -50 0.5 UNIT 1 60 MHz 0 -60 -0.5 -70 VOS (mV) HD (dBc) -1 20 MHz -80 -90 -1.5 -2 UNIT 2 -2.5 -100 10 MHz UNIT 3 5 MHz -3 -110 -3.5 -120 -10 -4 -5 0 5 10 15 20 -40 -15 POUT (dBm) RF = 237 AV = 2 10 35 60 85 110 135 TEMPERATURE (C) RL = 100 Figure 13. HD3 vs Output Power (Across 100 ) (SOIC Package) Figure 14. Input Offset for 3 Representative Units 10 -4 UNIT 3 8 -5 6 -7 2 0 IBN (A) IBI (A) UNIT 3 -6 4 UNIT 2 -2 UNIT 2 -8 -9 UNIT 1 -4 -10 -6 UNIT 1 -11 -8 -10 -40 -15 10 35 60 85 110 -12 -40 135 -15 TEMPERATURE (C) 10 35 60 85 TEMPERATURE (C) 110 135 Figure 16. Non-Inverting Input Bias for 3 Representative Units Figure 15. Inverting Input Bias for 3 Representative Units 15 70 1000 60 INVERTING CURRENT NON-INVERTING CURRENT 10 5 50 -5 - PSRR 40 -15 CMRR 30 -25 20 20 Log (RO) 100 CMRR/PSRR (dB) Hz) NOISE CURRENT (pA/ NOISE VOLTAGE (nV/ Hz) + PSRR -35 RO 10 VOLTAGE -45 1 100 1k 10k 100k 1M 0 1k 10M FREQUENCY (Hz) 10k VS = 5 V Figure 17. Noise 100k 1M Frequency (Hz) 10M -55 100M RL = 100 Figure 18. CMRR, PSRR, ROUT Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 9 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com Typical Characteristics (continued) TA = 25C, VS = 5 V, RL = 100 , Rf = 237 (unless otherwise noted) 120 220 110 200 100 180 90 160 0.006 0.03 0.004 0.02 70 120 60 100 PHASE 50 60 30 40 20 100k 1M 10M 100M -0.002 DG -0.004 -0.02 20 10k 0 0 -0.01 80 40 0.002 0.01 -0.03 -1.5 -1.2 -0.9 -0.6 -0.3 0 1G Frequency (Hz) VS = 5 V DP () 140 DG (%) MAG 80 Phase () Gain (dB) DP -0.006 0.3 0.6 0.9 1.2 1.5 VOUT (V) RL = 100 RF = 237 Figure 19. Transimpedance RL = 150 Figure 20. DG/DP (NTSC) 0.009 0.03 0.006 0.02 DP 0.003 0 0 -0.003 -0.01 -0.02 DP () DG (%) 0.01 DG -0.03 -1.5 -1.2 -0.9 -0.6 -0.3 0 -0.006 -0.009 0.3 0.6 0.9 1.2 1.5 VOUT (V) RF = 237 RL = 150 Figure 21. DG/DP (PAL) 10 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 7 Detailed Description 7.1 Overview The LMH6702 has been optimized for exceptionally low harmonic distortion while driving very demanding resistive or capacitive loads. Generally, when used as the input amplifier to very high speed flash ADCs, the distortions introduced by the converter will dominate over the low LMH6702 distortions shown in Typical Characteristics. 7.2 Feature Description 7.2.1 Harmonic Distortion The capacitor CSS, shown across the supplies in Figure 24 and Figure 25, is critical to achieving the lowest 2nd harmonic distortion. For absolute minimum distortion levels, it is also advisable to keep the supply decoupling currents (ground connections to CPOS, and CNEG in Figure 24 and Figure 25) separate from the ground connections to sensitive input circuitry (such as RG, RT, and RIN ground connections). Splitting the ground plane in this fashion and separately routing the high frequency current spikes on the decoupling caps back to the power supply (similar to Star Connection layout technique) ensures minimum coupling back to the input circuitry and results in best harmonic distortion response (especially 2nd order distortion). If this layout technique has not been observed on a particular application board, designer may actually find that supply decoupling caps could adversely affect HD2 performance by increasing the coupling phenomenon already mentioned. Figure 22 shows actual HD2 data on a board where the ground plane is shared between the supply decoupling capacitors and the rest of the circuit. Once these capacitors are removed, the HD2 distortion levels reduce significantly, especially between 10 MHz to 20 MHz, as shown in Figure 22: -30 -40 CPOS & CNEG INCLUDED HD2 (dBc) -50 -60 CPOS & CNEG REMOVED -70 -80 -90 1 10 Frequency (MHz) 100 Figure 22. Decoupling Current Adverse Effect on a Board with Shared Ground Plane At these extremely low distortion levels, the high frequency behavior of decoupling capacitors themselves could be significant. In general, lower value decoupling caps tend to have higher resonance frequencies making them more effective for higher frequency regions. A particular application board which has been laid out correctly with ground returns split to minimize coupling, would benefit the most by having low value and higher value capacitors paralleled to take advantage of the effective bandwidth of each and extend low distortion frequency range. Another important variable in getting the highest fidelity signal from the LMH6702 is the package itself. As already noted, coupling between high frequency current transients on supply lines and the device input can lead to excess harmonic distortion. An important source of this coupling is in fact through the device bonding wires. A smaller package, in general, will have shorter bonding wires and therefore lower coupling. This is true in the case of the SOT-23 compared to the SOIC package where a marked improvement in HD can be measured in the SOT-23 package. Figure 23 shows the HD comparing SOT-23 to SOIC package: Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 11 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com Feature Description (continued) -60 HD2, SOIC -65 -70 HD2 (dBc) -75 HD2, SOT23 -80 -85 -90 HD3, SOIC -95 HD3, SOT23 -100 -105 -110 1 10 Frequency (MHz) 100 Figure 23. SOIC and SOT-23 Packages Distortion Terms Compared The LMH6702 data sheet shows both SOT-23 and SOIC data in Electrical Characteristics to aid in selecting the right package. Typical Characteristics shows SOIC package plots only. 7.3 Device Functional Modes 7.3.1 2-Tone 3rd Order Intermodulation Figure 10 shows a relatively constant difference between the test power level and the spurious level with the difference depending on frequency. The LMH6702 does not show an intercept type performance, (where the relative spurious levels change at a 2X rate versus the test tone powers), due to an internal full power bandwidth enhancement circuit that boosts the performance as the output swing increases while dissipating negligible quiescent power under low output power conditions. This feature enhances the distortion performance and full power bandwidth to match that of much higher quiescent supply current parts. 7.3.2 DC Accuracy and Noise The example in Equation 1 shows the output offset computation equation for the non-inverting configuration using the typical bias current and offset specifications for AV = 2: Output Offset: VO = (IBN * RIN VIO) (1 + RF/RG) IBI * RF where * RIN is the equivalent input impedance on the non-inverting input. (1) Example computation for AV = +2, RF = 237, RIN = 25: VO = (6 A x 25 1mV) (1 + 237/237) 8 A x 237 = 4.20 mV (2) A good design, however, should include a worst case calculation using min/max numbers in the data sheet tables, in order to ensure worst case operation. Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in Application Note OA--07, Current Feedback Op Amp Applications Circuit Guide (SNOA365). The two input bias currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly done for matched input bias current devices). The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage and the two input noise currents, the output noise is developed through the same gain equations for each term but combined as the square root of the sum of squared contributing elements. See Application Note OA-12, Noise Analysis for Comlinear Amplifiers (SNOA375) for a full discussion of noise calculations for current feedback amplifiers. 12 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the feedback resistor value. The LMH6702 is optimized for use with a 237- feedback resistor. Using lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. 8.2 Typical Application 8.2.1 Feedback Resistor The LMH6702 achieves its excellent pulse and distortion performance by using the current feedback topology. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the feedback resistor value. The LMH6702 is optimized for use with a 237- feedback resistor. Using lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. +5V 6.8F AV = 1 +RF/RG = VOUT/VIN .01F VIN 3 VOUT 6 CSS 0.1F RIN 7 CPOS + LMH6702 2 4 CNEG RF .01F RG 6.8F -5V Figure 24. Recommended Non-Inverting Gain Circuit +5V 6.8F RF .01F 3 25: AV = = VOUT VIN 7 CPOS + VOUT 6 CSS 0.1F RG LMH6702 2 VIN RG 4 CNEG .01F RT 6.8F -5V RF SELECT RT TO YIELD DESIRED RIN = RT||RG Figure 25. Recommended Inverting Gain Circuit Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 13 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com Typical Application (continued) 8.2.2 Design Requirements The exceptional performance and uniquely targeted superior technical specifications of the LMH6702 make it a natural choice for high speed data acquisition applications as a front end amplifier driving the input of a high performance ADC. Of these specifications, the following can be discussed in more detail: 1. A bandwidth of 1.7 GHz and relative insensitivity of bandwidth to closed loop gain (characteristic of Current Feedback architecture when compared to the traditional voltage feedback architecture) as shown in Figure 1. 2. Ultra-low distortion approaching -87 dBc at the lower frequencies and exceptional noise performance (see Figure 9 and Figure 17). 3. Fast settling in less than 20 ns (see Figure 27). As the input of an ADC could be capacitive in nature and could also alternate in capacitance value during a typical acquisition cycle, the driver amplifier (LMH6702 in this case) should be designed so that it avoids instability, peaking, or other undesirable artifacts. For Capacitive Load Drive, see Figure 26, which shows a typical application using the LMH6702 to drive an ADC. ADC + RS LMH6702 - CIN Figure 26. Input Amplifier to ADC 8.2.3 Detailed Design Procedure The series resistor, RS, between the amplifier output and the ADC input is critical to achieving best system performance. This load capacitance, if applied directly to the output pin, can quickly lead to unacceptable levels of ringing in the pulse response. Figure 27 in Application Curve (RS and Settling Time vs CL) is an excellent starting point for selecting RS. The value derived in that plot minimizes the step settling time into a fixed discrete capacitive load with the output driving a very light resistive load (1 k). Sensitivity to capacitive loading is greatly reduced once the output is loaded more heavily. Therefore, for cases where the output is heavily loaded, RS value may be reduced. The exact value may best be determined experimentally for these cases. In applications where the LMH6702 is replacing the CLC409, care must be taken when the device is lightly loaded and some capacitance is present at the output. Due to the much higher frequency response of the LMH6702 compared to the CLC409, there could be increased susceptibility to low value output capacitance (parasitic or inherent to the board layout or otherwise being part of the output load). As already mentioned, this susceptibility is most noticeable when the LMH6702's resistive load is light. Parasitic capacitance can be minimized by careful lay out. Addition of an output snubber R-C network will also help by increasing the high frequency resistive loading. Referring back to Figure 26, it must be noted that several additional constraints should be considered in driving the capacitive input of an ADC. There is an option to increase RS, band-limiting at the ADC input for either noise or Nyquist band-limiting purposes. However, increasing RS too much can induce an unacceptably large input glitch due to switching transients coupling through from the convert signal. Also, CIN is oftentimes a voltage dependent capacitance. This input impedance non-linearity will induce distortion terms that will increase as RS is increased. Only slight adjustments up or down from the recommended RS value should therefore be attempted in optimizing system performance. 14 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 Typical Application (continued) 8.2.4 Application Curve 100 25 0.05% SETTLING 90 80 RS (:) 60 15 50 0.1% SETTLING 40 10 RS 30 20 Settling Time (ns) 20 70 5 10 0 1 10 100 1k 0 10k CL (pF) AV = -1 RL = 1 k Figure 27. RS and Settling Time vs CL 9 Power Supply Recommendations The LMH6702 can operate off a single supply or with dual supplies as long as the input CM voltage range (CMIR) has the required headroom to either supply rail. Supplies should be decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground plane close to device sensitive pins such as the inputs. 10 Layout 10.1 Layout Guidelines Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations. See Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367). Texas Instruments suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. See Table 1 for details. The LMH6702 evaluation board(s) is a good example of high frequency layout techniques as a reference. General high-speed, signal-path layout suggestions include: * Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs. However, open up both ground and power planes around the capacitive sensitive input and output device pins as shown in Figure 28. After the signal is sent into a resistor, parasitic capacitance becomes more of a bandlimiting issue and less of a stability issue. * Use good, high-frequency decoupling capacitors (0.1 F) on the ground plane at the device power pins as shown in Figure 28. Higher value capacitors (2.2 F) are required, but may be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors. * When using differential signal routing over any appreciable distance, use microstrip layout techniques with matched impedance traces. * The input summing junction is very sensitive to parasitic capacitance. Connect any Rf, and Rg elements into the summing junction with minimal trace length to the device pin side of the resistor, as shown in Figure 29. The other side of these elements can have more trace length if needed to the source or to ground. Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 15 LMH6702 SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 www.ti.com 10.2 Layout Example Figure 28. LMH6702 Evaluation Board Layer 1 Figure 29. LMH6702 Evaluation Board Layer 2 Table 1. Evaluation Board Comparison 16 DEVICE PACKAGE EVALUATION BOARD PART NUMBER LMH6702MF SOT-23 LMH730216 LMH6702MA SOIC LMH730227 Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 LMH6702 www.ti.com SNOSA03H - NOVEMBER 2002 - REVISED MAY 2016 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation For related documentation, see the following: * Absolute Maximum Ratings for Soldering (SNOA549) * Current Feedback Op Amp Applications Circuit Guide, Application Note OA--07 (SNOA365) * Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, Application Note OA-15 (SNOA367) * Noise Analysis for Comlinear Amplifiers, Application Note OA-12 (SNOA375) * Semiconductor and IC Package Thermal Metrics (SPRA953) 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks VIP10, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2002-2016, Texas Instruments Incorporated Product Folder Links: LMH6702 17 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMH6702MA NRND SOIC D 8 95 Non-RoHS & Green Call TI Call TI -40 to 85 LMH67 02MA LMH6702MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH67 02MA LMH6702MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH67 02MA LMH6702MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A83A LMH6702MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A83A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMH6702MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMH6702MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMH6702MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6702MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMH6702MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMH6702MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 0.90 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI's products are provided subject to TI's Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI's provision of these resources does not expand or otherwise alter TI's applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2021, Texas Instruments Incorporated