IRFZ44ESPbF
IRFZ44ELPbF
HEXFET® Power MOSFET
PD - 95572
07/19/04
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V48
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V34 A
IDM Pulsed Drain Current 192
PD @TC = 25°C Power Dissipation 110 W
Linear Derating Factor 0.71 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy220 mJ
IAR Avalanche Current29 A
EAR Repetitive Avalanche Energy11 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torque, 6-32 or M3 srew 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.4
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62
Thermal Resistance
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lAdvanced Process Technology
lSurface Mount (IRFZ44ES)
lLow-profile through-hole (IRFZ44EL)
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
lLead-Free
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve extremely low on-resistance per silicon area.
This benefit, combined with the fast switching speed and ruggedized device
design that HEXFET Power MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of accommodating die
sizes up to HEX-4. It provides the highest power capability and the lowest
possible on-resistance in any existing surface mount package. The D2Pak is
suitable for high current applications because of its low internal connection
resistance and can dissipate up to 2.0W in a typical surface mount application.
The through-hole version (IRFZ44EL) is available for low-profile applications.
Description
VDSS = 60V
RDS(on) = 0.023Ω
ID = 48A
2
D Pa k
TO-262
S
D
G
IRFZ44ES/LPbF
2www.irf.com
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode)––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 29A, VGS = 0V
trr Reverse Recovery Time ––– 69 104 ns TJ = 25°C, IF = 29A
Qrr Reverse Recovery Charge ––– 177 266 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
48
192
A
Starting TJ = 25°C, L = 520µH
RG = 25Ω, IAS = 29A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
ISD ≤ 29A, di/dt ≤ 320A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Uses IRFZ44E data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended soldering techniques refer to application note #AN-994.
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 ––– ––– V VGS = 0V, ID = 250µA
DV(BR)DSS/DTJBreakdown Voltage Temp. Coefficient ––– 0.063 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.023 ΩVGS = 10V, ID = 29A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 15 ––– ––– S VDS = 30V, ID = 29A
––– ––– 25 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 48V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge ––– ––– 60 ID = 29A
Qgs Gate-to-Source Charge ––– ––– 13 nC VDS = 48V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 23 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 12 ––– VDD = 30V
trRise Time ––– 60 ––– ID = 29A
td(off) Turn-Off Delay Time ––– 70 ––– RG = 15Ω
tfFall Time ––– 70 ––– RD = 1.1Ω, See Fig. 10
Between lead,
––– ––– and center of die contact
Ciss Input Capacitance ––– 1360 ––– VGS = 0V
Coss Output Capacitance ––– 420 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 160 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
IGSS
ns
IDSS Drain-to-Source Leakage Current
nH
7.5
LSInternal Source Inductance
IRFZ44ES/LPbF
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1
10
100
1000
0.1 1 10 100
20µs PULSE WIDTH
T = 25 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drai n-to-S ource Voltag e (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
1
10
100
1000
0.1 1 10 100
20µs PULSE WIDTH
T = 175 C
J°
TOP
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
V , Drain-to-Source Voltage (V)
I , Drain-to-Source Current (A)
DS
D
4.5V
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
1000
4 5 6 7 8 9 10
V = 25V
20µs PULSE WIDTH
DS
V , Gate-to-Source Voltage (V)
I , Drain-to-Source Current (A)
GS
D
T = 175 C
J°
T = 25 C
J°
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
2.5
T , Junction Temperature ( C )
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
48A
Fig 4. Normalized On-Resistance
Vs. Temperature
IRFZ44ES/LPbF
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Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1
10
100
1000
1 10 100 100
0
OPERATI O N I N THI S AREA LIMI TED
BY RDS(on)
Sing l e Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drai n- to-Source Voltage (V)
I , Drain Current ( A)I , Drain Current ( A)
DS
D
10us
100us
1ms
10ms
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1 10 100
0
500
1000
1500
2000
2500
V , Drain-to-Source Voltage (V)
C, Capacitance (pF)
DS
V
C
C
C
=
=
=
=
0V,
C
C
C
f = 1MHz
+ C
+ C
C SHORTED
GS
iss gs gd , ds
rss gd
oss ds gd
Ciss
Coss
Crss
010 20 30 40 50 60
0
4
8
12
16
20
Q , Total Gate Charg e (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
29
V = 30V
DS
V = 48V
DS
1
10
100
1000
0.5 1.0 1.5 2.0 2.5
V ,Sour ce-t o-Drain Vol tage (V)
I , Reverse Drain C urrent (A)
SD
SD
V = 0 V
GS
T = 25 C
J°
T = 175 C
J°
IRFZ44ES/LPbF
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RD
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
VGS
RG
D.U.T.
10V
+
-
25 50 75 100 125 150 175
0
10
20
30
40
50
T , C a se Tempe rature ( C)
I , Drain Current (A)
°
C
D
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10a. Switching Time Test Circuit
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
VGS
RG
D.U.T.
10V
VDD
25 50 75 100 125 150 175
0
10
20
30
40
50
T , C a se Tempe rature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. D u ty fa c to r D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pul se Durati on ( sec)
Thermal R esponse (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRFZ44ES/LPbF
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QG
QGS QGD
V
G
Charge
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
25 50 75 100 125 150 175
0
100
200
300
400
500
Startin g T , Junction Temperature ( C)
E , Single Pul se Avalanche Energy (mJ )
J
AS
°
ID
TOP
BOTTOM
12A
21A
29A
IRFZ44ES/LPbF
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P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRFZ44ES/LPbF
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D2Pak Part Marking Information
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: "P" in assembly line
pos ition indi cates "Lead-F ree"
F530S
THIS IS AN IRF530S WITH
LO T CODE 8024
ASSEMBLE D ON WW 02, 2000
IN THE ASSE MB LY LINE "L"
AS S EMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART N UMBE
R
DATE CODE
YEAR 0 = 2000
WEE K 02
LINE L
OR
F530S
A = ASSEMBLY SI TE CODE
WEEK 02
P = DE SI GNATES L EAD-FREE
PRODUCT (OPTIONAL)
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
AS S EMB LY YEAR 0 = 2000
DATE COD E
PART NUMBER
IRFZ44ES/LPbF
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TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
ASSEMBLY
LOT CODE
RECTIFIER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
N ote: "P" in assembly line
pos ition indicates "Lead-F ree"
IN THE ASSEMBLY LINE "C" LOGO
THIS IS AN IRL3103L
LOT CODE 1789
EXAMPLE:
LINE C
DATE CODE
WEEK 19
YEAR 7 = 1997
PAR T NUMBE R
PART NUMBER
LOGO
LOT CODE
AS S E MBL Y
INTERNATIONAL
RECTIFIER
PRODU CT (OPTIONAL)
P = DES IGN AT ES LEAD- F REE
A = ASSEMBLY SITE CODE
WEEK 19
Y EAR 7 = 1997
DATE CO DE
OR
IRFZ44ES/LPbF
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D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
F
EED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTION
10.90 (. 429)
10.70 (. 421) 16. 10 ( .634 )
15. 90 ( .626 )
1.75 (.069)
1.25 (.049)
11.60 (.4 57)
11.40 (.4 49) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24. 30 ( .957
)
23. 90 ( .941
)
0.368 (.0 145)
0.342 (.0 135)
1.60 (.0 63)
1.50 (.0 59)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362
)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCL UD ES FLANGE DISTORTION @ OUTER EDGE.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 07/04
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
