V53C518165A 1M x 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH MOSEL VITELIC HIGH PERFORMANCE 50 60 Max. RAS Access Time, (tRAC) 50 ns 60 ns Max. Column Address Access Time, (tCAA) 25 ns 30 ns Min. Extended Data Out Page Mode Cycle Time, (tPC) 20 ns 25 ns Min. Read/Write Cycle Time, (tRC) 84 ns 104 ns Features Description 1MB x 16-bit organization EDO Page Mode for a sustained data rate of 50 MHz RAS access time: 50, 60 ns Dual CAS Inputs Low power dissipation Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh * Refresh Interval: 1024 cycles/16 ms Available in 42-pin 400 mil SOJ and 44/50-pin 400 mil TSOP-II Packages Single 5V 10% Power Supply TTL Interface Optional Self Refresh (V53C518165AS) * Refresh Interval: 1024 cycles/128 ms The V53C518165A is a 1048576 x 16 bit highperformance CMOS dynamic random access memory. The V53C518165A offers Page mode operation with Extended Data Output. The V53C518165A has symmetric address, 10-bit row and 10-bit column. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 16 bits, within a page, with cycle times as short as 20ns. These features make the V53C518165A ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power K T 50 60 Std. Temperature Mark 0C to 70C * * * * * Blank -40C to +85C * * * * * I V53C518165A Rev. 1.1 January 1998 1 V53C518165A MOSEL VITELIC 42-Pin Plastic SOJ PIN CONFIGURATION Top View VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 44/50-Pin Plastic TSOP-II PIN CONFIGURATION Top View VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS 511816500-02 Pin Names A0-A9 Row, Column Address Inputs Description RAS Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Lower Byte Control WE Write Enable OE Output Enable I/O1-I/O16 Data Input, Output VCC +5V Supply VSS 0V Supply NC No Connect V53C518165A Rev. 1.1 January 1998 2 Pkg. Pin Count TSOP-II T 44/50 SOJ K 42 V53C518165A MOSEL VITELIC Absolute Maximum Ratings* Symbol Parameter VN Power Supply Voltage VDQ Input/Output Voltage TBIAS TSTG Commercial Extended Units -1 to +7 -1 to +7 V -0.5 to min (VCC+0.5, 7.0) -0.5 to min (VCC+0.5, 7.0) V Temperature Under Bias -10 to +125 -65 to +135 C Storage Temperature -55 to +125 -65 to +150 C *Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* TA = 25C, VCC = 5 V 10%, VSS = 0 V, f = 1 MHz Symbol Parameter Min. Max. Unit CIN1 Address Input -- 5 pF CIN2 RAS, UCAS, LCAS, WE, OE -- 7 pF COUT Data Input/Output -- 7 pF *Note: Capacitance is sampled and not 100% tested. Block Diagram I/O1 I/O2 I/O16 *** Data In Buffer Data Out Buffer OE 16 WE LCAS UCAS 16 No. 2 Clock Generator 10 A0 Column Address Buffers (10) 10 Column Decoder A1 A2 Refresh Controller A3 Sense Amplifier I/O Gating A4 16 A5 Refresh Counter (10) A6 A7 1024 x16 10 A8 A9 RAS 10 Row Address Buffers (10) 10 Row Decoder 1024 No. 1 Clock Generator Memory Array 1024 x 1024 x 16 Voltage Down Generator VCC VCC (internal) 316516500-03 V53C518165A Rev. 1.1 January 1998 3 V53C518165A MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, tT = 2ns, unless otherwise specified. Symbol Parameter Access Time Commercial Extended Min. Max. Min. Max. Unit Test Conditions Notes ILI Input Leakage Current (any input pin) -10 10 -10 10 mA VSS VIN VCC + 0.5V 1 ILO Output Leakage Current (for High-Z State) -10 10 -10 10 mA VSS VOUT VCC+ 0.5V RAS, CAS at VIH 1 ICC1 VCC Supply Current, Operating mA tRC = tRC (min.) 50 130 200 60 115 180 2 2 mA RAS, CAS at VIH other inputs VSS mA tRC = tRC (min.) 2, 4 mA Minimum Cycle 2, 3, 4 mA tRC = tRC (min.) 2, 4 ICC2 VCC Supply Current, TTL Standby ICC3 VCC Supply Current, RAS-Only Refresh 50 130 200 60 115 180 VCC Supply Current, EDO Page Mode Operation 50 50 90 60 40 75 VCC Supply Current, during CAS-before-RAS Refresh 50 130 200 60 115 180 ICC4 ICC5 2, 3, 4 ICC6 VCC Supply Current, CMOS Standby 1.0 1.0 mA RAS VCC - 0.2 V, CAS VCC - 0.2 V other input VSS ICC7 Self Refresh (Optional) 250 250 mA CBR cycle with tRAS tRASS (min.), CAS Held Low, WE = VCC-0.2V, Address and DIN = VCC-0.2V or 0.2V VCC Power Supply Voltage 4.5 5.5 4.5 5.5 V VIL Input Low Voltage -0.5 0.8 -0.5 0.8 V 1 VIH Input High Voltage 2.4 VCC+0.5 2.4 VCC+0.5 V 1 VOL Output Low Voltage 0.4 V IOL = 4.2 mA 1 VOH Output High Voltage V IOH = -5.0 mA 1 V53C518165A Rev. 1.1 January 1998 0.4 2.4 2.4 4 1 V53C518165A MOSEL VITELIC AC Characteristics(5,6) TA = 0C to 70C, VCC = 5 V 10%, tT = 2ns, unless otherwise noted Limit Values -50 # Symbol Parameter -60 Min. Max. Min. Max. Unit Note Common Parameters 1 tRC Random read or write cycle time 84 -- 104 -- ns 2 tRP RAS precharge time 30 -- 40 -- ns 3 tRAS RAS pulse width 50 10k 60 10k ns 4 tCAS CAS pulse width 8 10k 10 10k ns 5 tASR Row address setup time 0 -- 0 -- ns 6 tRAH Row address hold time 8 -- 10 -- ns 7 tASC Column address setup time 0 -- 0 -- ns 8 tCAH Column address hold time 8 -- 10 -- ns 9 tRCD RAS to CAS delay time 12 37 14 45 ns 10 tRAD RAS to column address delay 10 25 12 30 ns 11 tRSH RAS hold time 13 -- 15 -- ns 12 tCSH CAS hold time 40 -- 50 -- ns 13 tCRP CAS to RAS precharge time 5 -- 5 -- ns 14 tT Transition time (rise and fall) 1 50 1 50 ns 15 tREF Refresh period -- 16 -- 16 ms 7 Read Cycle 16 tRAC Access time from RAS -- 50 -- 60 ns 8, 9 17 tCAC Access time from CAS -- 13 -- 15 ns 8, 9 18 tCAA Access time from column address -- 25 -- 30 ns 8,10 19 tOAC OE access time -- 13 -- 15 ns 20 tCAR Column address to RAS lead time 25 -- 30 -- ns 21 tRCS Read command setup time 0 -- 0 -- ns 22 tRCH Read command hold time 0 -- 0 -- ns 11 23 tRRH Read command hold time referenced to RAS 0 -- 0 -- ns 11 24 tCLZ CAS to output in low-Z 0 -- 0 -- ns 8 25 tOFF Output buffer turn-off delay 0 13 0 15 ns 12 26 tOEZ Output turn-off delay from OE 0 13 0 15 ns 12 27 tDZC Data to CAS low delay 0 -- 0 -- ns 13 28 tDZO Data to OE low delay 0 -- 0 -- ns 13 29 tCDD CAS high to data delay 10 -- 13 -- ns 14 30 tODD OE high to data delay 10 -- 13 -- ns 14 V53C518165A Rev. 1.1 January 1998 5 V53C518165A MOSEL VITELIC AC Characteristics (Cont'd) Limit Values -50 # Symbol Parameter -60 Min. Max. Min. Max. Unit Note Write Cycle 31 tWCH Write command hold time 8 - 10 - ns 32 tWP Write command pulse width 8 - 10 - ns 33 tWCS Write command setup time 0 - 0 - ns 34 tRWL Write command to RAS lead time 8 - 10 - ns 35 tCWL Write command to CAS lead time 8 - 10 - ns 36 tDS Data setup time 0 - 0 - ns 16 37 tDH Data hold time 8 - 10 - ns 16 15 Read-modify-Write Cycle 38 tRWC Read-write cycle time 113 - 138 - ns 39 tRWD RAS to WE delay time 64 - 77 - ns 15 40 tCWD CAS to WE delay time 27 - 32 - ns 15 41 tAWD Column address to WE delay time 39 - 47 - ns 15 42 tOEH OE command hold time 10 - 13 - ns EDO Page Mode Cycle 43 tHPC EDO page mode cycle time 20 - 25 - ns 44 tCP CAS precharge time 8 - 10 - ns 45 tCPA Access time from CAS precharge - 27 - 32 ns 46 tCOH Output data hold time 5 - 5 - ns 47 tRASP RAS pulse width in EDO page mode 50 200k 60 200k ns 48 tRHPC CAS precharge to RAS Delay 27 - 32 - ns 49 tOES OE setup time prior to CAS 5 - 5 - ns EDO Page Mode Read-Modify-Write Cycle 50 tPRWC EDO page mode read-write cycle time 58 - 68 - ns 51 tCPWD CAS precharge to WE 41 - 49 - ns CAS-before-RAS Refresh Cycle 52 tCSR CAS setup time 10 - 10 - ns 53 tCHR CAS hold time 10 - 10 - ns 54 tRPC RAS to CAS precharge time 5 - 5 - ns 55 tWRP Write to RAS precharge time 10 - 10 - ns 56 tWRH Write hold time referenced to RAS 10 - 10 - ns 35 - 40 - ns CAS-before-RAS Counter Test Cycle 57 tCPT CAS precharge time (CAS-before-RAS counter test cycle) V53C518165A Rev. 1.1 January 1998 6 7 V53C518165A MOSEL VITELIC Limit Values -50 # Symbol Parameter -60 Min. Max. Min. Max. Unit Note -- 128 -- 128 ms 100K -- 100K -- ns 17 Optional Self Refresh 58 tREF Self Refresh period 59 tRASS RAS pulse width 60 tRPS RAS precharge time 95 -- 110 -- ns 17 61 tCHS CAS hold time -50 -- -50 -- ns 17 V53C518165A Rev. 1.1 January 1998 7 V53C518165A MOSEL VITELIC Notes: 1. All voltage are referenced to VSS. 2. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during an EDO page mode cycle. 5. An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 2ns. 7. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with the specified current load and 100pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tCAA, tCPA, tOAC, tCAC is measured from tristate. 9. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA. 11. Either tRCH or tRRH must be satisfied for a read cycle. 12. tOFF (max.), tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13. Either tDZC or tDZO must be satisfied. 14. Either tCDD or tODD must be satisfied. 15. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. V53C518165A Rev. 1.1 January 1998 8 V53C518165A MOSEL VITELIC Waveforms of Read Cycle t RC t RAS t RP VIH RAS VIL t CSH t RCD UCAS LCAS t CRP t RSH VIH t CAS VIL t RAD t ASR t CAR t CAH t ASC t ASR VIH Address VIL Column Row Row t RCH t RAH t RCS t RRH VIH WE VIL t CAA t OAC VIH OE VIL t DZC I/O (Inputs) I/O (Outputs) t CDD t ODD t DZO VIH VIL t CAC t CLZ VOH Hi Z t OFF t OEZ Valid Data Out Hi Z VOL t RAC "H" or "L" 511816502-04 V53C518165A Rev. 1.1 January 1998 9 V53C518165A MOSEL VITELIC Waveforms of Write Cycle (Early Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD UCAS LCAS tRSH VIH tCRP tCAS VIL tRAD tASR tCAR tCAH tASC tASR . VIH Address Column Row Row VIL tCWL tRAH tWCS tWP VIH WE VIL tWCH tRWL VIH OE VIL tDS I/O (Inputs) I/O (Outputs) tDH VIH Valid Data In VIL VOH Hi Z VOL "H" or "L" 511816502-05 V53C518165A Rev. 1.1 January 1998 10 V53C518165A MOSEL VITELIC Waveforms of Write Cycle (OE Controlled Write) tRC tRAS tRP VIH RAS VIL tCSH tRCD UCAS LCAS tCRP tRSH VIH tCAS VIL t RAD t ASR t CAR t CAH t ASC t ASR VIH Address Row Column Row VIL tCWL tRWL t RAH tWP VIH WE VIL tOEH VIH OE VIL tODD tDH tDZO tDZC I/O (Inputs) tOEZ tDS VIH Valid Data VIL tCLZ tOAC VOH I/O (Outputs) Hi-Z Hi-Z VOL 511816502-06 "H" or "L" V53C518165A Rev. 1.1 January 1998 11 V53C518165A MOSEL VITELIC Waveforms of Read-Write (Read-Modify-Write) Cycle tRWC tRAS tRP VIH VIL RAS tCSH tRCD UCAS LCAS tRSH tCAS VIH tCRP VIL tRAH tCAH tASR tASC tASR VIH Address Row Column Row VIL tCWL tAWD tRAD tCWD tRWL tRWD tWP VIH WE VIL tCAA tRCS tOAC tOEH VIH OE VIL tDS tDZO tDZC tDH VIH I/O (Inputs) Valid Data in VIL tCLZ tODD tCAC tOEZ I/O (Outputs) VOH Data Out VOL t RAC "H" or "L" V53C518165A Rev. 1.1 January 1998 511816502-07 12 V53C518165A MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle t RP tRASP VIH tRCD RAS tRHPC VIL tRSH tPC tCRP UCAS LCAS tCAS tCAS tCP tCRP tCAS VIH VIL tCSH tASR tCAR tRAH tASC tCAH tASC tCAH tASC tCAH Column 2 Column N VIH Address Row Column 1 VIL tRAD tRRH tRCS tRCH VIH WE VIL tCAC tCAA tOES tCPA tCAC tCAA tCPA tOFF tOAC VOH OE VOL tRAC tOEZ tCAA tCOH tCAC I/O (Output) tCOH tCLZ VIH Data Out 1 VIL Data Out 2 Data Out N 511816502-08 "H" or "L" V53C518165A Rev. 1.1 January 1998 13 V53C518165A MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle (OE Control) tRP tRASP VIH RAS tRCD tRHPC VIL tRSH tPC tCRP tCAS tCAS tCAS tCP tCRP VIH UCAS LCAS VIL tCSH tASR tCAR tRAH tASC tCAH tASC tCAH tASC tCAH VIH Address Row Column N Column 2 Column 1 VIL tRAD tRRH tRCH tRCS VIH WE tCAC tCAA VIL tOES tCAC tCAA tCPA tOEHC tCPA tOFF tOEHC tOAC VOH OE VOL tOEP tRAC tOAC tOEP tOAC tCAA tOEZ tOEZ tCAC tOEZ tCLZ I/O (Output) VIH Data Out 1 VIL Data Out 2 Data Out N 511816502-09 "H" or "L" V53C518165A Rev. 1.1 January 1998 14 V53C518165A MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle (WE Control) tRP tRASP VIH RAS tRHPC tRCD VIL tRSH tPC tCRP UCAS LCAS tCAS tCP tCAS tCRP tCAS VIH VIL tCSH tASR tCAR tRAH tASC tASC tCAH tCAH tASC tCAH VIH Address Row Column N Column 2 Column 1 VIL tRAD tCAA tCAA tRRH tRCH tRCS tRCH tRCS tRCS tRCH VIH WE VIL tWPZ tWPZ tCAC tCAC tOES tCPA tCPA tOFF tOAC VOH OE VOL tCAR tOEZ tCAA tCAC I/O (Output) tWEZ tCLZ VIH Data Out 1 VIL Data Out 2 Data Out N 511816502-10 "H" or "L" V53C518165A Rev. 1.1 January 1998 tWEZ 15 V53C518165A MOSEL VITELIC Waveforms of EDO Page Mode Early Write Cycle tRP tRASP VIH tRCD tRHPC RAS VIL tRSH tPC tCRP UCAS LCAS tCAS tCAS tCAS tCP tCRP VIH VIL tCAR tCSH tASR tRAH tASC tCAH tASC tASC tCAH tCAH VIH Address VIL Row Addr Column 1 Column 2 Column N tRAD tRWL tCWL tWCS tWCH tCWL tWCS tWCH tWP VIH tCWL tWCS tWCH tWP tWP WE VIL VOH OE VOL tDS tDH tDS tDH tDS tDH VIH I/O (Input) Data In 1 Data In 2 VIL "H" or "L" V53C518165A Rev. 1.1 January 1998 Data In N 511816502-11 16 V53C518165A MOSEL VITELIC Waveforms of EDO Page Mode Late Write Cycle tRP tRASP VIH tRCD RAS VIL tRSH tPC tCRP tCAS tCAS tCP tCP tCRP tCAS VIH UCAS LCAS VIL tCSH tASR tCAR tRAH tASC tCAH tASC tCAH tASC tCAH Column 2 Column N VIH Address Row Column 1 VIL tRAD tCWL tCWL tCWL tRWL tRCS tRCS tRCS VIH WE VIL tWP tWP tWP tOEH tOEH tOEH VOH OE VOL tODD tDS tDH tODD tDS tDH tDS tDH tODD I/O (Input) VIH Data In 2 Data In 1 VIL 511816502-12 "H" or "L" V53C518165A Rev. 1.1 January 1998 Data In N 17 V53C518165A Rev. 1.1 January 1998 18 I/O (Outputs) I/O (Inputs) OE WE Address UCAS LCAS RAS VOL VOH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH tASR Row tRAH tRAC tCAH tCAS tCAC tCLZ tDS tDH tOEH tCLZ tCPA tCAA tDZC tOAC Data Out tWP tDS tDH Data In tODD tOEZ tAWD tPRWC tCAS tCPWD tCWD tCAH Column tASC tCP tCWL tWP Data In tOEZ tODD Data Out tAWD tCAA tOAC tRWD tCWD Column tASC tDZO tDZC tRCS tRAD tRCD tCSH tRASP tOAC tCAC tCLZ tCAR tOEZ tDS tDH tRWL tCWL tOEH tWP Data In tODD Data Out tAWD tCPWD tCWD tCPA tCAA tOEH tDZC tCWL Column tASC tCAH tCAS tRSH tCRP 511816502-13 Row tASR tRP MOSEL VITELIC V53C518165A Waveforms of EDO Page Mode Read-Modify-Write Cycle V53C518165A MOSEL VITELIC Waveforms of RAS Only Refresh Cycle tRC tRAS tRP VIH RAS VIL tRPC UCAS LCAS tCRP VIH VIL tRAH tASR tASR VIH Address Row Row VIL I/O (Outputs) VOH HI-Z VOL 511816502-14 "H" or "L" V53C518165A Rev. 1.1 January 1998 19 V53C518165A MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Cycle tRC tRP tRAS tRP VIH RAS VIL tRPC tCP UCAS LCAS tCRP tCSR tRPC tCHR VIH VIL tWRP tWRH VIH WE VIL tOEZ VIH OE VIL tCDD I/O (Inputs) VIH VIL tODD I/O (Outputs) VOH HI-Z VOL tOFF 511816502-15 "H" or "L" V53C518165A Rev. 1.1 January 1998 20 V53C518165A MOSEL VITELIC Waveforms of CAS-before-RAS Self Refresh Cycle (Optional) tRP tRASS tRPS VIH RAS VIL tRPC tCRP tCSR tCHS tCP UCAS LCAS VIH VIL tWRP tWRH VIH WE VIL VIH OE VIL tCDD I/O (Inputs) VIH VIL tODD tOEZ I/O (Outputs) VOH HI-Z VOL tOFF 511816502-15 "H" or "L" V53C518165A Rev. 1.1 January 1998 21 V53C518165A MOSEL VITELIC Waveforms of Hidden Refresh Read Cycle tRC tRC tRP tRAS VIH tRP tRAS RAS VIL tRSH tRCD tCHR UCAS LCAS tCRP VIH VIL tRAD tWRP tASC tRAH tASR tWRH tCAH tASR VIH Address Column Row Row VIL tRRH tRCS VIH WE VIL tCAA tOAC VIH OE VIL tDZC tCDD tDZO tODD I/O (Inputs) VIH VIL tCAC tOFF tCLZ tOEZ tRAC I/O (Outputs) VOH Valid Data Out VOL "H" or "L" V53C518165A Rev. 1.1 January 1998 HI-Z 511816502-16 22 V53C518165A MOSEL VITELIC Waveforms of Hidden Refresh Early Write Cycle tRC tRC tRP tRAS VIH RAS tRAS tRP VIL tRCD tRSH tCHR tCRP VIH UCAS LCAS tRAD VIL tRAH tASC tASR tASR tCAH VIH Address Row Row Column VIL tWCS tWRP tWCH tWRH tWP VIH WE VIL tDS I/O (Input) I/O (Output) tDH VIH Valid Data VIL VOH HI-Z VOL 511816502-17 "H" or "L" V53C518165A Rev. 1.1 January 1998 23 V53C518165A MOSEL VITELIC Notes: V53C518165A Rev. 1.1 January 1998 24 V53C518165A MOSEL VITELIC Notes: V53C518165A Rev. 1.1 January 1998 25 V53C518165A MOSEL VITELIC Notes: V53C518165A Rev. 1.1 January 1998 26 V53C518165A MOSEL VITELIC Package Diagrams 42-Pin 400 mil SOJ 0.0170.004 [0.43 0.1] .441 -0.006 [11.2 -0.15](1) 0.3700.010 [9.40.25] +0.005 0.008 -0.002 +0.12 0.2 -0.05 0.145 [3.68] MAX 0.045 [1.15] MIN 0.81 [.032] MAX .406 -0.012(1) [10.3 - 0.3] 21 0.088 0.004 [2.24 0.1] 1 .406 -0.012 [10.3 -0.3] 22 .441 0.006 [11.2 0.15] 1.08 -0.010 [27.41 -0.25] 42 0.004 [0.1] 0.05 [1.27] 1.0 [25.4] (1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side. Unit in inches [mm] 44/50-Pin 400 mil TSOP-II 0.039 0.002 [1 0.05] 0.0040.002 [0.10.05] 0.031 [0.8] 0.016 +0.002 -0.004 0.004 [0.1] 0.008 [0.2] M 44x 50 40 36 1 11 15 +0.08 0.15 -0.03 0.0200.004 [0.5 0.1] 26 25 1 Unit in inches [mm] 0.8250.005 [20.950.13] Does not include plastic or metal protrusion of 0.010 [0.25] max. per side V53C518165A Rev. 1.1 January 1998 +0.003 0.006 -0.001 0.4630.008 [11.76 0.2] 0.4 +0.05 -0.1 1 0.047 Max [1.2 Max] 0.4 0.005 [10.16 0.13] 27 MOSEL VITELIC WORLDWIDE OFFICES V53C518165A U.S.A. TAIWAN JAPAN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 011-81-43-299-6000 FAX: 011-81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN CENTRAL & SOUTHEASTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 (c) Copyright 1998, MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC 1/98 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461