MOSEL VITELIC
1
V53C518165A
1M x 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
V53C518165A Rev. 1.1 January 1998
HIGH PERFORMANCE 50 60
Max. RAS Access Time, (t
RAC
) 50 ns 60 ns
Max. Column Address Access Time, (t
CAA
) 25 ns 30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
) 20 ns 25 ns
Min. Read/Write Cycle Time, (t
RC
) 84 ns 104 ns
Features
■
1MB x 16-bit organization
■
EDO Page Mode for a sustained data rate
of 50 MHz
■
RAS access time: 50, 60 ns
■
Dual CAS Inputs
■
Low power dissipation
■
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
• Refresh Interval: 1024 cycles/16 ms
■
Available in 42-pin 400 mil SOJ and
44/50-pin 400 mil TSOP-II Packages
■
Single 5V
±
10% Power Supply
■
TTL Interface
■
Optional Self Refresh (V53C518165AS)
• Refresh Interval: 1024 cycles/128 ms
Description
The V53C518165A is a 1048576 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C518165A offers Page mode op-
eration with Extended Data Output. The
V53C518165A has symmetric address, 10-bit row
and 10-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
20ns.
These features make the V53C518165A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power Temperature
MarkK T 50 60 Std.
0
°
C to 70
°
C • • • • • Blank
–40
°
C to +85
°
C•• • • • I
2
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Pin Names
A
0
–A
9
Row, Column Address Inputs
RAS Row Address Strobe
UCAS Column Address Strobe/Upper Byte Control
LCAS Column Address Strobe/Lower Byte Control
WE Write Enable
OE Output Enable
I/O
1
–I/O
16
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC No Connect
Description Pkg. Pin Count
TSOP-II T 44/50
SOJ K 42
VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
5
6
7
8
9
10
11
12
1
2
3
440
39
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
42
21
41 VCC
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
VSS
I/O16
I/O15
I/O14
I/O13
VSS
I/O12
I/O11
I/O10
I/O9
NC
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
VSS
5
6
7
8
9
10
11
1
2
3
4
15
16
17
18
19
20
511816500-02
21
22
23
24
25
46
45
44
43
42
41
40
50
49
48
47
36
35
34
33
32
31
30
29
28
27
26
42-Pin Plastic SOJ
PIN CONFIGURATION
Top View
44/50-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
3
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Block Diagram
No. 2 Clock
Generator
Data In
Buffer Data Out
Buffer
Column
Address
Buffers (10)
Refresh
Controller
Row
Decoder
Refresh
Counter (10)
Voltage Down
Generator
No. 1 Clock
Generator
Row
Address
Buffers (10)
10
16
I/O1 I/O2 I/O16
16
VCC
VCC (internal)
OE
10
10 10
16
1024
1024
x16
Memory Array
1024 x 1024 x 16
Sense Amplifier
I/O Gating
316516500-03
Column
Decoder
A0
UCAS
WE
LCAS
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
10
• • •
Absolute Maximum Ratings*
*
Note:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance*
T
A
= 25
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, f = 1 MHz
*
Note:
Capacitance is sampled and not 100% tested.
Symbol Parameter Commercial Extended Units
V
N
Power Supply Voltage -1 to +7 -1 to +7 V
V
DQ
Input/Output Voltage -0.5 to min (V
CC
+0.5, 7.0) -0.5 to min (V
CC
+0.5, 7.0) V
T
BIAS
Temperature Under Bias -10 to +125 -65 to +135
°
C
T
STG
Storage Temperature -55 to +125 -65 to +150
°
C
Symbol Parameter Min. Max. Unit
C
IN1
Address Input — 5 pF
C
IN2
RAS, UCAS, LCAS,
WE, OE — 7 pF
C
OUT
Data Input/Output — 7 pF
4
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
DC and Operating Characteristics
(1-2)
T
A
= 0
°
C to 70
°
C, V
CC
= 5 V
±
10%, V
SS
= 0 V, t
T
= 2ns, unless otherwise specified.
Symbol Parameter Access
Time
Commercial Extended
Unit Test Conditions NotesMin. Max. Min. Max.
I
LI
Input Leakage Current
(any input pin) –10 10 –10 10
m
A V
SS
£
V
IN
£
V
CC
+
0.5V 1
I
LO
Output Leakage Current
(for High-Z State) –10 10 –10 10
m
A V
SS
£
V
OUT
£
V
CC
+
0.5V
RAS, CAS at V
IH
1
I
CC1
V
CC
Supply Current,
Operating 50 130 200 mA t
RC
= t
RC
(min.) 2, 3, 4
60 115 180
I
CC2
V
CC
Supply Current,
TTL Standby 2 2 mA RAS, CAS at V
IH
other inputs
³
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh 50 130 200 mA t
RC
= t
RC
(min.) 2, 4
60 115 180
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
50 50 90 mA Minimum Cycle 2, 3, 4
60 40 75
I
CC5
V
CC
Supply Current,
during CAS-before-RAS Refresh 50 130 200 mA t
RC
= t
RC
(min.) 2, 4
60 115 180
I
CC6
V
CC
Supply Current,
CMOS Standby 1.0 1.0 mA RAS
³
V
CC
– 0.2 V,
CAS
³
V
CC
– 0.2 V
other input
³
V
SS
1
I
CC7
Self Refresh (Optional) 250 250
m
A CBR cycle with
t
RAS
³
t
RASS (min.)
,
CAS Held Low,
WE = V
CC
-0.2V,
Address and
D
IN
= V
CC
-0.2V or
0.2V
V
CC
Power Supply Voltage 4.5 5.5 4.5 5.5 V
V
IL
Input Low Voltage –0.5 0.8 –0.5 0.8 V 1
V
IH
Input High Voltage 2.4 V
CC
+0.5 2.4 V
CC
+0.5 V 1
V
OL
Output Low Voltage 0.4 0.4 V I
OL
= 4.2 mA 1
V
OH
Output High Voltage 2.4 2.4 V I
OH
= –5.0 mA 1
5
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
AC Characteristics
(5,6)
TA = 0°C to 70°C, VCC = 5 V ± 10%, tT = 2ns, unless otherwise noted
# Symbol Parameter
Limit Values
Unit Note
-50 -60
Min. Max. Min. Max.
Common Parameters
1 tRC Random read or write cycle time 84 — 104 — ns
2 tRP RAS precharge time 30 — 40 — ns
3 tRAS RAS pulse width 50 10k 60 10k ns
4 tCAS CAS pulse width 8 10k 10 10k ns
5 tASR Row address setup time 0 — 0 — ns
6 tRAH Row address hold time 8 — 10 — ns
7 tASC Column address setup time 0 — 0 — ns
8 tCAH Column address hold time 8 — 10 — ns
9 tRCD RAS to CAS delay time 12 37 14 45 ns
10 tRAD RAS to column address delay 10 25 12 30 ns
11 tRSH RAS hold time 13 — 15 — ns
12 tCSH CAS hold time 40 — 50 — ns
13 tCRP CAS to RAS precharge time 5 — 5 — ns
14 tTTransition time (rise and fall) 1 50 1 50 ns 7
15 tREF Refresh period — 16 — 16 ms
Read Cycle
16 tRAC Access time from RAS — 50 — 60 ns 8, 9
17 tCAC Access time from CAS — 13 — 15 ns 8, 9
18 tCAA Access time from column address — 25 — 30 ns 8,10
19 tOAC OE access time — 13 — 15 ns
20 tCAR Column address to RAS lead time 25 — 30 — ns
21 tRCS Read command setup time 0 — 0 — ns
22 tRCH Read command hold time 0 — 0 — ns 11
23 tRRH Read command hold time referenced to RAS 0 — 0 — ns 11
24 tCLZ CAS to output in low-Z 0 — 0 — ns 8
25 tOFF Output buffer turn-off delay 0 13 0 15 ns 12
26 tOEZ Output turn-off delay from OE 0 13 0 15 ns 12
27 tDZC Data to CAS low delay 0 — 0 — ns 13
28 tDZO Data to OE low delay 0 — 0 — ns 13
29 tCDD CAS high to data delay 10 — 13 — ns 14
30 tODD OE high to data delay 10 — 13 — ns 14
6
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Write Cycle
31 tWCH Write command hold time 8 – 10 – ns
32 tWP Write command pulse width 8 – 10 – ns
33 tWCS Write command setup time 0 – 0 – ns 15
34 tRWL Write command to RAS lead time 8 – 10 – ns
35 tCWL Write command to CAS lead time 8 – 10 – ns
36 tDS Data setup time 0 – 0 – ns 16
37 tDH Data hold time 8 – 10 – ns 16
Read-modify-Write Cycle
38 tRWC Read-write cycle time 113 – 138 – ns
39 tRWD RAS to WE delay time 64 – 77 – ns 15
40 tCWD CAS to WE delay time 27 – 32 – ns 15
41 tAWD Column address to WE delay time 39 – 47 – ns 15
42 tOEH OE command hold time 10 – 13 – ns
EDO Page Mode Cycle
43 tHPC EDO page mode cycle time 20 – 25 – ns
44 tCP CAS precharge time 8 – 10 – ns
45 tCPA Access time from CAS precharge – 27 – 32 ns 7
46 tCOH Output data hold time 5 – 5 – ns
47 tRASP RAS pulse width in EDO page mode 50 200k 60 200k ns
48 tRHPC CAS precharge to RAS Delay 27 – 32 – ns
49 tOES OE setup time prior to CAS 5 – 5 – ns
EDO Page Mode Read-Modify-Write Cycle
50 tPRWC EDO page mode read-write cycle time 58 – 68 – ns
51 tCPWD CAS precharge to WE 41 – 49 – ns
CAS-before-RAS Refresh Cycle
52 tCSR CAS setup time 10 – 10 – ns
53 tCHR CAS hold time 10 – 10 – ns
54 tRPC RAS to CAS precharge time 5 – 5 – ns
55 tWRP Write to RAS precharge time 10 – 10 – ns
56 tWRH Write hold time referenced to RAS 10 – 10 – ns
CAS-before-RAS Counter Test Cycle
57 tCPT CAS precharge time (CAS-before-RAS counter test cycle) 35 – 40 – ns
# Symbol Parameter
Limit Values
Unit Note
-50 -60
Min. Max. Min. Max.
AC Characteristics
(Cont’d)
7
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Optional Self Refresh
58 tREF Self Refresh period — 128 — 128 ms
59 tRASS RAS pulse width 100K — 100K — ns 17
60 tRPS RAS precharge time 95 — 110 — ns 17
61 tCHS CAS hold time -50 — -50 — ns 17
# Symbol Parameter
Limit Values
Unit Note
-50 -60
Min. Max. Min. Max.
8
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Notes:
1. All voltage are referenced to VSS.
2. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during
an EDO page mode cycle.
5. An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be
a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6. AC measurements assume tT = 2ns.
7. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8. Measured with the specified current load and 100pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by
the latter of tRAC, tCAC, tCAA, tCPA, tOAC, tCAC is measured from tristate.
9. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point
only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC.
10. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point
only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA.
11. Either tRCH or tRRH must be satisfied for a read cycle.
12. tOFF (max.), tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced
to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
13. Either tDZC or tDZO must be satisfied.
14. Either tCDD or tODD must be satisfied.
15. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electri-
cal characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit
(high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), and tAWD > tAWD (min.), the cycle
is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of con-
ditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in
read-write cycles.
17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM oper-
ation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
9
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of Read Cycle
Row
Column
Row
Valid Data Out
RAS
UCAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
VIH
VIL
tRAS
tRC
tCSH
tRAD
tCAS
tRP
tRAH
tCRP
tRSH
tRCD
tCAR
tASR tCAH
tASC tASR
tRCH
tRRH
tRCS
tCAA
tOAC
tCLZ
tCAC
tOEZ
tODD
tCDD
tOFF
tDZC
tDZO
tRAC
Hi ZHi Z
“H” or “L” 511816502-04
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
LCAS
10
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of Write Cycle (Early Write)
RAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
.
tRAS
Valid Data In
Hi Z
Column RowRow
“H” or “L”
511816502-05
tRC tRP
tCSH
tRCD tRSH
tCAS
tCRP
tCAR
tRAD
tASR tASC tCAH tASR
tCWL
tRAH tWCS
tWP
tWCH
tRWL
tDH
tDS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
UCAS
LCAS
11
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of Write Cycle (OE Controlled Write)
Valid Data
tRWL
tWP
tOEH
tCWL
Row
“H” or “L”
Hi-Z
Hi-Z
Column
Row
tASC
tRAD tCAR
tCAH
tRAH
RAS
Address
WE
OE
I/O
(Inputs)
I/O
(Outputs)
tCAS
tRSH
tRCD
tASR tASR
511816502-06
VIH
VIL
VOH
VOL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tRC
tRAS tRP
tCSH tCRP
tODD
tDZO
tDZC
tDH
tDS
tOEZ
tCLZ
tOAC
UCAS
LCAS
12
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of Read-Write (Read-Modify-Write) Cycle
RowRow
tRWC
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Column
Valid
Data in
Data
Out
tRAC
“H” or “L”
RAS
Address
511816502-07
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOL
VOH
tRAS tRP
tCSH
tRCD tRSH
tCAS tCRP
tASR
tCAH
tASC
tRAH
tASR
tRAD tAWD tCWD
tRWD
tCWL
tRWL
tWP
tOEH
tCAA tOAC
tRCS
tDS
tDH
tDZO
tDZC
tCLZ
tCAC tODD
tOEZ
UCAS
LCAS
13
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of EDO Page Mode Read Cycle
tRP
Column 2
Row
Data Out
RAS
I/O
WE
Address
VIH
VIL
“H” or “L”
OE
tRASP
(Output) Data Out
Column N
Column 1
Data Out
12N
511816502-08
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRHPC
tRCD
tCRP
tPC
tCAS tCP tCAS
tRSH
tCAS
tCRP
tCSH tCAR
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tRAD
tRCS
tRRH
tRCH
tCAC
tCAA
tCPA
tOES tCPA
tCAA tOFF
tOAC
tRAC
tCAC
tCAA
tCLZ
tCOH tCOH
tOEZ
tCAC
UCAS
LCAS
14
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of EDO Page Mode Read Cycle (OE Control)
Column 2
Row
Data Out
RAS
I/O
WE
Address
“H” or “L”
OE
tRASP
(Output) Data Out
Column N
Column 1
Data Out
12N
511816502-09
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRCD tRHPC
tRP
tCRP
tRSH
tCAS
tCAS
tCP
tCAS
tPC
tCRP
tCSH tCAR
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tRAD
tRCS
tRRH
tRCH
tCAC
tCAC
tCAA tCAA
tCPA
tCPA
tOES tOFF
tOEHC tOEHC
tOAC
tOEZ
tOAC
tOEP
tOEZ
tOAC
tOEP
tOEZ
tCAC
tCAA
tRAC
tCLZ
UCAS
LCAS
15
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of EDO Page Mode Read Cycle (WE Control)
Column 2
Row
Data Out
RAS
I/O
WE
Address
“H” or “L”
OE
tRASP
(Output) Data Out
Column N
Column 1
Data Out
12N
511816502-10
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRP
tRCD tRHPC
tPC
tCRP tCAS tCP tCAS
tRSH
tCAS
tCRP
tCSH
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
tCAR
tRAD tCAA tCAA tRRH
tRCH
tRCS
tRCH
tRCS
tRCH
tRCS
tWPZ
tOES
tOAC
tCPA
tCAC
tCPA
tCAC
tOFF
tOEZ
tWEZ
tWEZ
tCAC
tCLZ
tCAA
tCAR
tWPZ
UCAS
LCAS
16
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of EDO Page Mode Early Write Cycle
Column 1 Column 2
Row
Addr
Data In N
Data In 2
Data In 1
Column N
RAS
I/O (Input)
WE
Address
“H” or “L”
OE
tRASP
511816502-11
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRCD tRHPC
tRP
tCRP tPC
tCAS tCP tCAS tCAS
tCRP
tRSH
tCAR
tCAH
tASC
tCAH
tASC
tCAH
tCSH
tASC
tRAH
tASR
tRAD tCWL
tWCH
tWP
tWCS
tWP tWP
tWCH tWCH
tWCS tWCS
tCWL tCWL
tRWL
tDS tDH tDH
tDS tDH
tDS
UCAS
LCAS
17
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of EDO Page Mode Late Write Cycle
Column 2
Row
Data In
RAS
I/O
WE
Address
“H” or “L”
OE
(Input) Data In
Column N
Column 1
Data In
12N
511816502-12
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
tRASP
tRCD
tRP
tCRP
tPC
tCAS tCP tCAS tCP tCAS
tRSH tCRP
tCSH
tRAH
tASR tASC tCAH tCAH tCAH
tASC tASC
tCAR
tRAD tCWL tCWL tCWL
tRWL
tRCS
tRCStRCS
tWP tWP tWP
tOEH
tOEH
tOEH
tODD tODD
tDS tDH
tDS tDH
tDS tDH
tODD
UCAS
LCAS
18
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of EDO Page Mode Read-Modify-Write Cycle
RAS
WE
OE
Address
I/O
(Inputs)
I/O
(Outputs)
Data In Data In Data In
Data
Out Out
Data
Data
Out
Row
ColumnColumn
Row Column
tRASP
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tPRWC
tCSH
tRCD tCAS tCAS tCAS
tRSH
tRP
tCRP
tASR
tCAR
tCAH
tASC
tCAH
tCP
tCAH
tASC
tRAD
tRAH
tASR
tRWL
tCWL
tCPWD
tCWD
tCWL
tCWD
tCPWD
tCWL
tCWD
tRWD
tRCS
tAWD
tCAA
tOAC
tAWD
tOAC
tWP tWP
tAWD tWP
tRAC
tDZO
tCAC
tDZC tCLZ
tODD
tOEZ
tDS
tDH
tOEH
tDZC
tCPA
tCAA
tCLZ
tODD
tOEZ
tDS
tDH
tDZC
tCPA
tCLZ
tOEH tCAC
tCAA
tDS
tDH
tOEH
tODD
tOEZ
UCAS
LCAS
tASC
tOAC
511816502-13
19
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of RAS Only Refresh Cycle
Row
Row
HI-Z
Address
RAS
I/O
(Outputs)
“H” or “L”
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRC
tRAS tRP
tCRP
tRPC
tASR
tASR
tRAH
UCAS
LCAS
511816502-14
20
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of CAS-before-RAS Refresh Cycle
tRC
HI-Z
“H” or “L”
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRAS tRP
tRP
tRPC tCSR
tCP tCHR tRPC
tCRP
tWRP
tWRH
tOEZ
tCDD
tODD
tOFF
UCAS
LCAS
511816502-15
21
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of CAS-before-RAS Self Refresh Cycle (Optional)
HI-Z
“H” or “L”
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRASS tRPS
tRP
tRPC tCSR
tCP tCHS
tCRP
tWRP
tWRH
tOEZ
tCDD
tODD
tOFF
UCAS
LCAS
511816502-15
22
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of Hidden Refresh Read Cycle
RAS
I/O
(Outputs)
I/O
(Inputs)
OE
WE
Address
“H” or “L”
Valid Data Out
Row
Column
Row
HI-Z
511816502-16
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRC tRC
tRAS tRP tRAS tRP
tRCD tRSH
tCHR tCRP
tRAD tASC
tRAH
tASR tCAH
tWRP
tWRH tASR
tRRH
tRCS
tCAA
tOAC
tDZC
tDZO
tCDD
tODD
tOFF
tOEZ
tCAC
tCLZ
tRAC
UCAS
LCAS
23
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Waveforms of Hidden Refresh Early Write Cycle
RAS
I/O
(Output)
I/O
(Input)
WE
Address
“H” or “L”
tRC
Row Row
Valid Data
HI-Z
Column
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRAS
tRP
tRCD tRSH
tRC
tRAS tRP
tCRP
tCHR
tRAD
tRAH
tASR
tASC
tCAH tASR
tWCS tWCH
tWP
tWRP tWRH
tDS tDH
UCAS
LCAS
511816502-17
24
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Notes:
25
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Notes:
26
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Notes:
27
V53C518165A Rev. 1.1 January 1998
MOSEL VITELIC
V53C518165A
Package Diagrams
42-Pin 400 mil SOJ
44/50-Pin 400 mil TSOP-II
1.08 –0.010 [27.41 –0.25]
0.05 [1.27] 1.0 [25.4]
0.017±0.004
[0.43 ±0.1] 0.004 [0.1]
0.045 [1.15] MIN
0.145 [3.68] MAX
.406 –0.012 [10.3 –0.3]
.441 ±0.006 [11.2 ±0.15]
42
1
22
21
0.370±0.010 [9.4±0.25]
.406 –0.012(1)
[10.3 – 0.3]
.441 –0.006 [11.2 –0.15](1)
0.2
Unit in inches [mm]
0.81 [.032] MAX
+0.12
–0.05
0.008
+0.005
–0.002
0.088 ±0.004
[2.24 ±0.1]
(1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side.
50 263640
1 251511
0.016 +0.002
–0.004
0.4 +0.05
–0.1
0.006 +0.003
–0.001
0.15 +0.08
–0.03
0.008 [0.2] 44x
M
Unit in inches [mm]
0.004±0.002
[0.1±0.05]
0.031 [0.8]
0.039 ± 0.002
[1 ± 0.05] 0.4 ± 0.005
[10.16 ± 0.13]
0.463±0.008
[11.76 ± 0.2]
0.047 Max
[1.2 Max]
0.004 [0.1]
0.825±0.005
[20.95±0.13]
Does not include plastic or metal protrusion of 0.010 [0.25] max. per side
1
1
0.020±0.004
[0.5 ± 0.1]
MOSEL VITELIC
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MOSEL VITELIC subjects its products to normal quality control
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100% product quality assurance and does not assume any liabil-
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ucts. If such products are to be used in applications in which
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own quality assurance testing appropriate to such applications.
© Copyright 1998, MOSEL VITELIC Inc. 1/98
Printed in U.S.A.
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