Standard Products UT54ACS273/UT54ACTS273 Octal D-Flip-Flops with Clear Datasheet November 2010 www.aeroflex.com/logic FEATURES Contains eight flip-flops with single-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop Applications include: - Buffer/storage registers, shift registers, and pattern generators 1.2 CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack UT54ACS273 - SMD 5962-96578 UT54ACTS273 - SMD 5962-96579 PINOUTS 20-Pin DIP Top View CLR 1Q 1 2 20 19 VDD 8Q 1D 3 18 8D 2D 4 17 7D 2Q 5 16 7Q 3Q 3D 6 7 15 14 6Q 6D 4D 4Q 8 9 13 12 5D 5Q VSS 10 11 CLK 20-Lead Flatpack Top View DESCRIPTION The UT54ACS273 and the UT54ACTS273 are positive-edgetriggered D-type flip-flops with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The devices are characterized over full military temperature range of -55C to +125C. FUNCTION TABLE CLR 1 20 VDD 1Q 2 19 8Q 1D 3 18 8D 2D 2Q 4 5 17 16 7D 7Q 3Q 6 15 6Q 3D 7 14 6D 4D 4Q VSS 8 9 10 13 12 11 5D 5Q CLK LOGIC SYMBOL INPUTS OUTPUTS CLR CLK Dx Qx L X X L H H H H L L 1D H L X No change 2D 3D CLR CLK 4D 5D 6D 7D 8D 1 (1) (11) R C1 (2) (3) (4) (7) (8) (13) (14) (17) (18) 1D (5) (6) 1Q 2Q 3Q (9) 4Q (12) 5Q (15) 6Q (16) 7Q (19) 8Q Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM CLK (11) 1D (3) D C 4D (8) D C D C R CLR 3D (7) 2D (4) 6D (14) 7D (17) 8D (18) D C D C D C D C D C R R 5D (13) R R R R R (1) (2) 1Q (5) 2Q (6) (9) 3Q 4Q 2 (12) 5Q (15) 6Q (16) 7Q (19) 8Q OPERATIONAL ENVIRONMENT1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 80 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -.3 to VDD +.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 4.5 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C 3 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL VIL VIH IIN PARAMETER CONDITION MIN Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS MAX UNIT 0.8 .3VDD V .5VDD .7VDD V Input leakage current ACTS/ACS VIN = VDD or VSS Low-level output voltage 3 ACTS ACS IOL = 8.0mA IOL = 100A High-level output voltage 3 ACTS ACS IOH = -8.0mA IOH = -100A Short-circuit output current 2 ,4 ACTS/ACS VO = VDD and VSS -200 Output current10 VIN = VDD or VSS 8 mA (Sink) VOL = 0.4V Output current10 VIN = VDD or VSS -8 mA (Source) VOH = VDD - 0.4V Ptotal Power dissipation 2, 8, 9 CL = 50pF 1.9 mW/ MHz IDDQ Quiescent Supply Current VDD = 5.5V 10 A Quiescent Supply Current Delta For input under test 1.6 mA VOL VOH IOS IOL IOH IDDQ ACTS -1 1 A 0.40 0.25 V .7VDD VDD - 0.25 V 200 mA VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V CIN COUT Input capacitance 5 = 1MHz @ 0V 15 pF Output capacitance 5 = 1MHz @ 0V 15 pF 4 Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. 5 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V 10%; VSS = 0V 6, -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered. SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH CLK to Q 4 17 ns tPHL CLK to Q 4 19 ns tPHL CLR to Q 5 19 ns fMAX Maximum clock frequency 63 MHz tSU1 CLR inactive setup time before CLK 5 ns tSU2 Data setup time before CLK 5 ns tH Data hold time after CLK 3 ns tW Minimum pulse width CLR low CLK high CLK low 8 ns Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si). 6 PACKAGING Side-Brazed Packages 7 FLATPACK PACKAGES 8 UT54ACS273/UT54ACTS273: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 & 2) A = Solder C = Gold X = Optional Package Type: X = 20-lead ceramic bottom-brazed dual-in-line Flatpack C = 20-lead ceramic side-brazed dip Class Designator: Q = QML Class Q V = QML Class V Device Type: 01 Drawing Number: 96578 = UT54ACS273 96579 = UT54ACTS273 Total Dose: (Notes 3 & 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 9 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex UTMC Microelectronic Systems Inc. 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