To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 2tENESAS Renesas Technology Corp.MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL DESCRIPTION M51996A is the primary switching regulator controller which is especially designed to get the regulated DC voltage from AC power supply. This IC can directly drive the MOS-FET with fast rise and fast fall output pulse and with a large-drive totempole output. Type M51996A has the functions of not only high frequency OSC and fast output drive but also current limit with fast response and high sensibility so the true "fast switching regulator" can be realized. The M51996A is equivalent to the M51978 with externally re- settable OVP(over voltage protection)circuit. FEATURES @ 500kHz operation to MOS FET @ OULPUt CUITONE........ cscssesseseecensssersessnsesssetensssnestessetens @ Output rise time 60ns,fall time 40ns @ Modified totempole output method with small through current @ Compact and light-weight power supply 421A Small start-up current... ... 1O0UA typ. *Big difference between "start-up voltage" 2 and "stop voltage" makes the smoothing capacitor of the power input section small. Start-up threshold 16V,stop voltage 10V Packages with high power dissipation are used to with-stand the heat generated by the gate-drive current of MOS FET. 14-pin DIP,16-pin SOP 1.5W(at 25C) @ Simplified peripheral circuit with protection circuit and built-in large-capacity totempole output *High-speed current limiting circuit using pulse-by-pulse method(CLM+pin) *Over-voltage protection circuit with an externally re-settable latch(OVP) Protection circuit for output miss action at low supply voltage(UVLO) @ High-performance and highly functional power supply *Triangular wave oscillator for easy dead time setting *SOFT start function by expanding period APPLICATION Feed forward regulator, fly-back regulator RECOMMENDED OPERATING CONDITIONS Supply voltage range... 12 to 30V Operating nT than 500kHz Oscillator frequency setting resistance 10k to 75kQ 2k to 30kKQ *T-ON pin resistance RON.........0. eee *T-OFF pin resistance ROFF........ccccccecereeees PIN CONFIGURATION (TOP VIEW) COLLECTOR Vout EMITTER OVP F/B DET REG COLLECTOR VOUT EMITTER HEAT SINK PIN OVP F/B DET REG (4 [2 B) 4} @ [| $ [e| [7] Outline 14P4 Li [2] B| = 4] & | $ GB) 3 [7] [s| Outline 16P2N- > Vec CLM+ GND T-OFF CF T-ON SOFT Vec CLM+ GND HEAT SINK PIN T-OFF CF T-ON SOFT Connect the heat sink pin to GND. 2tENESAS (1/ 22)MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL BLOCK DIAGRAM REG(7.8V) 2 4 2 i VOLTAGE REGULATOR i UNDER | VOLTAGE LOCK OUT ove ())}|_ LATCH LATCH COLLECTOR 1 VOUT EMITTER CF ] CURRENT LIMIT TON OSCILLATOR DETECTION (TRIANGLE) T-OFF ! SOFT CLM+ GND ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vec Supply voltage 31 Vv Vc Collector voltage 31 Vv Peak +1 | = Ottbut-current Continuous +0.15 a IVREG VreEG terminal output current -6 mA VSOFT SOFT terminal voltage VreG +0.2 V VCLM+ CLM+ terminal voltage -0.3 to +3 V VDET DET terminal voltage 6 V love OVP terminal current 8 mA IFB F/B terminal current -10 mA ITON T-ON terminal input current a mA fone T-OFF terminal input current 2 mA Pa Power dissipation Ta=25C 1.5 Ww Ke Thermal derating Ta>25'C 12 mWwiC Topr Operating temperature -30 to +85 Cc Tstg Storage temperature -40 to +125 C Note 1."+" sign shows the direction of current flowing into the IC and "-" sign shows the current flowing out from the IC. 2.The low impedance voltage supply should not be applied to the OVP terminal. (@ 2.8 22: ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL ELECTRICAL CHARACTERISTICS (Vcc=18V, Ta=25C, unless otherwise noted) Block} Symbol Parameter Test conditions Min. Tp Max. Unit w~ | Vcc Operating supply voltage range Veo(STOP) 30 Vv S | VccistarT)| Operation start up voltage 15.2 | 16.2 | 17.2 V 3 Vccistop) | Operation stop voltage 9.0 9.9 10.9 V @ | Avec Vec(STant),Vec(sTor) difference AVcc=Vec(sTAAT) -Vec(STOP) 5.0 6.3 7.6 V 8 Voo=14.5V,Ta=25C 65 | 100 | 150 IecL Stand-by current : & y Vec=14.5V,-30<Tas85C 50 100 200 HA g | Icco Operating circuit current Veo=15V f=188kHz 73 u 17 Ha > Voec=30V,f=188kHz 8 12 19 a = | Iccove Circuit current in OVP state uGoneav 13 2.0 8.0 mu O Vec=9.5V 140 210 320 LA IFBMIND Current at 0% duty F/B terminal input current -2.1 -1.5 -1.0 mA lFBMAXD | Current at maximum duty F/B terminal input current -0.9 -0.6 -0.4 mA e AIFB Current differance between max and 0% duty AIFB=IFBMIND-IFBMAXD -1.35 | -0.99 | -0.70 mA VFB F/B terminal voltage F/B terminal input current=0.95mA 49 5.9 7.4 Vv Rre OVP terminal resistance 420 600 780 Q VTHOvPH | OVP terminal H threshold voltage 540 750 960 mV AVTHOvP | OVP terminal hysteresis voltage AVTHOVP=VTHOVPH-VTHOVPL 30 mV ItHove =| OVP terminal threshold current 80 150 250 pA o __linove | OVP terminal input current Vove=400mV 80 150 250 HA 75 9.0 10.0 V 3 Vccovec OMe reset supply voltage OVP terminal is open. Vcc(sTOP) | Difference supply voltage between (high impedance) 0.55 | 1.20 V -Vccovec | operation stop and OVP reset , i = -480 -320 | -213 ee Current from OVP terminal for Vcc=30V yA OVP reset Vec=18V -210 -140 -93 + | VtHcLm+ | CLM+ terminal threshold voltage 180 200 220 mV = lincLM+ | CLM+ terminal current VcLv+=0V -280 | -200 | -140 HA | Tepcims Delay time from CLM+ to VouT 100 ns Oscillating f oe ORS i tke 170 | 188 | 207 fose scillating frequency Cr=220pF,-5<Tac85C kHz Touty | Maximum ON duty 47 50 53 % S VOSCH Upper limit voltage of oscillation waveform Ron=20k2, ROFF=17kQ 3.97 4.37 4.77 Vv S | Vosc. | Lower limit voltage of oscillation waveform Cr=220pF 1.76 | 1.96 | 2.16 V 8 Voltage difference between upper limit and 211] 241) 274 | AVOSC | lower limit of OSC waveform , VT-ON | T-ON terminal voltage Ron=20kQ 3.8 4.5 5.4 Vv Vt-orF | T-OFF terminal voltage Rorr=17kQ 2.9 3.5 4.2 V VSOFT=5.5V | Ron=20kQ, RoFF=17kKQ 170 188 207 Oscillating frequency during = _ : foscsoFT SOFT operation Vsort=2.5V | Cr=220pF 111 131 151 kHz FE VsorT=0.2V 19.0 23.3 27.0 9 ISOFTIN | SOFT terminal input current VsortT=1V -0.5 -0.1 HA ISOFDIS ; ; ; Discharge current of SOFT terminal at SOFT terminal discharging current Voc less than Vecistop) 1 3.3 mA ii VREG Regulator output voltage 6.8 7.8 8.8 V Vout Vec=18V,lo=10mA 0.04 0.4 Vv VoL2 Output low voltage Vec=18V,lo=100mA 0.7 1.4 V w | VOL p 9 Vec=5V,lo=1mA 0.85 1.0 Vv a| vo4 Vec=5V,lo=100mA 13 | 20 Vv = = | Von Vec=18V,lo=-10mA 16.0 | 16.7 Vv Output high voltage , VoH2 RU Veo=18V,lo=-100mA 15.5 | 165 V TRISE Output voltage rise time 60 ns TFALL | Output voltage fall time 40 ns 5 | Voer | Detection voltage 24 | 25 2.6 Vv 8 IINDET DET terminal input current VoeET=2.5V 1.0 3.0 pA 8 GAVDET | Voltage gain of detection amp 30 40 dB (3 / 22 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL TYPICAL CHARACTERISTICS THERMAL DERATING 1800 (MAXIMUM RATING) 1500 1200 900 600 POWER DISSIPATION Pd(mW) /| 300 \ \ \ 0 25 50 7585 100 125 AMBIENT TEMPERATURE Ta(C) SOFT TERMINAL INPUT VOLTAGE VS. EXPANSION RATE OF PERIOD 150 CIRCUIT CURRENT VS.SUPPLY VOLTAGE (NORMAL OPERATION) a RON=18k22 fosc=500kHz ROFF=20k | _ | | Lee =< 12m pees ae E a ov = | 2 10m : . I SH | 5 } Wu fosc=100kHz c 5 #8 x 150m a7 E 3 Ta=-30C a ee oO = 50u 0 5 10 #15 20 25 30 35 40 SUPPLY VOLTAGE Vec(V) SOFT TERMINAL INPUT VOLTAGE VS. EXPANSION RATE OF PERIOD 5.0 os YOO = (fosc=100kHz) = (fosc=500kHz) o . 7) RON=15k, ROFF=27k o . 1) RON=15k, ROFF=27k < 3.5 2) RON=18k,ROFF=24k = 35 2 RON=18k, ROFF=24k ad 4) RON=22k,ROFF=22k = | 3) RON=22k,ROFF=22k 2 20 d- RON=24k, ROFF=20k 2 3.0 dy RON=24k, ROFF=20k e )| RON=22k, ROFF=12k eK 5) RON=22k,ROFF=12k a 2.5 6] RON-36k, ROFF=6.2k a 2.5 61 RON=36k,ROFF=6.2k | = = 2 20 3 2.0 = 15 = 15 Fe G 1.0 7 1.0 wi j i 0.5 i 0.5 v 0 1} 2] ays [5 6 a 0 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 EXPANSION RATE OF PERIOD(TIMES EXPANSION RATE OF PERIOD(TIMES) ( ) - SOFT TERMINAL INPUT VOLTAGE VS. CEMA TEHMANDE IHBE Stole SOErAGe < 400 INPUT VOLTAGE VS. AMBIENT TEMPERATURE = . z w > 5 -90 <& 3: 6 > = 205 =z of ke J > = oO o = > wo E Wi = 200 a I z - 7 I z 195 wi FE oi + & = 8 3 0 0 1 2 3 4 5 6 F 8 g 10 -60 -40 -20 0 20 640 60 = 80=6(100 SOFT TERMINAL INPUT VOLTAGE VsorT(V) AMBIENT TEMPERATURE Ta(C) (4 / 22 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL CLM+ TERMINAL CURRENT Iinci+(uA) OUTPUT HIGH VOLTAGE Vec-VoH(V) DETECTION VOLTAGE VpeT(V) CLM+ TERMINAL CURRENT VS. CLM+ TERMINAL VOLTAGE -400 -300 Ta=-30C Ta=25C _Ta=85C -200 -100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 CLM+ TERMINAL VOLTAGE Vcim+(V) OUTPUT HIGH VOLTAGE VS. SOURCE CURRENT 4.5 4.2 3.9 3.6 3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 i 103 107 10" 10 i0' SOURCE CURRENT Ion(A) DETECTION VOLTAGE VS. AMBIENT TEMPERATURE 2.554 2.50 2,45 2.40 -0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) 2tENESAS OUTPUT LOW VOLTAGE VoL(V) REG OUTPUT VOLTAGE Vrec(V) DETECTION TERMINAL INPUT CURRENT REG OUTPUT VOLTAGE VS. AMBIENT TEMPERATURE 8.57 8.0 7.5F 7.0 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) OUTPUT LOW VOLTAGE VS. SINK CURRENT 5.0 45 4.0 3.5 3.0 2.5 2.0 Vec=18V 1.5 1.0 0.5 0 10 1 107 10 10' SINK CURRENT IoL(A) DETECTION TERMINAL INPUT CURRENT VS. AMBIENT TEMPERATURE 1.4 1.3 1.2 1.1 < 1.0 G = 00 0.8 0.7 0 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) (5 / 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL VOLTAGE GAIN OF DETECTION AMP UPPER & LOWER LIMIT VOLTAGE OF OSC GDET(dB) ON duty (%) Voscu-VoscL() VOLTAGE GAIN OF DETECTION AMP VS. FREQUENCY 50 45 40 35. 30 25 20 15 10 1 10 10 10 10 FREQUENCY (Hz) ON duty 59 VS. F/B TERMINAL INPUT CURRENT (fosc=200kHz) Ron=18kQ RorF=20kQ 40 30 | | | | | LL Ta=-30C Ta=25C 20 { | | Ta=85C 10 09kaa 0.6 0.8 1.0 1.2 1416 1.8 2.0 2.2 F/B TERMINAL INPUT CURRENT Irie (mA) UPPER & LOWER LIMIT VOLTAGE OF OSC VS. AMBIENT TEMPERATURE Ron=18kQ 5-2) Rorr=20kQ 48 -~ fosc=200kHz 4.0 t t t + fosc=100kHz; fosc=100kHz 2.2 1 1 1 + fosc=200kHz fosc=500kHz 2.0 t ee 1.8 -0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) 2tENESAS ON duty (%) ON duty (%) OSCILLATING FREQUENCY fosc(kHz) ON duty VS. F/B TERMINAL INPUT CURRENT 45 foo} | (fosc=100kHz) Ron=18kQ Rorr=20kQ 40 35. BS cm lle um a Ta=25C Ta=85C 25 20 15 10 gaa 0.6 0.8 1.0 12 14 1.6 18 2.0 22 F/B TERMINAL INPUT CURRENT IF/s (mA) ON duty VS. F/B TERMINAL INPUT CURRENT 50 (fosc=500kHz) Ron=18kQ RorF=20kQ = Ta=-30C Ta=25C - Ta=85C ol aoa 0.60.8 1012 1416 18 2.0 2.2 F/B TERMINAL INPUT CURRENT IF/a(mA) OSCILLATING FREQUENCY VS. CF TERMINAL CAPACITANCE 107 Rorr=6.2kQ Ll tod 21 Rorr=20k2 10! 5 a 2 10 40? 3 yp 23 5 10223 5 49323 5 494 CF TERMINAL CAPACITANCE (pF) {( 6 / 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL ON duty VS. Rorr OSCILLATOR FREQUENCY VS. AMBIENT TEMPERATURE 2tENESAS 100 120 90 x Ron=24kQ 80 = RorF=20kQ a Cr=330pF 2 4110 P 70 Ron=75kQ 3 ee) 1 z 0 ee ee x 51kQ w 2 50 kQ 3 2 KO S100 3 fia z 40 e oO 30 e 90 20 a 8 10 o 0 10 10 3 10 80 50 -40 -20 O 20 40 60 80 100 RorF(kQ) AMBIENT TEMPERATURE Ta(C) OSCILLATOR FREQUENCY VS. AMBIENT TEMPERATURE ON duty VS. AMBIENT TEMPERATURE 700 100 (fosc=100kKHz) N Ron=24kQ, 90 = Rorr=20kQ2 = 600 CF=47pF 80 RON=36k, ROFF=6.2k g : gz < 500 + t 1 1 } } x 60 = RON=22k,ROFF=12k wi poo % o co 450 RON=24k, ROFF=20k vd S en AON=22k, ROFF=22k = 400 40 RON=18k, ROFF=24k 9 30 = RONEISK, ROFFE27K 5 = 300 20 3 oO 10 200 0 -60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE Ta(C) AMBIENT TEMPERATURE Ta(C) nan ON duty VS. AMBIENT TEMPERATURE ON duty VS. AMBIENT TEMPERATURE 100 (fosc=200kHz) (fosc=500kHz) 90 | | | 90 | | | 80 RON=36k, ROFF=6.2k 80 a RON=36k, ROFF=6.2k 70 70 & x > 60 FON-22k,ROFF=12k = 60 i RON=22K, ROFF=12K S 5 | 3 50 R= 24k, RoFF=20k 3 50 RON=24k,ROFF=20k S oe RON=22k,ROFF=22k p> l= RON=22k,ROFF=22k 40 [ RON=18k,ROFF=24k O 40 | RON=18K, ROFF=24k 30 OO _ RON 15k, ROFF=27k 30 ft RON=15k,ROFF=27k 20 20 10 10 0 0 -60 -40 -20 O 20 40 60 80 100 -60 -40 -20 OQ 20 40 60 80 = 100 AMBIENT TEMPERATURE Ta(C) AMBIENT TEMPERATURE Ta(C) (7/22)MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL OVP TERMINAL INPUT CURRENT lovp(A) CIRCUIT CURRENT lee(mA) im 100p 10p 1p OVP TERMINAL INPUT VOLTAGE VS. INPUT CURRENT Ta=85C = \Ta=25C 1} Ta=-30C+ 0.2 0.4 0.6 0.8 1.0 OVP TERMINAL INPUT VOLTAGE Vove(V) CIRCUIT CURRENT VS.SUPPLY VOLTAGE (OVP OPERATION) 8.0 OVP RESET POINT__ 7.0} 8:87V(-30C) | 8.94V(25C) 9.23V(85C) 5.0 4.0 Ta=-30% | | | Ta-25CS 3.0 _Ta=85C-. 2.0 1.0 0 0 10.0 20.0 30.0 40.0 SUPPLY VOLTAGE Vec(V) OUTPUT THRUGH CURRENT WAVEFORM AT RISING EDGE OF OUTPUT PULSE Horizontal-axis : 20ns/div Vertical-axis =: 50mA/div CURRENT FROM OVP TERMINAL FOR OVP RESET OVP TERMINAL THRESHOLD VOLTAGE VTHOVP(V) Hovec(HA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 800 700 600 500 400 300 200 100 OVP TERMINAL THRESHOLD VOLTAGE VS.AMBIENT TEMPERATURE +Mcc=18V H threshold voltage W- (VTHOVPH) +L threshold voltage (VTHOVPL)_| 40 -20 0 20 40 60 g0 100 AMBIENT TEMPERATURE Ta(C) CURRENT FROM OVP TERMINAL FOR OVP RESET VS.SUPPLY VOLTAGE Ta=-30C | Ta=25C -Ta=85C 5 10 15 20 25 30 35 4 SUPPLY VOLTAGE Vec(V) AT FALLING EDGE OF OUTPUT PULSE Horizontal-axis : 20ns/div Vertical-axis : 5mA/div 0 2tENESAS (8 / 22)MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL FUNCTION DESCRIPTION Type M51996AP and M51996AFP are especially designed for off-line primary PWM control IC of switching mode power supply to get DC voltage from AC power supply. Using this IC,smart SMPS can be realized with reasonable cost and compact size as the number of external electric parts can be reduced and also parts can be replaced by reasonable one. In the following circuit diagram,MOS-FIT is used for output transistor however bipolar transistor can be replaced with no problem. RUSH CURRENT PREVENTION CIRCUIT o OF) + A =Rt . . 7 | DG OUTPLT * | 6 6 * ! Ver COLLECTOR Al vout (_}-w ka REG > MA i ig be te CLM+h_/ WW _ Veo + ee 5 Bi sm = M51996AP/FP EMITTER INPUT| & PH loan) 3 Lu = +{ SOFT GND DET OVP__FIB_T-ON CE __T-OFF iL L 'S) = Act az | RON i RoFF of] {|} || L_| FEEDBACK l ___ - ove ANA; AN, || = a. a {TL431) i Fig.1 Application example for feed forward regulator AUSH CURRENT PREVENTION CIRCUIT e oI __ + ei . . 2= DC OUTPUT | 0 6 an L Vee COLLECTOR 7 vout (>) w Fe pnE-C) Fe - wee CLM+ en aes 15 at ae - MS51996AP/FP cywrtea INPUT | PH cen [cvec REG z L GND = = SOFT DET T-ON CF __T-OFF | TT = RON | ROFF oO4 - . . * Fig.2 Application example for fly-back regulator 2tENESAS (9 / 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL Start-up circuit section The start-up current is such low current level as typical 100 A,as shown in Fig.3,when the Vcc voltage is increased from low level to start-up voltage Vcc(START). In this voltage range,only a few parts in this IC,which has the function to make the output voltage low level,is alive and Icc current is used to keep output low level.The large voltage difference between Vcc(START) and Vcc(stor) makes start-up easy, because it takes rather long duration from Vcc(sTART) to Vec(sTop). = Icco SAMA Resort ke = Ww cc cr 5 = Ilece Pp E ~100uA Oo c Vcc Vcc o (STOP) (START) =9.9V =16.2V SUPPLY VOLTAGE Vec(V) Fig.3 Circuit current vs.supply voltage Oscillator section The oscillation waveform is the triangle one. The ON-duration of output pulse depends on the rising duration of the triangle waveform and dead-time is decided by the falling duration. The rising duration is determined by the product of external resistor Ron and capacitor Cr and the falling duration is mainly determined by the product of resistor RorF and capacitor Cr. (1)Oscillator operation when SOFT circuit does not operate Fig.4 shows the equivalent charging and discharging circuit diagram of oscillator. The current flows through Ron from the constant voltage source of 5.8V.CrF is charged up by the same amplitude as Ron current,when internal switch SW1,SW2 is switched to "charging side" The rise rate of Cr terminal is given as ~ _T-ON where VT- ON 4.5V The maximum on duration is approximately given as ~ _(VOScH-VoscL) X RON X Cr = VekGn (S) ooo eeeeeeeeesveeee(2) where VoscH ~ 4.4V Vosc. = 2.0V Cr is discharged by the summed-up of Rorr current and one sixteenth (1/16) of Ron current by the function of Q2,Q3 and Q4 when SW1,SWe2 are switched to discharge side". C Ts J 5.8V T-ON CHARGING Ron= | + Swi T-OFF * - SWITCHED BY Rorr VF SIGNAL CHARGING AND Vz=4.3V iDISGHARGING (SIGNAL Do 8 Pale! DISCHARGING _M51996A Fig.4 Schematic diagram of charging and discharging control circuit for OSC.capacitor Cr VOSCH =4.4V VOSCL | _ =2.0V WAVEFORM OF CF TERMINAL VOH VOL WAVEFORM OF YouT TERMINAL IN MAX. ON DUTY CONDITION Fig.5 OSC.waveform at normal condition (no- operation of intermittent action and OSC.control circuit) So fall rate of CF terminal is given as ~ _VT-OFF VT -ON ~~ Bore X CE + 16 X RON X Cp WS) ensseeeeeeeeeeeenee (3) The minimum off duration approximately is given as ~ _(VoscH-VoscL) X Cr SO VTHOFF . VT-ON (Sd sssssesesnsssesssssnsecnssneseessssee(4) RoFF 16 X Ron where VT - OFF ~ 3.5V The cycle time of oscillation is given by the summation of Equations 2 and 4. The frequency including the dead-time is not influenced by the temperature because of the built-in temperature compensating circuit. 2tENESAS (10 / 22 )(2)Oscillator operation when the SOFT(soft start) circuit is operating. Output transistor is protected from rush current by CLM function at the start time of power on.SOFT terminal is used to improve the rising response of the output voltage of power supply(prevention of overshooting). The ON duration of output is kept constant,and the OFF duration is extended as the SOFT terminal voltage becomes lower by the soft start circuit of this IC. The maximum value of extension is set internally at approximately sixteen times of the maximum ON duartion. The features of this method are as follows: a) It is ideal for primary control as IC driving current is supplied from the third widing of the main transformer at the start-up because constant ON duration is obtained from start-up. It is possible to get a wide dynamic range for ON/OFF ratio by pulse-by-pulse current limit circuit. (3) The response characteristics at power-on is not affected by input voltage as the pulse-by-pulse limit current value is not affected by the input voltage. Fig.6 shows the circuit diagram of the soft start.If SOFT terminal voltage is low,T-OFF terminal voltage bocomes low and VT-oFF in equations (3) and (4) become low. TO REG TO REG TERMINAL TERMINAL RSOFT | | SOFT TERMINAL t ceorn| | DISCHARGING TRANSISTOR* IC's INTERNAL CIRCUIT *Active when operation stops. + T-OFF TERMINAL Vz2=4.2V | GND | TERMINAL Fig.6 Circuit diagram of SOFT terminal section and T- OFF terminal section VOSCH =4.4V VOSCL | _ t nN S = WAVEFORM OF CF VOH | -- VOL TERMINAL INMAX.ON duty TERMINAL WAVEFORM OF VouT CONDITION t Fig.7 Oscillator waveform when the SOFT circuit is operating WAVEFORM OF CF WAVEFORM OF Vout MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL START FROM 0V - \ 3 = \ oc 1 Ww i 1 - 1 2 3 5 ' THE FIRST * ' i OUTPUT PULSE $ | 2 z VOH F - AT RST EES Sree 25 NO OUTPUT ze ' PULSE ie VOL r o-7 t Fig.8 Relationship between oscillator waveform and output waveform at start-up Fig.7 shows the relationship between oscillator waveform and output pulse. If the SOFT terminal voltage is Vsort,the rise rate of CF terminal given as VT - ON = _ (WS RON GE (VIS) oo ccccesecscsssssssessesesestsessrsesstsesseresreseereene() The fall rate of oscillation waveform is given as . SOFT - VBE VT - ON Pays Ge e* RONKGE (M/S) siisiscevsiceensstieneces (6) where Vsort;SOFT terminal applied voltage Vee ~ 0.65V If VSorT - VBE < 0, VSCFT - VaE=0 If VSOFT - VBE > VT - OFF (~3.5V), VSOFT - VBE=VT - OFF PWM comparator, PWM latch and current limit latch section Fig.9 shows the scematic diagram of PWM comparator and PWM latch section. The on-duration of output waveform coincides with the rising duration of CF terminal waveform,when the no output current flows from F/B terminal. When the F/B terminal has finite impedance and current flows out from F/B terminal,"A" point potential shown in Fig.9 depends on this current.So the "A" point potential is close to GND level when the flow-out current becomes large. "A" point potential is compared with the CF terminal oscillator waveform and PWM comparator,and the latch circuit is set when the potential of oscillator waveform is higher than "A" point potential. The latch circuit is reset during the dead-time of oscillation (falling duration of oscillation current).So the "B" point potential or output waveform of latch circuit is the one shown in Fig. 10. The final output waveform or "C" point potential is got by combining the "B" point signal and dead-time signal logically.(please refer to Fig.10) (11/ 22 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL OSC WAVEFORM OF CF TERMINAL LATCH POINT B To VTHCLM= 200mV CURRENT "yig- OUTPUT WA by WAVEFORM OF _ CLM+ TERMINAL POINT G 2 CURRENT LIMIT | SIGNAL TO SET LATCH 2 TFROM ye osc M51996 CF CLM+ \ WAVEFORM OF GO VOUT TERMINAL 1 Resistor to determine current limit sensitivety 2 High level during dead time Fig.11 Operating waveform of current limiting circuit Fig.9 PWM comparator PWM latch and , . . current limit latch section To eliminate the abnormal operation by the noise voltage,the low pass filter,which consists of RnF and Cnr is used as shown in Fig.12. OSC WAVEFORM It is recommended to use 10 to 100Q for RNF because such range of Rne is not influenced by the flow-out current of some 200yA from Cim+ terminal and Cnr is designed to have the enough value to absorb the noise voltage. WAVEFORM OF O.S.C.& POINT A M51996 le POINTB | | var) St a l Lo POINT C | CLM+ o: BE | Le cnr =A Fig.10 Waveforms of PWM comparator input point A, i latch circuit points B and C GND Pod a | Current limiting section When the current-limit signal is applied before the crossing . . . a instant of "A" pint potential and CF terminal voltage shown in Fig.12 Connection diagram of current limit circult Fig.9,this signal makes the output off" and the off state will continue until next cycle.Fig.11 shows the timing relation among them. Voltage detector circuit(DET) section If the current limiting circuit is set,no waveform is generated at output terminal, however this state is reset during the The DET terminal can be used to control the output voltage succeeding dead-time. which is determined by the winding ratio of fly back transformer So this current limiting circuit is able to have the function in in fly-back system or in case of common ground circuit of every cycle,and is named "pulse-by-pulse current limit". primary and secondary in feed forward system. There happen some noise voltage on Rcvm during the switching The circuit diagram is quite similar to that of shunt regulator of power transistor due to the snubber circuit and stray type 431 as shown in Fig.13.As well known from Fig.13 and capacitor of the transformer windings. Fig.14,the output of OP AMP has the current-sink ability,when the DET terminal voltage is higher than 2.5V ( 12/ 22 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL It is necessary to input the sufficient larger current(800A to 8mA)than |2 for triggering the OVP operation. The reason to decrease [2 is that it is necessary that Icc at the OVP rest supply voltage is small. It is necessary that OVP state holds by circuit current from R1 in the application example,so this IC has the characteristic of small Icc at the OVP reset supply voltage(~stand-by current + 20pA) On the other hand,the circuit current is large in the higher supply voltage,so the supply voltage of this IC doesn't become so high by the voltage drop across R1. This characteristic is shown in Fig.16. The OVP terminal input current in the voltage lower than the OVP threshold voltage is based on |2 and the input current in the voltage higher than the OVP threshold voltage is the sum of the current flowing to the base of Q3 and the current flowing from the collector of Q2 to the base. For holding in the latch state,it is necessary that the OVP terminal voltage is kept in the voltage higher than VeE of Q3. So if the capacitor is connected between the OVP terminal and GND,even though Q2 turns on in a moment by the surge voltage,etc,this latch action does not hold if the OVP terminal voltage does not become higher than Vee of Q3 by charging this capacitor. For resetting OVP state,it is necessary to make the OVP terminal voltage lower than the OVP L threshold voltage or make Vcc lower than the OVP reset supply voltage. As the OVP reset voltage is settled on the rather high voltage of 9.0V,SMPS can be reset in rather short time from the switch-off of the AC power source if the smoothing capacitor is not so Fig.13 Voltage detector circuit section(DET) but it becomes high impedance state when lower than 2.5V DET terminal and F/B terminal have inverting phase characteristics each other,so it is recommended to connect the resistor and capacitor in series between them for phase compensation.I|t is very important one can not connect by resistor directly as there is the voltage difference between them and the capacitor has the DC stopper function. large value. Vee O * 7.8V 100A 8k hh 12k Qi + Fig.14 Schmatic diagram of voltage detector circuit section(DET) 400 . . . . . . ovP Q3 OVP circuit(over voltage protection circuit)section { 2.5k OVP circuit is basically positive feedback circuit constructed GNDO iu by Q2,Q3 as shown in Fig.15. 11=0 when OVP operates Q2,Q3 turn on and the circuit operation of IC stops,when the . oo _, input signal is applied to OVP terminal.(threshold voltage ~ Fig.15 Detail diagram of OVP circuit 750mv) The current value of I2 is about 150A when the OVP does not operates but it decreases to about 2uA when OVP operates. (13 / 22 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL OVP RESET POINT. 718.87V(-30C) 8.94V(25C) 6 | _9.23V(85C) Ta=-30C | Tae25C IN | Ta=85C ON CIRCUIT CURRENT Ice(mA) 0 10 20 30 40 SUPPLY VOLTAGE Vcc(V) Fig.16 CIRCUIT CURRENT VS. SUPPLY VOLTAGE (OVP OPERATION) Output section Itis required that the output circuit have the high sink and source abilities for MOS-FET drive.t is well known that the totempole circuit has high sink and source ability. However, it has the demerit of high through current. For example,the through current may reach such the high current level of 1A,if type M51996A has the "conventional" totempole circuit.For the high frequency application such as higher than 100kHz,this through current is very important factor and will cause not only the large Icc current and the inevitable heat-up of IC but also the noise voltage. This IC uses the improved totempole circuit,so without deteriorating the characteristic of operating speed,its through current is approximately 100mA. APPLICATION NOTE OF TYPE M51996AP/FP Design of start-up circuit and the power supply of IC (1)The start-up circuit when it is not necessary to set the start and stop input voltage Fig.17 shows one of the example circuit diagram of the start-up circuit which is used when it is not necessary to set the start and stop voltage. It is recommended that the current more than 300A flows through R11 in order to overcome the operation start-up current lcc(START) and Cvec is in the range of 10 to 47yF.The product of R1 by Cvcc causes the time delay of operation,so the response time will be long if the product is too much large. RECTIFIED DC VOLTAGE FROM MAIN TRANSFORMER SMOOTHING CAPACITOR Rl ove ( | Vcc THIRD WINDING OR BIAS WINDING M51996A we az CVoo GND Fig.24 Start-up circuit diagram when it is not necessary to set the start and stop input voltage Just after the start-up,the lcc current is supplied from Cvcc,however,under the steady state condition ,IC will be supplied from the third winding or bias winding of transformer,the winding ratio of the third winding must be designed so that the induced voltage may be higher than the operation-stop voltage VecisTor). The Vcc voltage is recommended to be 12V to 17V as the normal and optimum gate voltage is 10 to 15V and the output voltage(Von) of type M51996AP/FP is about(Vcc-2V). Itis not necessary that the induced voltage is settled higher than the operation start-up voltage Vcc(sTART),and the high gate drive voltage causes high gate dissipation,on the other hand,too low gate drive voltage does not make the MOS-FET fully on- state or the saturation state. (2)The start-up circuit when it is not necessary to set the start and stop input voltage It is recommend to use the third winding of forward winding" or "positive polarity" as shown in Fig.18,when the DC source voltages at both the IC operation start and stop must be settled at the specified values. The input voltage(VIN(STAAT)),at which the IC operation starts,is decided by R1 and R2 utilizing the low start-up RECTIFIED DC VIN * PRIMARY WINDING VOLTAGE FROM NP OF TRANSFORMER SMOOTHING CAPACITOR 4 Fi VE Vee Ne @ THIRD WINDING OF TRANSFORMER M51996A + r= zz CVce GND Fig.18 Start-up circuit diagram when it is not necessary to set the start and stop input voltage 2tENESAS (14/ 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL current characteristics of type M51996AP/FP. The input voltage(Vin(stop)),at which the IC operation stops,is decided by the ratio of third winding of transformer. The VIN(START) and Vin(sTOP) are given by following equations. VIN(START)= R1 * IccL + a + 1) * VCC(STARTL...........(7) VIN(STOP}= (Vec(STOP)-V! NE gol ! IN(STOP}= (Vec(STOP)-VF) Ne 2 V'IN RIP(P-P),..........(B) where IccL is the operation start-up current of IC Vcc(sTant) is the operation start-up voltage of IC Vec(sTop) is the operation stop voltage of IC VF is the forward voltage of rectifier diode V'in(P-P) is the peak to peak ripple voltage of ; Ne Vcc terminal NP V'IN RIP(P-P} Itis required that the Vin(sTART) must be higher than ViN(sTOP). When the third winding is the "fly back winding" or "reverse polarity",the Vin(START) can be fixed, however, VIN(STOP) can not be settled by this system,so the auxiliary circuit is required. (3)Notice to the Vcc, Vcc line and GND line To avoid the abnormal IC operation,it is recommended to design the Vcc is not vary abruptly and has few spike voltage,which is induced from the stray capacity between the winding of main transformer. To reduce the spike voltage,the Cvec,which is connected between Vcc and ground,must have the good high frequency characteristics. To design the conductor-pattern on PC board,following cautions must be considered as shown in Fig.19. (a)To separate the emitter line of type M51996A from the GND line of the IC (b)The locate the Cvcc as near as possible to type M51996A and connect directly (c)To separate the collector line of type M51996A from the Vcc line of the IC (d)To connect the ground terminals of peripheral parts of ICs to GND of type M51996A as short as possible MAIN COLLECTOR t vee ( TRANSFORMER THIRD WINDING K-CH M51996A meet OUTPUT Rc_m aren ano ( / Fig.19 How to design the conductor-pattern of type M51996A on PC board(schematic example) (4)Power supply circuit for easy start-up When IC start to operate,the voltage of the Cvcc begins to decrease till the Cvcc becomes to be charged from the third winding of main-transformer as the Icc of the IC increases abruptly.In case shown in Fig.17 and 18,some unstable start- up" or "fall to start-up" may happen, as the charging interval of Cvcc is very short duration;that is the charging does occur only the duration while the induced winding voltage is higher than the Cvcc voltage, if the induced winding voltage is nearly equal to the "operation-stop voltage" of type M51996A. It is recommended to use the 10 to 47yF for Cvcci,and about 5 times capacity bigger than Cvcc1 for Cvccez. {qd 1 MAIN Vee TRANSFORMER THIRD WINDING + M51996A oY CVeet CVee2 GND Fig.20 DC source circuit for stable start-up 2tENESAS (15/ 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL OVP circuit (1)To avoid the miss operation of OVP It is recommended to connect the capacitor between OVP terminal and GND for avoiding the miss operation by the spike noise. The OVP terminal is connected with the sink current source (~150pA) in IC when OVP does not operate,for absorbing the leak current of the photo coupler in the application. So the resistance between the OVP terminal and GND for leak- cut is not necessary. If the resistance is connected,the supply current at the OVP reset supply voltage becomes large. As the result,the OVP reset supply voltage may become higher than the operation stop voltage. In that case,the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation stop voltage. So it should be avoided absolutely to connect the resistance between the OVP terminal and GND. O Vee M51996A To REG or Vcc PHOTO COUPLER + GND Fig.21 Peripheral circuit of OVP terminal (2)Application circuit to make the OVP-reset time fast The reset time may becomes problem when the discharge time constant of Crin * (R1+R2) is long. Under such the circuit condition, it is recommended to discharge the Cvcc forcedly and to make the Vcc low value;This makes the OVP-reset time fast. (3)OVP setting method using the induced third winding voltage on fly back system For the over voltage protection (OVP),the induced fly back type third winding voltage can be utilized,as the induced third winding voltage depends on the output voltage.Fig.23 shows one of the example circuit diagram. TO MAIN TRANSFORMER > =A 9 a + + | Veco alll aE HE ] CFIN/R2 | Cvec |M51996A |@nb THE TIME CONSTANT OF THIS PART SHOULD BE SHORT Fig.22 Example circuit diagram to make the OVP-reset-time fast MAIN TRANSFORMER THIRD WINDING 4700 MS51996A a= CVec GND FIG.23 OVP setting method using the induced third winding voltage on fly back system (4)Method to control for ON/OFF using the OVP terminal You can reset OVP to lower the OVP terminal voltage lower than VTHOVPL. So you can control for ON/OFF using this nature. The application is shown in Fig.24. The circuit turns off by SW OFF and turns on by SW ON in this application. Of course you can make use of the transistor or photo-transistor instead of SW. M51996A ON/OFF in FIG.24 Method to control for ON/OFF using the OVP terminal 2tENESAS (16 / 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL Current limiting circuit (1)Peripheral circuit of CLM+ terminal : Fig.25 shows the example circuit diagrams around the CLM+ terminal.It is required to connect the low pass filter,in order to reduce the spike current component,as the main current or drain current contains the spike current especially during the turn-on duration of MOS-FIT. SH 1,000pF to 22,000pF is recommended for Cnr and the RnF1 CLM and Rnr2 have the functions both to adjust the "current- detecting-sensitivity" and to consist the low pass filter. | RCLM fe Ai 4 CFIN 24r INPUT lg SMOOTHING Vee | COLLECTOR CAPACITOR + Ze Creo VOUT \2 HOW M51996A HO eh + TL CEM abe RNFI (b) Primary and secondary current Pano EMITTER Tene =RNF2 rows _r + Fig.25 Peripheral circuit diagram of CLM+ terminal To design the Rnei and Rerz,it is required to consider the influence of CLM+ terminal source current(liNcLM+), which value is in the range of 90 to 270pA. In order to be not influenced from these resistor paralleled value of RNFi and Rnr2,(RNFi/RNF2)is recommended to be less than 1000. The Rem should be the non-inductive resistor. (2)Over current limiting curve (a)In case of feed forward system Fig.26 shows the primary and secondary current wave-forms under the current limiting operation. At the typical application of pulse by pulse primary current detecting circuit,the secondary current depends on the primary current.As the peak value of secondary current is limited to specified value,the characteristics curve of output voltage versus output current become to the one as shown in Fig.27. Fig.26 Primary and secondary current waveforms under the current limiting operation condition on feed forward system OUTPUT VOLTAGE ________-+ OUTPUT CURRENT Fig.27 Over current limiting curve on feed forward system The demerit of the pulse by pulse current limiting system is that the output pulse width can not reduce to less than some value because of the delay time of low pass filter connected to the CLM+ terminal and propagation delay time Teocim from CLM+ terminal to output terminal of type M51996A.The typical TPDCLM+ is 100ns. As the frequency becomes higher,the delay time must be shorter.And as the secondary output voltage becomes higher,the dynamic range of on-duty must be wider;it means that it is required to make the on-duration much more narrower. So this system has the demerit at the higher oscillating frequency and higher output voltage applications. To prevent that the SOFT terminal is used to lower the frequency when the curve starts to become vertical. 2tENESAS (17 / 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL REG FiB M51996A Fig.28 Relationship between REG terminal and F/B terminal If the curve becomes vertical because of an excess current, the output voltage is lowered and no feedback current flows from feedback photo-coupler;the PWM comparator operates to enlarge the duty sufficiently,but the signal from the CLM+ section operates to make the pulse width narrower. Under the condition in which I2 in Fig.26 does not become 0,the output voltage is proportional to the product of the input voltage VIN(primary side voltage of the main transformer) and on duty.lf the bias winding is positive,Vcc is approximately proportional to VIN.The existance of feed back current of the photo-coupler is known by measuring the F/B terminal voltage which becomes less than 2VBE in the internal circuit of REG terminal and F/B terminal if the output current flows from the F/B terminal. Fig.29 shows an application example. Q1 is turned on when normal output voltage is controlled at a certain value. The SOFT terminal is clampedto a high-level voltage.|f the output voltage decreases and the curve starts to drop,no feed back current flows,Q1 is turned off and the SOFT terminal responds to the smoothed output voltage. It is recommended to use an Ri and R2 of 10kQ~30k0.An R3 of 20 to 100k2 and C of 1000pF to 8200pF should be used. To change the knee point of frequency drop,use the circuit in Fig.30. To have a normal SOFT start function in the circuit in Fig.29,use the circuit in Fig.31.It is recommended to use an R4 of 10kQ. BIAS WINDING OF ate THE MAIN TRANSFORMER + . Vi cc COLLECTOR Vee VOUT TO OUTPUT TRANSISTOR M51996A SOFT AS ie PHOTO-COUPLER FOR FEED BACK SIGNAL Fig.29 Current to lower frequency during over current SOFT SOFT VOUT VOUT TO MAKE THE KNEE POINT HIGH SOFT VOUT TO MAKE THE KNEE POINT LOW Fig.30 Method to control the knee point of frequency drop pe BIAS WINDING OF THE MAIN TRANSFORMER + . Veo COLLECTOR CVcc VOUT TO OUTPUT TRANSISTOR M519964 PHOTO-COUPLER FOR FEED BACK SIGNAL Fig.31 Circuit to use frequency drop during the over current and normal soft start 2tENESAS (18/ 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL (b)In case of fly back system The DC output voltage of SMPS depends on the Vcc voltage of type M51996A when the polarity of the third winding is negative and the system is fly back.So the operation of type M51996A will stop when the Vcc becomes lower than "Operation-stop voltage" of M51996A when the DC output voltage of SMPS decreases under specified value at over load condition. However,the M51996A will non-operate and operate intermittently,as the Vcc voltage rises in accordance with the decrease of Icc current. The fly back system has the constant output power characteristics as shown in Fig.32 when the peak primary current and the operating frequency are constant. Toavoid anincrease of the output current,the frequency is lowered when the DC output voltage of SMPS starts to drop using the SOFT terminal.Vcc is divided and is input to the SOFT terminal as shown in Fig.33,because the voltage in proportional to the output voltage is obtained from the bias winding.In this application example,the current flowing to R3 added to the start- up current.So please use high resistance or 100k to 200kQ for R3. The start-up current is not affected by R3 if R3 is connected to Cvec2 in the circuit shown in Fig.20. \, POINT THAT Vee VOLTAGE ORTHIRD WINDING - VOLTAGE DECREASES -- UNDER OPERATION-STOP VOLTAGE" DC OUTPUT VOLTAGE DC OUTPUT CURRENT Fig.32 Over current limitting curve on fly back system M51996A To photo-coupler for feed back signal Fig.33 Current to lower the frequency during the over current in the fly back system Output circuit (1)The output terminal characteristics at the Vcc voltage lower than the "Operation-stop" voltage TO MAIN TRANSFORMER Vout M51996A 100k RCLM Fig.34 Circuit diagram to prevent the MOS-FIT gate potential rising The output terminal has the current sink ability even though the Vcc voltage lower than the "Operation-stop" voltage or Vcc(stop) (It means that the terminal is "Output low state" and please refer characteristics of output low voltage versus sink current.) This characteristics has the merit not to damage the MOS-FIT at the stop of operation when the Vcc voltage decreases lower than the voltage of Vcc(stor),as the gate charge of MOS- FIT,which shows the capacitive load characteristics to the output terminalis drawn out rapidly. The output terminal has the draw-out ability above the Vcc voltage of 2V,however,lower than the 2V,it loses the ability and the output terminal potential may rise due to the leakage current. In this case, it is recommended to connect the resistor of 100kQ between gate and source of MOS-FIT as shown in Fig.34. (2)MOS-FIT gate drive power dissipation Fig.35 shows the relation between the applied gate voltage and the stored gate charge. In the region (1) ,the charge is mainly stored at Cas as the depletion is spread and Cep is small owing to the off-state of MOS-FIT and the high drain voltage. In the region '2) ,the Cap is multiplied by the "mirror effect" as the characteristics of MOS-FIT transfers from off-state to on- state. In the region (3) ,both the Cap and Cas affect to the characteristics as the MOS-FIT is on-state and the drain voltage is low. The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation between gate drive current ID and total gate charge Qasu is shown by following equation; IpD=QGsH fosc dcorstevsateotautesaatectocacneeteuel 1) Where fosc is switching frequency (19 / 22 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL As the gate drive current may reach up to several tenths milliamperes at 500kHz operation,depending on the size of MOS-FIT,the power dissipation caused by the gate current can not be neglected. In this case, following action will be considered to avoid heat up of type M51996A. 20 > % > 415 -_vps=80v Wi Vos=200 + <z _vbs=320V, A 3) | g fl 10 o 5 2: SOURCE ui 5 | | < J ID=4A Go | | 0 0 4 8 12 16 20 TOTAL STORED GATE CHARGE(nC) Fig.35 The relation between applied gate-source voltage and stored gate charge (1) To attach the heat sink to type M51996A (2) To use the printed circuit board with the good thermal conductivity (3) To use the buffer circuit shown next section (3)Output buffer circuit It is recommended to use the output buffer circuit as shown in Fig.36,when type M51996A drives the large capacitive load or bipolar transistor. VOUT M51996A Fig.36 Output buffer circuit diagram DET Fig.37 shows how to use the DET circuit for the voltage detector and error amplifier. For the phase shift compensation, it is recommended to connected the CR network between det terminal and F/B terminal. Jt Lt, C1 DETECTING G rf VOLTAGE a I Ri HOw M51996A DET & 3 LO.-- C4 = J = Fig.37 How to use the DET circuit for the voltage detector Fig.38 shows the gain-frequency characteristics between point B and point C shown in Fig.37. The G1,7 and 2 are given by following equations; R3 =i CD 0 RQ ceteeceeeeseeestensesees _~ _Ci+C2 At the start of the operation,there happen to be no output pulse due to F/B terminal current through C1 and C2,as the potential of F/B terminal rises sharply just after the start of the operation. Not to lack the output pulse,is recommended to connect the capacitor C4 as shown by broken line. Please take notice that the current flows through the R1 and R2 are superposed to Icc(START).Not to superpose,RA1 is connected to Cvcec2 as shown in Fig.20. sesssaserseses(10) 1 cientcrwel we ssevesersensee(12) * GAVDET (DC VOLTAGE GAIN) log G(dB) @ a ca a Log 4 Fig.38 Gain-frequency characteristics between point B and C shown in Fig.37 How to get the narrow pulse width during the start of operation Fig.39 shows how to get the narrow pulse width during the start of the operation.|f the pulse train of forcedly narrowed pulse- width continues too long,the misstart of operation may happen,so it is recommended to make the output pulse width narrow only for a few pulse at the start of operation.0.1pF is recommended for the C. 2tENESAS ( 20/ 22 )MITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL FIB Driver circuit for bipolar transistor M51996A When the bipolar transistor is used instead of MOS-FIT,the 1002 base current of bipolar transistor must be sinked by the negative base voltage source for the switching-off duration,in cepen: c order to make the switching speed of bipolar transistor fast one. | In this case,over current can not be detected by detecting resistor in series to bipolar transistor,so it is recommended to Fig.39 How to get the narrow pulse width use the CT (current transformer). . . For the low current rating transistor,type M51996A can drive it during the start of operation directly as shown in Fig.42. How to synchronize with external circuit Type M51996A has no function to synchronize with external COLLECTOR circuit,however,there is some application circuit for | synchronization as shown in Fig.40. Vee VOUT BIPOLAR M51996A TRANSISTOR M51996A GND EMITTER T-ON CF T-OFF ' ; C ) Fig.42 Driver circuit diagram (2) for bipolar transistor RON SYNCHRONOUS PULSE oO ee FE 0 a6 oO at oF ov Ww MM Sz ZO ou > >> - = ov w MINIMUM PULSE WIDTH OF MAXIMUM PULSE WIDTH OF FUSE NOUS SYNCHRONOUS PULSE Fig.40 How to synchronize with external circuit vy COLLECTOR 3 Vec Veco VOUT M51996A ated GND EMITTER (-2V to -5V) 9 9 | Fig.41 Driver circuit diagram (1) for bipolar transistor (21/ 22 ) 2tENESASMITSUBISHI (Dig./Ana. INTERFACE) M51996AP/FP SWITCHING REGULATOR CONTROL Attention for heat generation The maximum ambient temperature of type M51996A is +85C, however,the ambient temperature in vicinity of the IC is not uniform and varies place by place,as the amount of power dissipation is fearfully large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junction and the surface of IC package is 15C or less,when the IC junction temperature is measured by temperature dependency of forward voltage of pin junction,and IC package temperature is measured by "thermo- viewer" and also the IC is mounted on the "phenol-base" PC beard in normal atmosphere. So it is concluded that the maximum case temperature(surface temperature of !C) rating is 120C with adequate margin. 2tENESAS (22 / 22 )