S70FL01GS
1 Gbit (128 Mbyte), 3.0V, SPI Flash
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-98295 Rev. *I Revised February 03, 2016
Features
CMOS 3.0V Core
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot – power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles on any sector typical
Data Retention
– 20 Year Data Retention typical
Security Features
One Time Program (OTP) array of 1024 bytes
Block Protection
– Status Register bits to control protection against program
or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress 65 nm MirrorBit Technology with Eclipse
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range:
– Industrial (-40°C to +85°C)
– Industrial Plus (-40°C to +105°C)
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
– BGA-24, 8 6 mm
–5 5 ball (FAB024) footprint
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, refer to the discrete die datasheet provided in Table 1.
Table 1. Affected Documents/Related Documents
Document Title Publication Number
S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet 001-98284
Document Number: 001-98295 Rev. *I Page 2 of 16
S70FL01GS
Contents
1. Block Diagram.............................................................. 3
2. Connection Diagrams.................................................. 4
3. Input/Output Summary ................................................ 5
4. Device Operations ....................................................... 6
4.1 Programming ................................................................. 6
4.2 Simultaneous Die Operation.......................................... 6
4.3 Sequential Reads........................................................... 6
4.4 Sector/Bulk Erase .......................................................... 6
4.5 Status Registers............................................................. 6
4.6 Configuration Register ................................................... 6
4.7 Bank Address Register .................................................. 6
4.8 Security and DDR Registers .......................................... 6
4.9 Block Protection ............................................................. 6
5. Read Identification (RDID)........................................... 7
6. RESET# ......................................................................... 7
7. Versatile I/O Power Supply (VIO).................................. 7
8. DC Characteristics........................................................ 8
9. AC Test Conditions....................................................... 9
10. SDR AC Characteristics ............................................. 10
10.1 DDR AC Characteristics ............................................... 11
10.2 Capacitance Characteristics ......................................... 11
11 Ordering Information.................................................. 12
11.1 Valid Combinations....................................................... 12
12. SOIC 16 Physical Diagram ......................................... 13
12.1 SL3016 — 16-pin Wide Plastic Small Outline
Package (300-mil Body Width) ..................................... 13
13. FAB024 Physical Diagram.......................................... 14
13.1 FAB024 — 24-Ball BGA (8 x 6 mm) Package .............. 14
14. Revision History.......................................................... 15
Document Number: 001-98295 Rev. *I Page 3 of 16
S70FL01GS
1. Block Diagram
SI/IO0 SI/IO0
WP#/IO2 WP#/IO2
SO/IO1
HOLD#/IO3 HOLD#/IO3
VSS VSS
SCK SCK
CS#1 CS# VCC VCC
SI/IO0
WP#/IO2
HOLD#/IO3
VSS
SCK
CS#2 CS#
VCC
SO/IO1
SO/IO1
FL512S
Flash
Memory
FL512S
Flash
Memory
Document Number: 001-98295 Rev. *I Page 4 of 16
S70FL01GS
2. Connection Diagrams
Figure 2.1 16-Pin Plastic Small Outline Package (SO)
Figure 2.2 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View
Note:
1. VIO is not supported in the S70FL01GS device and is RFU. Refer to Section 7. for more details.
1
2
3
4
16
15
14
13
HOLD#/IO3
VCC
RESET#
DNU NC
VIO/RFU
SI/IO0
SCK
5
6
7
8
12
11
10
9WP#/IO2
VSS
DNU
DNU
DNU
CS2#
CS1#
SO/IO1
32541
CS2#DNU RFURESET#
B
D
E
A
C
VSSSCK RFUVCCDNU
RFUCS# RFUWP#/IO2DNU
SI/IO0SO/IO1 DNUHOLD#/IO3DNU
DNUDNU DNUVIO/RFUDNU
Document Number: 001-98295 Rev. *I Page 5 of 16
S70FL01GS
3. Input/Output Summary
Table 3.1 Signal List
Signal Name Type Description
RESET# Input
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used.
SCK Input Serial Clock.
CS# Input Chip Select.
SI / IO0 I/O Serial Input for single bit data commands or IO0 for Dual or Quad commands.
SO / IO1 I/O Serial Output for single bit data commands. IO1 for Dual or Quad commands.
WP# / IO2 I/O Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up
resistor and may be left unconnected in the host system if not used for Quad commands.
HOLD# / IO3 I/O
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The
signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad commands.
VCC Supply Core Power Supply.
VIO Supply Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer to
Section 7. for more details.
VSS Supply Ground.
NC Unused
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC
must not have voltage levels higher than VCC.
RFU Reserved
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use of the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
DNU Reserved
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
VIL. The signal has an internal pull-down resistor and may be left unconnected in the host
system or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do
not connect any host system signal to this connection.
Document Number: 001-98295 Rev. *I Page 6 of 16
S70FL01GS
4. Device Operations
4.1 Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
4.2 Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
4.3 Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the user desires to
sequentially read across the two die, data must be read out of the first die via CS1# and then read out of the second die via CS2#.
4.4 Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via a single command is
not supported due to the nature of the dual die stack. A Bulk Erase command must be issued for each die.
4.5 Status Registers
Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the Status Registers must be
managed separately. It is recommended that Status Register control bit settings of each die are kept identical to maintain
consistency when switching between die.
4.6 Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the Configuration Register control bits
must be managed separately. It is recommended that Configuration Register control bit settings of each die are kept identical to
maintain consistency when switching between die.
4.7 Bank Address Register
It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain consistency when switching
between die.
4.8 Security and DDR Registers
It is recommended that the bit settings for ASP Register, Password Register, PPB Lock Register, PPB Access Register, DYB
Access Register, and DDR Data Learning Register in each die are kept identical to maintain consistency when switching between
die.
4.9 Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and BPNV bits of each die must
be managed separately. By default, each die is configured to be protected starting at the top (highest address) of each array, but no
address range is protected. It is recommended that the Block Protection settings of each die are kept identical to maintain
consistency when switching between die. In addition, any update to the FREEZE bit must be managed separately for each die. If the
FREEZE bit is set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the FREEZE
bit set to 1.
Document Number: 001-98295 Rev. *I Page 7 of 16
S70FL01GS
5. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the two-byte device
identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the FL01GS dual die stack will have identical
identification data as the FL512S die, with the exception of the CFI data at byte 27h, as shown in Table 5.1.
6. RESET#
Note that the hardware RESET# input (pin 3 on the 16-pin SO package and ball A4 on the 5x5 BGA package) is bonded out and
active for the S70FL01GS device. For applications that do NOT require use of the RESET# pin, it is recommended to not use
RESET# for PCB routing channels that would cause the RESET# signal to be asserted Low (VIL). Doing so will cause the device to
reset to standby state. The RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not
used.
7. Versatile I/O Power Supply (VIO)
Note that the Versatile I/O (VIO) power supply (pin 14 on the 16-pin SO package and ball E4 on the 5x5 BGA package) is not
supported, and pin 14 and ball E4 are RFU (Reserved for Future Use) in the standard configuration of the S70FL01GS device.
Contact your local sales office to confirm availability with the VIO feature enabled.
Table 5.1 Product Group CFI Device Geometry Definition
Byte Data Description
27h 1Bh Device Size = 2N byte
Document Number: 001-98295 Rev. *I Page 8 of 16
S70FL01GS
8. DC Characteristics
This section summarizes the DC Characteristics of the device.
Notes:
1. Typical values are at TAI = 25°C and VCC = 3V.
2. Output switching current is not included.
3. Bulk Erase is on a per-die basis, not for the whole device.
Table 8.1 DC Characteristics
Symbol Parameter Test Conditions Min Typ (1) Max Unit
VIL Input Low Voltage -0.5 0.2 x VCC V
VIH Input High Voltage 0.7 x VCC V
CC + 0.4 V
VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min 0.15 x VCC V
VOH Output High Voltage IOH = –0.1 mA 0.85 x VCC V
ILI Input Leakage Current VCC = VCC Max, VIN = VIH or VIL ±4 µA
ILO Output Leakage Current VCC = VCC Max, VIN = VIH or VIL ±4 µA
ICC1 Active Power Supply
Current (READ)
Serial SDR @ 50 MHz
Serial SDR @ 133 MHz
Quad SDR @ 80 MHz
Quad SDR @ 104 MHz
Quad DDR @ 66 MHz
Outputs unconnected during read data
return (2)
18
36
50
61
75
mA
ICC2
Active Power Supply
Current (Page Program) CS# = VCC 100 mA
ICC3 Active Power Supply
Current (WRR) CS# = VCC 100 mA
ICC4
Active Power Supply
Current (SE) CS# = VCC 100 mA
ICC5
Active Power Supply
Current (BE) (3) CS# = VCC 100 mA
ISB (Industrial) Standby Current RESET#, CS# = VCC; SI, SCK = VCC
or VSS, Industrial Temp 70 200 µA
ISB (Industrial Plus) Standby Current RESET#, CS# = VCC; SI, SCK = VCC
or VSS, Industrial Plus Temp 70 300 µA
Document Number: 001-98295 Rev. *I Page 9 of 16
S70FL01GS
9. AC Test Conditions
Figure 9.1 Input, Output, and Timing Reference Levels
Figure 9.2 Test Setup
Notes:
1. Output High-Z is defined as the point where data is no longer driven.
2. Input slew rate: 1.5 V/ns.
3. AC characteristics tables assume clock and data signals have the same slew rate (slope).
4. DDR Operation.
Table 9.1 AC Measurement Conditions
Symbol Parameter Min Max Unit
CLLoad Capacitance 30
15 (4) pF
Input Rise and Fall Times 2.4 ns
Input Pulse Voltage 0.2 x VCC to 0.8 VCC V
Input Timing Ref Voltage 0.5 VCC V
Output Timing Ref Voltage 0.5 VCC V
VCC
+ 0.4V
0.7 x VCC
0.2 x VCC
- 0.5V
Timing Reference Level
0.5 x VCC
0.85 x VCC
0.15 x VCC
Input Levels Output Levels
Device
Under
Test
CL
Document Number: 001-98295 Rev. *I Page 10 of 16
S70FL01GS
10. SDR AC Characteristics
Notes:
1. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
2. Full VCC range (2.7 - 3.6V) and CL = 30 pF.
3. Regulated VCC range (3.0 - 3.6V) and CL = 30 pF.
4. Regulated VCC range (3.0 - 3.6V) and CL = 15 pF.
5. ±10% duty cycle is supported for frequencies
50 MHz.
6. Maximum value only applies during Program/Erase Suspend/Resume commands.
7. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the other for operations and data
to be valid.
Table 10.1 SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V)
Symbol Parameter Min Typ Max Unit
FSCK, R SCK Clock Frequency for READ and 4READ instructions DC 50 MHz
FSCK, C SCK Clock Frequency for single commands (4) DC 133 MHz
FSCK, C SCK Clock Frequency for the following dual and quad commands:
DOR, 4DOR, QOR, 4QOR, DIOR, 4DIOR, QIOR, 4QIOR DC 104 MHz
FSCK, QPP SCK Clock Frequency for the QPP, 4QPP commands DC 80 MHz
PSCK SCK Clock Period 1/ FSCK
tWH, tCH Clock High Time (5) 45% PSCK ns
tWL, tCL Clock Low Time (5) 45% PSCK ns
tCRT
, tCLCH Clock Rise Time (slew rate) 0.1 V/ns
tCFT
, tCHCL Clock Fall Time (slew rate) 0.1 V/ns
tCS (7) CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
50 ns
tCSS CS# Active Setup Time (relative to SCK) 3 ns
tCSH CS# Active Hold Time (relative to SCK) 3 3000 (6) ns
tSU Data in Setup Time 3 ns
tHD Data in Hold Time 2 ns
tV Clock Low to Output Valid
8.0 (2)
7.65 (3)
6.5 (4)
ns
tHO Output Hold Time 2 ns
tDIS Output Disable Time 0 8 ns
tWPS WP# Setup Time 20 (1) ns
tWPH WP# Hold Time 100 (1) ns
tHLCH HOLD# Active Setup Time (relative to SCK) 3 ns
tCHHH HOLD# Active Hold Time (relative to SCK) 3 ns
tHHCH HOLD# Non-Active Setup Time (relative to SCK) 3 ns
tCHHL HOLD# Non-Active Hold Time (relative to SCK) 3 ns
tHZ HOLD# Enable to Output Invalid 8 ns
tLZ HOLD# Disable to Output Valid 8 ns
Document Number: 001-98295 Rev. *I Page 11 of 16
S70FL01GS
10.1 DDR AC Characteristics
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
10.2 Capacitance Characteristics
Note:
1. For more information on capacitance, please consult the IBIS models.
Table 10.2 DDR AC Characteristics 66 MHz Operation
Symbol Parameter Min Typ Max Unit
FSCK, R SCK Clock Frequency for DDR READ instruction DC 66 MHz
PSCK, R SCK Clock Period for DDR READ instruction 15 ns
tWH, tCH Clock High Time 45% PSCK ns
tWL, tCL Clock Low Time 45% PSCK ns
tCS CS# High Time (Read Instructions) 10 ns
tCSS CS# Active Setup Time (relative to SCK) 3 ns
tCSH CS# Active Hold Time (relative to SCK) 3 ns
tSU IO in Setup Time 2 3000 (2) ns
tHD IO in Hold Time 2 ns
tVClock Low to Output Valid 0 6.5 (1) ns
tHO Output Hold Time 0 ns
tDIS Output Disable Time 8 ns
tLZ Clock to Output Low Impedance 0 8 ns
tIO_skew First IO to last IO data valid time 600 ps
Table 10.3 Capacitance
Parameter Test Conditions Min Max Unit
CIN Input Capacitance (applies to SCK, CS#1, CS#2, RESET#) 1 MHz 16 pF
COUT Output Capacitance (applies to All I/O) 1 MHz 16 pF
Document Number: 001-98295 Rev. *I Page 12 of 16
S70FL01GS
11 Ordering Information
The ordering part number is formed by a valid combination of the following:
Notes:
1. EHPLC = Enhanced High Performance Latency Code table.
2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer.
11.1 Valid Combinations
Table 11.1 lists the valid combinations configurations planned to be supported in volume for this device.
Note:
1. Package Marking omits the leading “S70” and package type.
S70FL 01G S AG M F I 0 1 1
Packing Type (Note 1)
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Sector Type)
1 = Uniform 256-kB sectors
Model Number
(Latency Type, Package Details, RESET# support)
0 = EHPLC, SO footprint
C = EHPLC, 5 x 5 ball BGA footprint with RESET#
Temperature Range
I = Industrial (-40°C to + 85°C)
V = Industrial Plus (-40°C to +105°C)
Package Materials
F = Lead (Pb)-free
H = Low-Halogen, Lead (Pb)-free
Package Type
B = 24-ball BGA 8 x 6 mm package, 1.00 mm pitch
M = 16-pin SO package
Speed
AG = 133 MHz
DP = 66 MHz DDR
DS = 80 MHz DDR
Device Technology
S = 0.065 µm MirrorBit Process Technology
Density
01G = 1 Gbit
Device Family
S70FL
Cypress Stacked Memory 3.0V-Only, Serial Peripheral Interface (SPI) Flash Memory
Table 11.1 S70FL01GS Valid Combinations Table
S70FL01GS Valid Combinations
Package Marking (1)
Base Ordering
Part Number
Speed
Option
Package and
Temperature
Model
Number Packing Type
S70FL01GS
AG MFI, MFV 01 0, 1, 3 FL01GS + A + (temp) + F + (Model Number)
DP FL01GS + D + (temp) + F + (Model Number)
AG BHI C1 0, 3 FL01GS + A + (temp) + H + (Model Number)
DP BHV FL01GS + D + (temp) + H + (Model Number)
Document Number: 001-98295 Rev. *I Page 13 of 16
S70FL01GS
12. SOIC 16 Physical Diagram
12.1 SL3016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)
Document Number: 001-98295 Rev. *I Page 14 of 16
S70FL01GS
13. FAB024 Physical Diagram
13.1 FAB024 — 24-Ball BGA (8 x 6 mm) Package
Document Number: 001-98295 Rev. *I Page 15 of 16
S70FL01GS
14. Revision History
Document History Page
Document Title: S70FL01GS, 1 Gbit (128 Mbyte), 3.0V, SPI Flash
Document Number: 001-98295
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** BWHA 11/06/2012 Initial release
*A BWHA 04/25/2013
Global: Datasheet designation updated from Advance Information to Preliminary
DC Characteristics: DC Characteristics table: changed Max value of ILI, ILO,
ICC1, and ISB
*B BWHA 05/16/2013 SOIC 16 Physical Diagram: Updated package nomenclature from S03016 to
SL3016
*C BWHA 08/22/2013 Valid Combinations: Valid Combinations table: added MFV
DC Characteristics: DC Characteristics table: added ISB (Automotive)
*D BWHA 11/08/2013 Global: Datasheet designation updated from Preliminary to Full Production
*E BWHA 03/19/2014
Features: Packages (all Pb-free): added BGA-24, 8 x 6 mm
Connections Diagrams: Added figure: 24-Ball BGA, 5 x 5 Ball Footprint
(FAB024), Top View
Ordering Information: Added options to: Model Number, Package Materials,
Package Type, and Speed
Valid Combinations: Added option to S70FL01GS Valid Combinations Table
SDR AC Characteristics: SDR AC Characteristics (Single Die Package, VCC =
2.7V to 3.6V) table: updated tv Min
DDR AC Characteristics:Updated DDR AC Characteristics 66 MHz Operation
table
Capacitance Characteristics: Capacitance table: updated Max values and
removed note
*F BWHA 11/07/2014 Valid Combinations: Added DP Speed Option for BGA 5x5 package
*G BWHA 04/21/2015 Valid Combinations: Added BHV option
*H 4871631 BWHA 08/24/2015
Updated to Cypress template.
Changed Automotive Temperature Range to Industrial Plus Temperature Range
in Features and Section 4..
*I 5123878 BWHA 02/03/2016 Updated General Description.
Document Number: 001-98295 Rev. *I Revised February 03, 2016 Page 16 of 16
Cypress®, Spansion®, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, HyperBus™, HyperFlash™ and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp.
All products and company names mentioned in this document may be the trademarks of their respective holders.
© Cypress Semiconductor Corporation, 2012-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
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Use may be limited by and subject to the applicable Cypress software license agreement.
S70FL01GS
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