MT9V022IA7ATM - Micron Technology, Inc.

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Applications

Features

MT9V022I77ATM (mono)

MT9V022I77ATC (color)

1/3-Inch, Wide-VGA CMOS Digital Image Sensor

Rugged Specs and High Quality for Scene-Understanding

and Smart Imaging Applications Micron’s MT9V022 has specifi-

cally been designed to support the demanding interior and exterior

needs of automotive imaging, which makes it ideal for a wide vari-

ety of scene understanding and smart imaging applications in real-

world environments. This wide-VGA CMOS image sensor features

DigitalClarity™, Micron’s breakthrough, low-noise CMOS imaging

technology that achieves CCD image quality (based on signal-to-

noise ratio and low-light sensitivity) while maintaining the inher-

ent size, cost, and integration advantages of CMOS.

• Micron’s DigitalCla rity™

CMOS imaging technolog y

• Double-buffered global shutter

photodiode pixels

• Simultaneous integration and

readout

• Enhanced Near-IR

performance (NIR QE >35%)

• Progr essive or interlaced

readout modes

• Linear or high dynamic range

pixel response

• >99% global shutter efficiency

• Register lock capability

• User-Programmable window

size within frame

• 2 x 2 and 4 x 4 pixel averag ing

of the full resolution

• ADC On-Chip (10-bit linear or

12-bit to 10-bit companding

mode)

• Auto exposure control (AEC)

• Auto gain control (AGC)

• Black level calibration (BLC)

• User-Programmable regional

gain and exposure weighting

(25 regions)

• Support for 4 unique serial

control register IDs to control

multiple imagers on the same

bus

• Master/Slave dual sensor

operation for stereoscopic,

foveal, or hyperspectral

operation

• On-Chip digi ta l thermo m eter

• Data output formats:

– Single sensor mode: 10-bit

parallel/stand-alone or 8-

bit or 10-bit serial LVDS

– Dual sensor mode:

Interspersed 8-bit serial

LVDS

•Automotive

• Unattended surveillance

• Stereo vision

•Security

•Smart vision

•Automation

•Video as input

•Machine vision

Key Parameters

Optical format 1/3-inch

Active imager size 4.51mm(H) x 2.88mm(V)

5.35mm Diagonal

Active pixels 752H x 480V

Pixel size 6.0µm x 6.0µm

Color filter array Monochrome or color RGB

Bayer pattern

Shutter type Double-Buffered global

shutter TrueSNAP™

Maximum data rate

Master clock 26.6 Mp/s

26.6 MHz

Full resolution 752 x 480

Frame rate 60 fps (at full resolution)

ADC resolution 10-bit

Responsivity 4.8 V/lux-sec (550nm)

Dynamic range >55dB linear;

>80dB–100dB in HiDy

Mode

Supply voltage 3.3V +0.3V (all supplies)

Power consumption <320mW at maximum

data rate; 100µW standby

current

Operating

temperature –4 0°C to +85°C

Packaging 52-ball IBGA, automotive-

qualified; wafer or die

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

General Description

The MT9V022 active imaging pixel array is 752H x 480V. It incorporates sophisticated

camera functions on-chip, such as averaging 2 x 2 and 4 x 4, to impro ve SNR when oper-

ating in smaller resolutions, as well as windowing and column and row mirroring. It is

programmable through a simple two-wire serial interface. The MT9V022 pixel response

can be configured for either linear light response with >55dB of dynamic range or for

high dynamic range response with as much as 100dB of dynamic range.

The MT9V022 can be operated in its default mode or be programmed by the user for

frame size, exposure, gain setting, and ot her parameters. The default mode outputs a

wide-VGA-sized image at 60 frames per second (fps). An on-ch ip analog-to-digital con-

verter (ADC) provides 10 bits per pixel. The user can alternatively enable 12-bit resolu-

tion companded to 10 bits for small signals, enabling more accurate digitizati on fo r

darker areas in the image.

In addition to a traditional, parallel logic output, the MT9V022 also features a serial low-

voltage differential signaling (LVDS) output.

The sensor can be operated in stereo-camer a mode, where the sensor, designated as a

stereo-master, is able to merge the data from itself and the stereo-slave sensor into one

serial LVDS stream.

The sensor is desi gned to operate in a wide temp erature range (–40°C to +85°C). A built-

in digital thermometer allows the host to read the temperature through the two-wire

serial interface.

Figure 1: Block Diagram

Operational Modes

The MT9V022 works in master, sna psh ot, or slave mode. In master mode, the sensor

generates the readout timing. There are two possible operati on methods for master

mode: simultaneous and sequen tial. I n simult aneous master mod e, the exposur e pe riod

occurs during readout. The exposure and readout occ ur in parallel rather than sequen-

tially, making this the fastest mode of operation.

In sequential master mode, the exposure period is followed by readout, and the frame

rate changes as the integration time changes.

In snapshot mode, the start of the integration period is determin ed by the externally-

applied EXPOSURE pulse that the user inputs to the MT9V022. The sensor in snapshot

mode can capture a single image or a sequence of images.

Parallel

Video

Data Out

Serial

I/O

Control Register

ADCs

Active-Pixel

Sensor (APS)

Array

752H x 480V Timing and Control

Digital Processing

Analog Processing

Serial Video

LVDS Out

Slave Video LVDS In

(for stereo applications only)

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Pixel Data Format and Pixel Array Structure

In slave mode, the sensor accepts both external integration and readout controls.

The integration time is programmed through the two-wire serial interface during master

or snapshot modes, or controlled via an externally generated control signal during slave

mode.

LVDS Serial Output (Stand-Alone and Stereoscopic Operation)

The LVDS interface allows for the stre aming of sensor data serially to a standard off-the

shelf deser ializer up to 8 meters away from the sens or. The LVDS serial output could

either be data from a single sensor (stand-alone) or stre am-merged data from a pair

(master and slave) of synchronized MT9V022 devices.

The pixels (and controls) are packeted—12-bit packets for stand-alone mode and 18-bit

packets (2 frame bits and 8 data bits from each sensor) fo r st ereoscopi c mode. All serial

signals (clock and data) is LVDS.

An LVDS connection overview for a single MT9V02 2 and for stereoscopic pair of

MT9V022 devices is shown in Figure 2.

Figure 2: LVDS Stereoscopic Topology

Pixel Data Format and Pixel Array Structure

The MT9V022 pixel array is configured of 782 columns by 492 ro ws, as sho wn in Figur e3.

The left 26 columns and th e top 8 rows of pixels are optically black and can be us ed to

monitor the black level. The black row data is used internally for the automatic black

level adjustment.

X1 8/X12 PLL

SENSOR

DS92LV16

8 8

PIXEL PIXEL

FROM FROM

SLAVE MASTER

SENSOR

SLAVE MASTER

1. PLL in non-bypass mode 1. PLL in bypass mode

2. PLL in x 18 mode (stereoscopy)

LV and FV are embedded in the data stream

26.6 MHz

Osc.

LVDS

SER_DATAIN

LVDS

BYPASS_CLKIN

LVDS

SER_DATAIN

LVDS

BYPASS_CLKIN

LVDS

SHIFT_CLKOUT

LVDS

SER_DATAOUT

5m (maximum)

26.6 MHz

Osc.

LVDS

SER_DATAOUT LVDS

SHIFT_CLKOUT

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Output Data Format

Figure 3: Pixel Array Description and Color Pattern Detail

Output Data Format

The MT9V022 image data can be read out in a progressive scan or in interlaced scan

mode. Valid image data is surrounded by horizontal and vertical blanking, as shown in

Figure 4.

Figure 4: Spatial Illustration of Image Readout: Interlaced Scan (left) and Progr essive Scan (right)

(782,492)

2 dummy

columns

2 dummy rows

8 dark, 1 light dummy rows

(0,0)

26 dark, 1 light

dummy columns

Pixel

(2,9)

Column Readout Direction

Row Readout Direction

Dummy Pixel

P4,1 P4,2 P4,3.....................................P4,n-1 P4,n

P6,0 P6,1 P6,2.....................................P6,n-1 P6,n

00 00 00 .................. 00 00 00

Pm-2,0 Pm-2,2.....................................Pm-2,n-2 Pm-2,n

Pm,2 Pm,2.....................................Pm,n-1 Pm,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

00 00 00 ............................................................................................. 00 00 00

VALID IMAGE - Even FieldHORIZONTAL

BLANKING

VERTICAL BLANKING

P5,1 P5,2 P5,3.....................................P5,n-1 P5,n

P7,0 P7,1 P7,2.....................................P7,n-1 P7,n

Pm-3,1 Pm-3,2.....................................Pm-3,n-1 Pm-3,n

Pm,1 Pm,1.....................................Pm,n-1 Pm,n

VALID IMAGE - Odd Field

FIELD BLANKING

0,0

0,1

0,2

.....................................P

0,n-1

0,n

1,0

1,1

1,2

.....................................P

1,n-1

1,n

00 00 00 .................. 00 00 00

m-1,0

m-1,1

.....................................P

m-1,n-1

m-1,n

m,0

m,1

.....................................P

m,n-1

m,n

00 00 00 .................. 00 00 00

00 00 00 ..................................... 00 00 00

VALID IMAGEHORIZONTAL

BLANKING

VERTICAL BLANKINGVERTICAL/HORIZONTAL

BLANKING

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Output Data Timing

The data output of the MT9V022 is synchronized with the PIXCLK output. When

LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.

Figure 5: Row Timing and FRAME_VALID/LINE_VALID Signals

Figure 6: Timing Example of Pixel Data

Note: The parameters P1, A, Q, and P2 are defined in Table 1 on page 5.

Serial Bus Description

The MT9V022 control r egis ters ar e written to and read from the two-wir e serial interface

bus. The MT9V022 is a serial interface slave with four possible IDs (0x90, 0x98, 0xB0, and

0xB8) determined by S_CTRL_ADR0 and S_CTRL_ADR1 inputs.

Data is transferred into the MT9V022 and out through the serial data (SDATA) line. The

SDATA line is pulled up to VDD off-chip by a 1. 5kΩ resistor. Either the slave or master

device can pull the SDATA line down. The serial interface protocol determines which

device is allowed to pull the SDATA line down at any given time.

inadvertent, noise-triggered two-wir e serial interface WRITE to the sensor. The user may

lock all registers or only the read mode register. The read mode register controls the

image orientation, and an uninte nded flip to the imag e c a n caus e se rious results.

Table 1: Frame Time

Parameter Description Pixel Clock Master Clocks Time Units

A Active data time 752 752 28.02 µs

P1 Frame start blanking 71 71 2.66 µs

P2 Frame end blanking 23 23 0.86 µs

Q Horizontal blanking 94 94 3.52 µs

A + Q Row time 846 846 31.72 µs

V Vertical blanking 38,074 38,074 1.43 ms

Nrows Frame valid time 406,080 406,080 15.23 ms

F Total frame time 444,154 444,154 16.66 ms

P1 A Q A Q AP2

. . .

Number of master clocks

FRAME_VALID

LINE_VALID

PIXCLK

DOUT(9:0)

. . . .

(9:0) P1

(9:0) P2

(9:0) P3

(9:0) P4

(9:0) Pn-1

(9:0) Pn

(9:0)

Valid Image DataBlankingBlanking

. . . .

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Output Data Timing

High Dynamic Range

The MT9V022 pixel light response can be option all y configured to achieve intra-scene

dynamic range as high as 100dB. High dynamic range is achieved by controlling the

slopes of a thre e-segment, piecewise , linear pixel r esponse , as illustrated in F igur e 7. The

slope of the thre e segments can be programme d via the serial i nterface.

Figure 7: High Dynamic Range

Variable ADC Resolution

By default, the MT9V022 ADC has a linear response with 10-bit resolution. The ADC can

also be configured to have a 12- to 10-bit companding response, as illustrated in

Figure7. This mode allows higher ADC resolution (12 bits) for low-level signals (shadow

details) and lower ADC resolution (9 bits) for high-level signals (highlight details. )

Figure 8: 12- to 10-Bit ADC Companding Chart

Light

Output

High Dynamic

Range Response

Linear Response

12-Bit Resolution (0:255 0:255)

11-Bit Resolution (256:511 256:383)

10-Bit Resolution (512:2047 384:767)

256

512

768

1,024

4,0962,048

1,024

256

10-Bit

Codes

12-Bit

Codes

9-Bit Resolution (2048:4095 768:1,023)

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Output Data Timing

Automatic Gain Control (AGC) and Automatic Exposure Control (AEC)

The integrated AEC/AGC unit is responsible for ensuring that optimal auto settings of

exposure and (analog) gain are computed and updated every frame.

When the AGC or AEC are enabled, the MT9V022 measures current scene luminosity

and desired output luminosity by accumulating a histogram of pixel values while read-

ing out a frame. The desired exposure and gain are then calculated and applied for the

subsequent frame.

Pixel Clock Speed The pixel clock speed is same as the master clock of 26.66 MHz by default. However,

when column binning 2 or 4 is enabled, the pixel clock speed will be reduced by half or

one-fourth of the master clock speed, respectively.

Gain Settings

Analog Gain The analog gain range supported in the MT9V022 is 1X–4X with a step size of 6.25

percent.

Digital Gain I n the MT9V022, the user either may apply a single gain value for the entir e arr ay or they

may divide the image into 25 tiles (Figure 9) through the two-wire serial interface and

apply digital gain individually to each tile.

The coordinates and digital gain (0.25 - 3.75X) of each tile may be individually pro-

grammed via the two-wire serial interface. This feature should help improve pulling

detail out of regions of an image that are either dark, or lighter than the rest of the scene

without affecting the rest of the scene.

Figure 9: Digital Gain Tiled Sample

Read Mode Options

Column and Row Flip To ease mounting orientation issues, the MT9V022 column and row readout order can

be independently reversed via the two-wire serial interface. The image will then be rep-

resented correctly regardless of camera orientation.

0/5

1/5

2/5

3/5

5/5

0/5

1/5

2/5

3/5

4/5

5/5

x0_y0 x1_y0 x4_y0

x0_y1 x1_y1 x4_y1

x0_y2 x1_y2 x4_y2

x0_y3 x1_y3 x4_y3

x0_y4 x1_y4 x4_y4

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Pixel Binning In addition to windowing mode— in which sm al le r resolution (CIF, QCIF, user-selected

size frame) is obtained by selecting a small window from the sensor array—the MT9V022

pro vi des the abil ity to show the entir e image captured by the pixel arr ay with smaller res-

olution by pixel binning. Pixel binning is performed by combining signals from adjacent

pixels by averaging. There are two options: binning 2 and binning 4.

When binning 2 is on, 4 pixel signals from 2 adjacent rows and columns are combined.

In the case of binning 4 mode, 16 pixels are combined from 4 adjacent rows and col-

umns. Binning may be used in conjunction with image flip. The binning operation

incr eases SNR but decr eases r esolution. Enabl ing ro w bin2 and ro w bin4 im pro ves fr ame

rate by 2x and 4x, respectively. Column binning does not increase the frame rate.

Power Reduction Modes

Standby Control The user may set the sensor in standby mode by setting STANDBY HIGH. Once the

MT9V022 detects that STANDBY is asserted, it completes the current frame before dis-

abling the digital logic, internal clocks, and analog power enable signal. To release the

sensor out from the standby mode, reset STANDBY back to LOW.

Monitor Mode Control In this mode, the MT9V022 first captures a programmable number of frames and then

goes into a sleep period for five minutes. During the sleep period, all of the analog ci r-

cuitry of the MT9V022 is powered-down and only a small portion of the digital circuitry

re mains powered.

Thermometer The MT9V022 thermometer circuit provides a digital output vs. temperature that is

accessible via the serial interface. The resolution of the thermometer is approximately 1

LSB per degree Celsius.

Electrical Specifications

Table 2: DC Electrical Characteristics

VPWR = 3.3V ±0.3V; TA = Ambient = 25°C

Symbol Definition Condition Min Typ Max Unit

VIH Input high voltag e VPWR -0.5 – VPWR +0.3 V

VIL Input low voltage -0.3 – 0.8 V

IIN Input leakage current No pull-up resistor;

VIN = VPWR or VGND -15.0 – 15.0 μA

VOH Output high vol tage IOH = -4.0mA VPWR -0.7 – – V

VOL Output low voltag e IOL = 4.0mA ––0.3V

IOH Output high current VOH = VDD - 0.7 -9.0 – – mA

IOL Output low current VOL = 0.7 ––9.0mA

VAA Analog pow er su pp ly Default settings 3.0 3.3 3.6 V

IPWRA Analog supply current Default settings – 35.0 60.0 mA

VDD Digital power supply Default settings 3.0 3.3 3.6 V

IPWRD Digital supply current Default settings, CLOAD= 10pF —35.060mA

VAAPIX Pixel array power supply Def a ul t se t t ings 3.0 3.3 3.6 V

IPIX Pixel supply current Default settings 0.5 1.4 3.0 mΑ

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

VLVDS LVDS power supply Default settings 3.0 3.3 3.6 V

ILVDS LVDS supply current Default settings 11.0 13.0 15.0 mA

IPWRA

Standby Analog standby supply current STDBY = VDD 234μA

IPWRD

Standby

Clock Off

Digital standby supply current

with clock off STDBY = VDD, CLKIN = 0 MHz 124μA

IPWRD

Standby

Clock On

Digital standby supply current

with clock on STDBY= VDD, CLKIN = 27 MHz –1.05–mA

LVDS Driver DC Specifications

|VOD| Output differential voltage

RLOAD = 100

Ω ±1%

250 – 400 mV

|DVOD| Change in VOD between

complementary output states ––50mV

VOS Output offset voltage 1.0 1.2 1.4 mV

DVOS Change in VOS between

complementary output states ––35mV

IOS Output current when driver

shorted to ground ±10 ±12 mA

IOZ Output current when driver is

tri-state ±1±10 μA

LVDS Receiver DC Specifications

VIDTH+ Input differential | VGPD| <925mV -100 – 100 mV

Iin Input current ––

±20 μA

Table 3: AC Electrical Characteristics

VPWR = 3.3V ±0.3V; TA = Ambient = 25°C; Output Load = 10pF

Symbol Definition Condition Min Typ Max Unit

Clock duty cycle 45.0 50.0 55.0 %

tR Input clock rise time 125ns

tF Input clock fall time 125ns

tPLHPSYSCLK to PIXCLK propagation delay CLOAD = 10pF 3 7 11 ns

tPD PIXCLK to valid DOUT(9:0) propagation delay CLOAD = 10pF -2 0 2 ns

tSD Data setup time 14 16 – ns

tHD Data hold time 14 16 –

tPFLR PIXCLK to LINE_VALID propagation delay CLOAD = 10pF -2 0 2 ns

tPFLF PIXCLK to FRAME_VALID prop ag ati on delay CLOAD = 10pF -2 0 2 ns

Table 2: DC Electrical Characteristics (continued)

VPWR = 3.3V ±0.3V; TA = Ambient = 25°C

Symbol Definition Condition Min Typ Max Unit

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Note: Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Figure 10: Propagation Delays for PIXCLK and Data Out Signals

Figure 11: Propagation Delays for FRAME_VA LID and LINE_VALID Signals

Table 4: Absolute Maximum Ratings

Symbol Parameter Min Max Unit

VSUPPLY Power supply voltage (all supplies) -0.3 4.5 V

ISUPPLY Total power supply current –200mA

IGND Total ground current –200mA

VIN DC input voltage -0.3 VDDQ + 0.3 V

VOUT DC output voltage -0.3 VDDQ + 0.3 V

TSTGNote: Storage t emperatu r e -40 +125 °C

tPD

tPLHP

tHD

tSD

SYSCLK

PIXCLK

DOUT(9:0)

PIXCLK

tPFLF

tPFLR

FRAME_VALID

LINE_VALID

PIXCLK

FRAME_VALID

LINE_VALID

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Figure 12: Quantum Efficiency – Color and Monochrome

Figure 13: Typical Configuration (Connection) – Parallel Output Mode

Note: LVDS signals are to be left floating.

350 450 550 650 750 850 950 1,050

Wavelength (n m)

Quantum Efficiency (%)

Blue

Gr een ( B )

Gr een ( R)

Red

MONO

SYSCLK LINE_VALID

FRAME_VALID

PIXCLK

OUT

(9:0)

STANDBY

EXPOSURE

RSVD

S_CTRL_ADR0

S_CTRL_ADR1

LVDSGND

LED_OUT

ERROR

DATA

SCLK

RESET#

LVDS

GND

VAAPIX

Master Clock

0.1μF

To Controller

STANDBY from

Controller or

Digital GND

Two-Wire

Serial Interface

VAAPIX

To LED output

10K

1.5K

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Figure 14: 52-Ball IBGA Package

Table 5: Ball Descriptions

Only pins DOUT0 through DOUT9 may be tri-stated.

52-Ball IBGA

Numbers Symbol Type Description Notes

H7 RSVD Input Connect to DGND.1

D2 SER_DATAIN_N Input Serial data in for stereoscopy (differential negative).

Tie to 1KΩ pull-up (to 3.3V) in non-stereoscop y mode.

D1 SER_DATAIN_P Input Serial data in for stereoscopy (differential positive). T ie

to DGND in non-stereoscopy mode.

C2 BYPASS_CLKIN_N Input Input bypass shift-CLK (differential ne gative). Tie to

1KΩ pull-up (to 3.3V) in non-stereoscopy mode.

C1 BYPASS_CLKIN_P Input Input bypass shift-CLK (differential positive). Tie to

DGND in non-stereoscopy mode.

H3 EXPOSURE Input Rising edge starts exposure in slave mode.

H4 SCLK Input Two-wire serial interface clock. Connect to VDD with

1.5K resistor even when no other two-wire serial

interface peripheral is attached.

H6 OE Input DOUT enable pad, active HIGH. 2

G7 S_CTRL_ADR0 Input Two-wire serial interface slave address bit 3.

H8 S_CTRL_ADR1 Input Two-wire serial interface slave address bit 5.

G8 RESET# Input Asynchronous reset. All registers assume defaults.

F8 STANDBY Input Shut down sensor operation for power saving.

SER_

SHFT_

BYPASS

SER_

VDD

DOUT7

FRAME

LINE_

SER_

SHFT_

LVDS

DGND

STLN_

EXPO-

SURE

VDD

LVDS

BYPASS

SER_

DOUT5

DOUT6

DOUT8

DOUT9

VDD

SDATA

SCLK

DOUT0

DOUT1

DGND

AGND

LED_

DOUT2

DOUT4

AGND

VAA

S_CTRL_

RSVD

SYS-

PIXCLK

STFRM_

ERROR

Top View

(Ball Down)

OUT

_VALID

DATAOUT

LVDS

_CLKIN

GND

DATAIN

CLKOUT

DATAIN

VALID

DATAOUT

CLKOUT

GND

OUT

LVDSCLK

OUT

_ADR1

ADR0

_CLKIN

DOUT3

VAAPIX

VAA

STAND-

RESET#

S_CTRL

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MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Notes: 1. Pin H7 (RSVD) must be tied to GND .

2. Output Enable (OE) tri-states signals DOUT0-DOUT9. No other signals are tri-stated with OE.

3. No connect. These pins must be left floating for proper operation.

A5 SYSCLK Input Master clock (26.6 MHz).

G4 SDATA I/O Two-wire ser ia l inte rface data. Connect to VDD with

1.5K resistor even when no other two-wire serial

interface peripheral is attached.

G3 STLN_OUT I/O Output in master mode—start line sync to drive slave

chip in-phase; input in slave mode.

G5 STFRM_OUT I/O Output in master mode—start frame sync to drive a

slave chip in-phase; input in slave mode.

H2 LINE_VALID Output Asserted when DOUT data is valid.

G2 FRAME_VALID Output Asserted when DOUT data is valid.

E1 DOUT5 Output Parallel pixel data output 5.

F1 DOUT6 Output Parallel pixel data output 6.

F2 DOUT7 Output Parallel pixel data output 7.

G1 DOUT8 Output Parallel pixel data output 8

H1 DOUT9 Output Parallel pixel data output 9.

H5 ERROR Output Error detected. Directly OR with STEREO ERROR FLAG

and PIXEL ERROR FLAG.

G6 LED_OUT Output LED strobe output.

B7 DOUT4 Output Parallel pixel data output 4.

A8 DOUT3 Output Parallel pixel data output 3.

A7 DOUT2 Output Parallel pixel data output 2.

B6 DOUT1 Output Parallel pixel data output 1.

A6 DOUT0 Output Parallel pixel data output 0.

B5 PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this

clock.

B3 SHFT_CLKOUT_N Output Output shift CLK (differential negative).

B2 SHFT_CLKOUT_P Output Output shift CLK (differential positive).

A3 SER_DATAOUT_N Output Serial data out (differential negative).

A2 SER_DATAOUT_P Output Serial data out (differential positive).

B4, E2 VDD Supply Digital power 3.3V.

C8, F7 VAA Supply Analog power 3.3V.

B8 VAAPIX Supply Pixel power 3.3V.

A1, A4 VDDLVDS Supply Dedicated power for LVDS pads.

B1, C3 LVDSGND Ground Dedicated GND for LVDS pads.

C6, F3 DGND Ground Digital GND.

C7, F6 AGND Ground Analog GND.

E7, E8, D7, D8 NC NC No connect. 3

Table 5: Ball Descriptions (continued)

Only pins DOUT0 through DOUT9 may be tri-stated.

52-Ball IBGA

Numbers Symbol Type Description Notes

PDF:09005aef8201ffc3/Source: 09005aef81ff2525 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Electrical Specifications

Figure 15: 52-Ball IBGA Package Outline Drawing

Note: All dimensions in millimeters.

SEATING

PLANE

9.000 ±0.075

3.50

4.50 ±0.05

OPTICAL

AREA

1.50 MAX

0.40

(FOR REFERENCE ONLY)

0.90 (FOR REFERENCE ONLY)

5.50

FIRST

CLEAR

PIXEL

FUSES

7.00

1.849

1.999

4.500 ±0.075

OPTICAL CENTER

BALL A1

CORNER

4.90

4.500 ±0.075

OPTICAL

CENTER

1.00 TYP

9.000 ±0.075

0.375 ±0.075

0.525 ±0.050

0.125 (FOR REFERENCE ONLY)

7.00

3.50

0.10 AA

BALL A1 ID

BALL A1

BALL A8

52X Ø0.55

DIMENSIONS APPLY

TO SOLDER BALLS

POST REFLOW. THE

PRE-REFLOW

DIAMETER IS 0.50.

ENCAPSULANT: EPOXY IMAGE SENSOR DIE

LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS

SUBSTRATE MATERIAL: PLASTIC LAMINATE

SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag

OR 96.5% Sn, 3% Ag, 0.5% Cu

NON SOLDER MASK DEFINED BALL PADS: Ø0.40

MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1º

MAXIMUM TILT OF OPTICAL AREA RELATIVE TO PACKAGE EDGE : 50 MICRONS.

MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 50 MICRONS.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Lin e: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product

development and data characterization sometimes occur.

MT9V022: 1/3-Inch Wide-VGA Digital Image Sensor

Ordering Information

PDF:09005aef8201ffc3/Source: 09005aef81ff2525 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Ordering Information

Production Parts

Demo Kits A demonstration kit is also available for evaluation purposes and consists of:

• Micr o n Imaging De mo2 Camera Board

• Micron Sensor Head with lens

• USB2.0 Cable

•Software CD

• Demo User Manual picture from Demo Kit

Headboards

Note: For customers who already have a demo kit with the demo 2 camera board (USB2.0), only

order the head board.

MT9V022I77ATM Monochrome Pb packaged parts

MT9V022IA7ATM Monochrome Pb-Free packaged parts

MT9V022I77ATC Color Pb packaged parts

MT9V022IA7ATC Color Pb-Free packaged parts

MT9V022I77ATMD ES Monochrome Demo Kit

MT9V022I77ATCD ES Color Demo Kit

MT9V022I77ATMH ES Monochrome Headboard

MT9V022I77ATCH ES Color Head bo ard