4 MHz, 7 nV/Hz, Low Offset and Drift, High Precision Amplifiers ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet PIN CONNECTION DIAGRAMS Offset voltage: 25 V maximum at 25C (B grade, 8-lead SOIC, single/ dual) 50 V maximum at 25C (A grade, 8-lead SOIC, single/ dual) 50 V maximum at 25C (A grade, 14-lead SOIC, quad) Offset voltage drift: 0.25 V/C maximum (B grade, 8-lead SOIC, single/dual) 0.55 V/C maximum (A grade, 8-lead SOIC, single/dual) 0.75 V/C maximum (A grade, 14-lead SOIC, quad) MSL1 rated Low input bias current: 1 nA maximum at TA = 25C Low voltage noise density: 6.9 nV/Hz typical at f = 1000 Hz CMRR, PSRR, and AV > 120 dB minimum Low supply current: 400 A per amplifier typical Wide gain bandwidth product: 3.9 MHz at 5 V Dual-supply operation: Specified at 5 V to 15 V Operates at 2.5 V to 15 V Unity gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 0.5 V typical Temperature hysteresis: 1 V typical APPLICATIONS 1 -IN 2 +IN 3 V- 4 ADA4077-1 TOP VIEW (Not to Scale) 8 NIC 7 V+ 6 OUT 5 NIC NIC = NOT INTERNALLY CONNECTED. Figure 1. ADA4077-1, 8-Lead SOIC and 8-Lead MSOP -IN A 2 ADA4077-2 +IN A 3 TOP VIEW (Not to Scale) V- 4 8 V+ 7 OUT B 6 -IN B 5 +IN B 10238-001 OUT A 1 OUT A 1 -IN A 2 14 OUT D 13 -IN D +IN A 3 ADA4077-4 12 +IN D V+ 4 TOP VIEW (Not to Scale) 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C 10238-202 Figure 2. ADA4077-2, 8-Lead MSOP and 8-Lead SOIC Figure 3. ADA4077-4, 14-Lead TSSOP and 14-Lead SOIC The ADA4077-1 and ADA4077-2 are available in an 8-lead SOIC package, including the B grade, and in an 8-lead MSOP (A grade only). The ADA4077-4 is offered in a 14-lead TSSOP and a 14-lead SOIC package. Process control front-end amplifiers Optical network control circuits Instrumentation Precision sensors and controls Precision filters 200 180 GENERAL DESCRIPTION VSY = 5V SOIC Unlike other amplifiers, the ADA4077-1/ADA4077-2/ ADA4077-4 have an MSL1 rating that is compliant with the most stringent of assembly processes, and they are specified over the extended industrial temperature range from -40C to +125C for the most demanding operating environments. 140 120 100 80 60 40 20 VOS (V) 10238-103 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 MORE Applications for this amplifier include sensor signal conditioning (such as thermocouples, resistance temperature detectors (RTDs), strain gages), process control front-end amplifiers, and precision diode power measurement in optical and wireless transmission systems. The ADA4077-1/ADA4077-2/ADA4077-4 are useful in line powered and portable instrumentation, precision filters, and voltage or current measurement and level setting. NUMBER OF AMPLIFIERS 160 The single ADA4077-1, dual ADA4077-2, and quad ADA4077-4 amplifiers feature extremely low offset voltage and drift, and low input bias current, noise, and power consumption. Outputs are stable with capacitive loads of more than 1000 pF with no external compensation. Rev. E NIC 10238-101 FEATURES Figure 4. Offset Voltage Distribution Table 1. Evolution of Precision Devices by Generation Op Amp Single Dual Quad First OP07 Second OP77 Third OP177 Fourth OP1177 OP2177 OP4177 Fifth AD8677 Sixth ADA4077-1 ADA4077-2 ADA4077-4 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Test Circuit ...................................................................................... 21 General Description ......................................................................... 1 Theory of Operation ...................................................................... 22 Pin Connection Diagrams ............................................................... 1 Applications Information .............................................................. 23 Revision History ............................................................................... 2 Output Phase Reversal ............................................................... 23 Specifications..................................................................................... 3 Low Power Linearized RTD ...................................................... 23 Electrical Characteristics, 5 V .................................................. 3 Proper Board Layout .................................................................. 23 Electrical Characteristics, 15 V ................................................ 5 Long-Term Drift ......................................................................... 24 Absolute Maximum Ratings ....................................................... 7 Temperature Hysteresis ............................................................. 24 Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 25 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 27 Pin Configurations and Function Descriptions ........................... 8 REVISION HISTORY 5/2017--Rev. D to Rev. E Changes to Features Section, Applications Section, and Figure 1 ... 1 Added Maximum Reflow Temperature (MSL1 Rating) Parameter and Note 2,Table 4; Renumbered Sequentially .......... 7 Changes to Figure 5, Figure 6, and Table 6 ................................... 8 Changes to Figure 24 and Figure 27 ............................................. 13 Changes to Figure 29, Figure 30, Figure 31, Figure 32, Figure 33, and Figure 34 ................................................................................... 14 Changes to Figure 66 ...................................................................... 20 Added Test Circuit Section and Figure 69; Renumbered Sequentially ..................................................................................... 22 Added Long-Term Drift Section, Temperature Hysteresis Section, Figure 72, Figure 73, and Figure 74 ................................................. 24 Changes to Ordering Guide .......................................................... 27 10/2016--Rev. C to Rev. D Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Changes to Figure 19 ...................................................................... 12 Changes to Figure 23 and Figure 26 ............................................. 13 Changes to Figure 29, Figure 30, Figure 32, and Figure 33 ....... 14 6/2015--Rev. B to Rev. C Change to Figure 63 ....................................................................... 18 1/2014--Rev. A to Rev. B Added ADA4077-1 ............................................................. Universal Changes to Features Section ............................................................1 Added Figure 1; Renumbered Sequentially ...................................1 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................4 Added Figure 5, Figure 6, and Table 6; Renumbered Sequentially ........................................................................................7 Changes to Figure 17, Figure 20, and Figure 21 ......................... 11 Changes to Figure 65...................................................................... 19 Added Figure 67 and Figure 68 .................................................... 19 Changes to Output Phase Reversal Section and Figure 70 ....... 21 Changes to Ordering Guide .......................................................... 24 10/2013--Rev. 0 to Rev. A Added ADA4077-4 ............................................................. Universal Changes to Features, General Description, and Figure 1 .............1 Deleted Figure 2; Renumbered Sequentially .................................1 Added Figure 2...................................................................................1 Changes to Table 2.............................................................................3 Changes to Table 3.............................................................................4 Changes to Table 4.............................................................................6 Added Figure 6, Figure 7, and Table 7; Renumbered Sequentially ........................................................................................8 Changes to Typical Performance Characteristics Section ...........9 Changes to Figure 65...................................................................... 20 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 23 10/2012--Revision 0: Initial Version Rev. E | Page 2 of 27 Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 SPECIFICATIONS ELECTRICAL CHARACTERISTICS, 5 V VSY = 5.0 V, VCM = 0 V, TA = 25C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage ADA4077-1/ADA4077-2 B Grade, SOIC Symbol Test Conditions/Comments Min Typ Max Unit 10 25 65 50 105 90 220 V V V V V V 50 105 120 220 V V V V 0.1 0.25 0.5 0.25 0.55 1.2 V/C V/C V/C 0.4 0.5 -0.4 0.75 1.2 +1 +1.5 +0.5 +1 +3 5 70 V/C V/C nA nA nA nA V dB dB dB dB dB pF G 10 22 0.05 V V V V mA mA VOS -40C < TA < +125C A Grade, SOIC 15 -40C < TA < +125C A Grade, MSOP 50 -40C < TA < +125C ADA4077-4 A Grade, SOIC 15 -40C < TA < +125C A Grade, TSSOP Offset Voltage Drift ADA4077-1/ADA4077-2 B Grade, SOIC A Grade, SOIC A Grade, MSOP ADA4077-4 A Grade, SOIC A Grade, TSSOP Input Bias Current 15 VOS/T -40C < TA < +125C -40C < TA < +125C IB -40C < TA < +125C Input Offset Current IOS -40C < TA < +125C Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain Av Input Capacitance Input Resistance OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier CINCM RIN VOH VOL IOUT ISC ZOUT PSRR ISY VCM = -3.8 V to +3 V VCM = -3.8 V to +3 V, -40C < TA < +85C VCM = -3.8 V to +2.8 V, 85C < TA < 125C RL = 2 k, VO = -3.0 V to +3.0 V -40C < TA < +125C Common mode Common mode -1 -1.5 -0.5 -1 -3.8 122 120 120 121 120 IL = 1 mA -40C < TA < +125C IL = 1 mA -40C < TA < +125C VDROPOUT < 1.6 V TA = 25C f = 1 kHz, AV = +1 3.8 3.7 VS = 2.5 V to 18 V -40C < TA < +125C VO = 0 V -40C < TA < +125C 123 120 Rev. E | Page 3 of 27 +0.1 140 130 -3.8 -3.7 128 400 450 650 dB dB A A ADA4077-1/ADA4077-2/ADA4077-4 Parameter DYNAMIC PERFORMANCE Slew Rate Settling Time to 0.1% Gain Bandwidth Product Unity-Gain Crossover -3 dB Closed-Loop Bandwidth Phase Margin Total Harmonic Distortion Plus Noise NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density MULTIPLE AMPLIFIERS CHANNEL SEPARATION Data Sheet Symbol Test Conditions/Comments SR tS GBP UGC -3 dB M THD + N RL = 2 k VIN = 1 V step, RL = 2 k, AV = -1 VIN = 10 mV p-p, RL = 2 k, AV = +100 VIN = 10 mV p-p, RL = 2 k, AV = +1 AV = +1, VIN = 10 mV p-p, RL = 2 k VIN = 10 mV p-p, RL = 2 k, AV = +1 VIN = 1 V rms, AV = +1, RL = 2 k, f = 1 kHz 1.2 3 3.9 3.9 5.9 55 0.004 V/s s MHz MHz MHz Degrees % en p-p en 0.1 Hz to 10 Hz f = 1 Hz f = 100 Hz f = 1000 Hz f = 1 kHz f = 1 kHz, RL = 10 k 0.25 13 7 6.9 0.2 -125 V p-p nV/Hz nV/Hz nV/Hz pA/Hz dB in CS Rev. E | Page 4 of 27 Min Typ Max Unit Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 ELECTRICAL CHARACTERISTICS, 15 V VSY = 15 V, VCM = 0 V, TA = 25C, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage ADA4077-1/ADA4077-2 B Grade, SOIC Symbol Test Conditions/Comments Min Typ Max Unit 10 35 65 50 105 90 220 V V V V V V 50 105 120 220 V V V V VOS -40C < TA < +125C A Grade, SOIC 15 -40C < TA < +125C A Grade, MSOP 50 -40C < TA < +125C ADA4077-4 A Grade, SOIC 15 -40C < TA < +125C A Grade, TSSOP 15 -40C < TA < +125C Offset Voltage Drift ADA4077-1/ADA4077-2 B Grade, SOIC A Grade, SOIC A Grade, MSOP ADA4077-4 A Grade, SOIC A Grade, TSSOP Input Bias Current VOS/T -40C < TA < +125C -40C < TA < +125C -40C < TA < +125C 0.1 0.25 0.5 0.25 0.55 1.2 V/C V/C V/C -40C < TA < +125C -40C < TA < +125C 0.4 0.5 -0.4 0.75 1.2 +1 +1.5 +0.5 +1 +13 V/C V/C nA nA nA nA V dB dB IB -40C < TA < +125C Input Offset Current IOS -40C < TA < +125C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain ADA4077-1/ADA4077-2 (SOIC, MSOP) CMRR Input Resistance OUTPUT CHARACTERISTICS Output Voltage High +0.1 150 Av ADA4077-4 (SOIC, TSSOP) Input Capacitance VCM = -13.8 V to +13 V -40C < TA < +125C -1 -1.5 -0.5 -1 -13.8 132 130 CINDM CINCM RIN VOH Output Voltage Low VOL Output Current Short-Circuit Current Closed-Loop Output Impedance IOUT ISC ZOUT RL = 2 k, VO = -13.0 V to +13.0 V -40C < TA < +125C RL = 2 k, VO = -13.0 V to +13.0 V -40C < TA < +125C Differential mode Common mode Common mode 125 120 122 120 IL = 1 mA -40C < TA < +125C IL = 1 mA -40C < TA < +125C VDROPOUT < 1.2 V TA = 25C f = 1 kHz, AV = +1 13.8 13.7 Rev. E | Page 5 of 27 130 3 5 70 dB dB dB dB pF pF G 10 22 0.05 V V V V mA mA 130 -13.8 -13.7 ADA4077-1/ADA4077-2/ADA4077-4 Parameter POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier Data Sheet Symbol Test Conditions/Comments Min Typ PSRR VS = 2.5 V to 18 V -40C < TA < +125C VO = 0 V -40C < TA < +125C 123 120 128 ISY 400 Max Unit 500 650 dB dB A A DYNAMIC PERFORMANCE Slew Rate Settling Time to 0.01% Settling Time to 0.1% Gain Bandwidth Product Unity-Gain Crossover -3 dB Closed-Loop Bandwidth Phase Margin Total Harmonic Distortion Plus Noise SR ts ts GBP UGC -3 dB M THD + N RL = 2 k VIN = 10 V p-p, RL = 2 k, AV = -1 VIN = 10 V p-p, RL = 2 k, AV = -1 VIN = 10 mV p-p, RL = 2 k, AV = +100 VIN = 10 mV p-p, RL = 2 k, AV = +1 AV = +1, VIN = 10 mV p-p, RL = 2 k VIN = 10 mV p-p, RL = 2 k, AV = +1 VIN = 1 V rms, AV = +1, RL = 2 k, f = 1 kHz 1.2 16 10 3.6 3.9 5.5 58 0.004 V/s s s MHz MHz MHz Degrees % NOISE PERFORMANCE Voltage Noise Voltage Noise Density en p-p en Current Noise Density MULTIPLE AMPLIFIERS CHANNEL SEPARATION in CS 0.1 Hz to 10 Hz f = 1 Hz f = 100 Hz f = 1000 Hz f = 1 kHz f = 1 kHz, RL = 10 k 0.25 13 7 6.9 0.2 -125 V p-p nV/Hz nV/Hz nV/Hz pA/Hz dB Rev. E | Page 6 of 27 Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Input Voltage Input Current1 Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Maximum Reflow Temperature (MSL1 Rating)2 Lead Temperature, Soldering (10 sec) Electrostatic Discharge (ESD) Human Body Model (HBM)3 Field Induced Charge Device Model (FICDM)4 Rating 36 V VSY 10 mA VSY Indefinite -65C to +150C -40C to +125C -65C to +150C 260C 300C JA is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 8-Lead MSOP 8-Lead SOIC 14-Lead TSSOP 14-Lead SOIC ESD CAUTION 6 kV 1.25 kV The input pins have clamp diodes to the power supply pins and to each other. Limit the input current to 10 mA or less whenever input signals exceed the power supply rail by 0.3 V. 2 IPC/JEDEC J-STD-020 applicable standard. 3 ESDA/JEDEC JS-001-2011 applicable standard. 4 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard. 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 7 of 27 JA 190 158 240 115 JC 44 43 43 36 Unit C/W C/W C/W C/W ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet 1 -IN 2 +IN 3 V- 4 ADA4077-1 TOP VIEW (Not to Scale) 8 NIC NIC 1 7 V+ -IN 2 6 OUT +IN 3 5 NIC V- 4 NIC = NOT INTERNALLY CONNECTED. 10238-205 NIC NIC 7 V+ 6 OUT 5 NIC Figure 6. ADA4077-1 Pin Configuration, 8-Lead SOIC (R-8) Table 6. ADA4077-1 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC Mnemonic NIC -IN +IN V- OUT V+ TOP VIEW (Not to Scale) 8 NIC = NOT INTERNALLY CONNECTED. Figure 5. ADA4077-1 Pin Configuration, 8-Lead MSOP (RM-8) Pin No. 1, 5, 8 2 3 4 6 7 ADA4077-1 10238-105 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Description Not internally connected. Inverting Input. Noninverting Input. Negative Supply Voltage. Output. Positive Supply Voltage. Rev. E | Page 8 of 27 ADA4077-1/ADA4077-2/ADA4077-4 OUT A 1 8 V+ -IN A 2 ADA4077-2 7 OUT B -IN A 2 ADA4077-2 +IN A 3 TOP VIEW (Not to Scale) 6 -IN B +IN A 3 5 +IN B TOP VIEW (Not to Scale) 10238-004 V- 4 OUT A 1 V- 4 Table 7. ADA4077-2 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC Mnemonic OUT A -IN A +IN A V- +IN B -IN B OUT B V+ V+ 7 OUT B 6 -IN B 5 +IN B Figure 8. ADA4077-2 Pin Configuration, 8-Lead SOIC Figure 7. ADA4077-2 Pin Configuration, 8-Lead MSOP Pin No. 1 2 3 4 5 6 7 8 8 10238-005 Data Sheet Description Output Channel A. Inverting Input Channel A. Noninverting Input Channel A. Negative Supply Voltage. Noninverting Input Channel B. Inverting Input Channel B. Output Channel B. Positive Supply Voltage. Rev. E | Page 9 of 27 OUT A 1 -IN A 2 14 OUT D 13 -IN D Data Sheet OUT A 1 14 OUT D -IN A 2 13 -IN D ADA4077-4 12 +IN D TOP VIEW (Not to Scale) 11 V- 10 +IN C +IN A 3 +IN A 3 ADA4077-4 12 +IN D V+ 4 TOP VIEW (Not to Scale) 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C -IN B 6 9 -IN C OUT B 7 8 OUT C OUT B 7 8 OUT C V+ 4 10238-206 +IN B 5 Figure 9. ADA4077-4 Pin Configuration, 14-Lead TSSOP Figure 10. ADA4077-4 Pin Configuration, 14-Lead SOIC Table 8. ADA4077-4 Pin Function Descriptions, 14-Lead TSSOP and 14-Lead SOIC Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic OUT A -IN A +IN A V+ +IN B -IN B OUT B OUT C -IN C +IN C V- +IN D -IN D OUT D 10238-207 ADA4077-1/ADA4077-2/ADA4077-4 Description Output Channel A. Negative Input Channel A. Positive Input Channel A. Positive Supply Voltage. Positive Input Channel B. Negative Input Channel B. Output Channel B. Output Channel C. Negative Input Channel C. Positive Input Channel C. Negative Supply Voltage. Positive Input Channel D. Negative Input Channel D. Output Channel D. Rev. E | Page 10 of 27 Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 TYPICAL PERFORMANCE CHARACTERISTICS 140 120 VSY = 5V MSOP NUMBER OF AMPLIFIERS 60 40 100 80 60 40 20 20 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 MORE VOS (V) Figure 14. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = 15 V Figure 11. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = 5 V 200 200 VSY = 5V SOIC 180 VSY = 15V SOIC 180 160 NUMBER OF AMPLIFIERS 160 120 100 80 60 140 120 100 80 60 20 0 0 10238-144 VOS (V) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 MORE 40 20 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 MORE 40 VOS (V) 10238-009 140 Figure 15. Offset Voltage (VOS) Distribution, VSY = 15 V Figure 12. Offset Voltage (VOS) Distribution, VSY = 5 V 15 20 VSY = 15V VSY = 5V 10 10 5 VOS (V) 15 5 0 0 -5 -5 -10 -10 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) -15 -50 10238-210 VOS (V) 10238-003 VOS (V) 10238-006 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 MORE 0 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 13. Offset Voltage (VOS) vs. Temperature, VSY = 5 V Figure 16. Offset Voltage (VOS) vs. Temperature, VSY = 15 V Rev. E | Page 11 of 27 10238-213 NUMBER OF AMPLIFIERS 80 NUMBER OF AMPLIFIERS VSY = 15V MSOP 120 100 ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet 70 50 VSY = 15V, 5V SOIC, A GRADE VSY = 15V, 5V TSSOP AND MSOP, A GRADE 45 60 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 40 35 30 25 20 15 50 40 30 20 10 10 5 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 10238-130 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 TCVOS (V/C) TCVOS (V/C) Figure 17. TCVOS Distribution ([TSSOP and MSOP, A Grade) 10238-008 0 0 Figure 20. TCVOS Distribution (SOIC, A Grade) 10 140 VSY = 15V, 5V SOIC, B GRADE 120 NUMBER OF AMPLIFIERS VOS (V) 5 0 -5 100 80 60 40 5 10 15 20 25 30 35 VSY (V) 0 TCVOS (V/C) Figure 18. Offset Voltage (VOS) vs. Power Supply Voltage (VSY) Figure 21. TCVOS Distribution (SOIC, B Grade) 100 0.6 VS = 15V -15V V CM +15V 80 10238-308 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 -10 10238-134 20 60 0.4 20 ISY (mA) VOS (V) 40 0 -20 0.2 -40C +25C +85C +125C -60 AVERAGE AVERAGE +3 AVERAGE -3 -100 -15 -13 -11 -9 -7 -5 -3 -1 1 VCM (V) 3 5 7 9 11 13 15 0 10238-419 -80 Figure 19. Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 15 V VO = 0V 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 VSY (V) 10238-218 -40 Figure 22. Supply Current per Amplifier (ISY) vs. Power Supply Voltage (VSY) Rev. E | Page 12 of 27 Data Sheet 4.15 14.15 VOH = 1mA VOL = 1mA VOH = 1mA VOL = 1mA 14.10 OUTPUT VOLTAGE SWING (V) 4.10 4.05 4.00 3.95 3.90 3.85 14.05 14.00 13.95 13.90 13.85 13.80 3.80 -25 0 25 50 75 100 125 TEMPERATURE (C) 13.75 -50 10238-423 3.75 -50 -25 25 50 75 125 Figure 23. Output Voltage Swing vs. Temperature, VSY = 5 V Figure 26. Output Voltage Swing vs. Temperature, VSY = 15 V 350 400 VSY = 15V 350 150 0 -0.1 10238-016 INPUT BIAS CURRENT (nA) -0.2 -1 0 10238-013 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 0 -0.9 0 -1.0 50 -0.3 100 50 -0.4 100 200 -0.5 150 250 -0.6 200 300 -0.7 250 -0.8 NUMBER OF AMPLIFIERS 300 INPUT BIAS CURRENT (nA) Figure 24. Input Bias Current Distribution, VSY = 5 V Figure 27. Input Bias Current Distribution, VSY = 15 V 0 0 VSY = 5V VSY = 15V -0.1 -0.1 -0.2 -0.2 +IB -IB -IB IB (nA) -0.3 -0.4 -0.3 -0.4 -0.5 -0.5 -0.6 -0.6 -0.7 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 25. Input Bias Current (IB) vs. Temperature, VSY = 5 V -0.7 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) Figure 28. Input Bias Current (IB) vs. Temperature, VSY = 15 V Rev. E | Page 13 of 27 10238-017 +IB 10238-014 IB (nA) 100 TEMPERATURE (C) VSY = 5V NUMBER OF AMPLIFIERS 0 10238-426 VS = 15V VS = 5V -0.9 OUTPUT VOLTAGE SWING (V) ADA4077-1/ADA4077-2/ADA4077-4 ADA4077-1/ADA4077-2/ADA4077-4 100k 1k VSY = 5V -40C T +125C 10 100 100k OUTPUT DROPOUT VOLTAGE (mV) = -40C = +25C = +85C = +125C 1k 100 0.001 0.01 0.1 1 10 100 = -40C = +25C = +85C = +125C 1k 50 50 0 0 -50 OPEN-LOOP GAIN (dB) 100 -100 -100 100k 1M 10M 0.1 1 10 100 150 GAIN = 0pF PHASE = 0pF 100 VSY = 5V AV = -1 RL = 2k 0.01 150 GAIN = 200pF PHASE = 200pF PHASE MARGIN (Degrees) GAIN = 100pF PHASE = 100pF VSY = 15V -40C T +125C Figure 33. Output Dropout Voltage vs. ILOAD, Source Current, VSY = 15 V GAIN = 100pF PHASE = 100pF GAIN = 200pF PHASE = 200pF 100 100 50 50 0 0 -50 VSY = 15V AV = -1 RL = 2k -50 -100 -100 -150 100M 10238-227 OPEN-LOOP GAIN (dB) GAIN = 0pF PHASE = 0pF 100 ILOAD (mA) 150 150 10 10k 100 0.001 Figure 30. Output Dropout Voltage vs. ILOAD, Source Current, VSY = 5 V -150 10k ISOURCE ISOURCE ISOURCE ISOURCE VSY = 5V -40C T +125C ILOAD (mA) -50 1 Figure 32. Output Dropout Voltage vs. ILOAD, Sink Current, VSY = 15 V 10238-430 OUTPUT DROPOUT VOLTAGE (mV) ISOURCE ISOURCE ISOURCE ISOURCE 0.1 ILOAD (mA) Figure 29. Output Dropout Voltage vs. ILOAD, Sink Current, VSY = 5 V 10k 0.01 FREQUENCY (Hz) Figure 31. Open-Loop Gain and Phase Margin vs. Frequency, VSY = 5 V 10238-433 1 ILOAD (mA) VSY = 15V -40C T +125C -150 10k PHASE MARGIN (Degrees) 0.1 1k 100k 1M 10M -150 100M FREQUENCY (Hz) Figure 34. Open-Loop Gain and Phase Margin vs. Frequency, VSY = 15 V Rev. E | Page 14 of 27 10238-230 0.01 10k 100 0.001 10238-429 100 0.001 ISINK = -40C ISINK = +25C ISINK = +85C ISINK = +125C 10238-432 ISINK = -40C ISINK = +25C ISINK = +85C ISINK = +125C OUTPUT DROPOUT VOLTAGE (mV) OUTPUT DROPOUT VOLTAGE (mV) 10k Data Sheet Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 140 133 VSY = 15V VSY = 5V VSY = 5V TO 15V 132 120 131 100 CMRR (dB) PSRR (dB) 130 129 128 127 80 60 40 126 20 -25 0 25 50 75 100 125 TEMPERATURE (C) 0 100 10238-035 124 -50 1k 10k 100k 1M Figure 35. PSRR vs. Temperature, VSY = 5 V to 15 V Figure 38. CMRR vs. Frequency, VSY = 5 V and VSY = 15 V 120 120 VSY = 5V VSY = 15V 100 100 80 80 PSRR (dB) PSRR (dB) 10M FREQUENCY (Hz) 10238-029 125 60 PSRR- 40 60 PSRR- 40 PSRR+ 20 20 0 0 1k 10k 100k 1M 10M FREQUENCY (Hz) -20 100 10238-034 -20 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 36. PSRR vs. Frequency, VSY = 5 V 10238-037 PSRR+ Figure 39. PSRR vs. Frequency, VSY = 15 V 152 159 151 VSY = 15V VSY = 5V 158 150 149 157 CMRR (dB) 147 146 145 156 155 144 143 154 141 -50 -25 0 25 50 TEMPERATURE (C) 75 100 125 153 -50 -25 0 25 50 TEMPERATURE (C) 75 100 Figure 40. CMRR vs. Temperature, VSY = 15 V Figure 37. CMRR vs. Temperature, VSY = 5 V Rev. E | Page 15 of 27 125 10238-033 142 10238-030 CMRR (dB) 148 ADA4077-1/ADA4077-2/ADA4077-4 50 50 VSY = 5V G = 100 40 Data Sheet 30 G = 10 20 CLOSED-LOOP GAIN (dB) 10 G=1 0 -10 -20 G = 10 20 10 G=1 0 -10 -20 -40 -50 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 10238-028 -40 -50 1k 1M 10M 100M Figure 44. Closed-Loop Gain vs. Frequency, VSY = 15 V 1k 1k VSY = 15V VSY = 5V 100 10 AV = +10 1 ZOUT () AV = +100 10 AV = +1 0.01 0.01 10k 100k 1M 10M FREQUENCY (Hz) 10238-036 0.1 1k 0.001 100 AV = +1 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 45. Output Impedance (ZOUT) vs. Frequency, VSY = 15 V Figure 42. Output Impedance (ZOUT) vs. Frequency, VSY = 5 V 10238-040 VOLTAGE (1V/DIV) VSY = 5V VIN = 1V p-p AV = +1 RL = 2k CL = 300pF TIME (100s/DIV) AV = +10 1 0.1 0.001 100 AV = +100 10238-039 100 ZOUT () 100k FREQUENCY (Hz) Figure 41. Closed-Loop Gain vs. Frequency, VSY = 5 V VOLTAGE (0.2V/DIV) 10k 10238-031 -30 -30 0V VSY = 15V VIN = 4V p-p AV = +1 RL = 2k CL = 300pF TIME (100s/DIV) Figure 43. Large Signal Transient Response, VSY = 5 V Figure 46. Large Signal Transient Response, VSY = 15 V Rev. E | Page 16 of 27 10238-043 CLOSED-LOOP GAIN (dB) 30 0V VSY = 15V G = 100 40 ADA4077-1/ADA4077-2/ADA4077-4 0.20 0.15 0.15 0.10 0.10 0.05 0.05 0 -0.05 VSY = 5V VIN = 100mV p-p AV = +1 LOAD = 2k||1000pF -0.10 -0.15 -0.20 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 -0.05 -0.15 0.5 0.6 0.7 0.8 TIME (ms) -0.20 -0.2 -0.1 0 0.2 0.1 0.3 0.4 0.5 0.6 0.7 0.8 TIME (ms) Figure 47. Small Signal Transient Response, VSY = 5 V Figure 50. Small Signal Transient Response, VSY = 15 V 0.5 35 0 30 -0.5 25 0.5 INPUT INPUT (V) -1.0 5 3 1 OUTPUT -1 TIME (10s/DIV) 20 VSY = 15V VIN = 200mV p-p AV = -100 LOAD = 10k -1.5 -2.0 15 10 -2.5 5 -3.0 0 -3.5 -10 -5 0 10 20 30 40 50 60 70 80 10238-248 VSY = 5V AV = -100 VIN = 200mV RL = 10k OUTPUT VOLTAGE (V) 90 TIME (s) INPUT VOLTAGE (V) Figure 51. Positive Overload Recovery, VSY = 15 V 0.5 INPUT 0 -0.5 0.5 INPUT 0 -0.5 OUTPUT -1 VSY = 5V AV = -100 VIN = 200mV RL = 10k -3 -5 TIME (10s/DIV) 0 -5 VSY = 15V AV = -100 VIN = 200mV RL = 10k Figure 49. Negative Overload Recovery, VSY = 5 V -15 TIME (10s/DIV) Figure 52. Negative Overload Recovery, VSY = 15 V Rev. E | Page 17 of 27 -10 OUTPUT VOLTAGE (V) OUTPUT OUTPUT VOLTAGE (V) 1 10238-047 INPUT VOLTAGE (V) Figure 48. Positive Overload Recovery, VSY = 5 V 10238-051 -0.5 OUTPUT (V) 0 10238-046 INPUT VOLTAGE (V) VSY = 15V VIN = 100mV p-p AV = +1 LOAD = 2k||1000pF -0.10 10238-247 VOLTAGE (V) 0.20 10238-344 VOLTAGE (V) Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet 40 40 35 30 OVERSHOOT (%) 25 20 15 OS+ OS- 10 20 15 OS+ OS- 10 10n LOAD CAPACITANCE (F) 0 1p 100p 1n Figure 56. Small Signal Overshoot vs. Load Capacitance, VSY = 15 V 0.25 0.04 0.20 0.03 0.15 0.02 0.10 0 INPUT (V) OUTPUT (V) 0.05 0.01 0.05 0 -0.01 VSY = 15V VIN = 10V p-p RL = 2k 10238-251 -0.02 -0.03 TIME (1s/DIV) Figure 57. Positive 0.1% Settling Time, VSY = 15 V 0.25 0.04 0.20 VSY = 15V VIN = 10V p-p RL = 2k 0.03 0 INPUT (V) 0.01 0.15 0.10 OUTPUT (V) 0.02 0.05 0 -0.01 -0.05 -0.02 -0.10 -0.03 10238-252 INPUT (V) -0.10 -0.15 0.05 TIME (1s/DIV) -0.05 TIME (1s/DIV) Figure 54. Positive 0.1% Settling Time, VSY = 5 V VSY = 5V VIN = 1V p-p RL = 2k 10n LOAD CAPACITANCE (F) Figure 53. Small Signal Overshoot vs. Load Capacitance, VSY = 5 V VSY = 5V VIN = 1V p-p RL = 2k 10p OUTPUT (V) 1n 10238-254 100p 10238-250 10p 10238-253 5 5 INPUT (V) 25 Figure 55. Negative 0.1% Settling Time, VSY = 5 V -0.15 TIME (1s/DIV) Figure 58. Negative 0.1% Settling Time, VSY = 15 V Rev. E | Page 18 of 27 OUTPUT (V) OVERSHOOT (%) 30 0 1p VSY = 15V RL = 2k 10238-255 35 VSY = 5V RL = 2k Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 100 VSY = 15V VSY = 5V AV = +1 VSY = 5V VSY = 15V 90 VOLTAGE NOISE CORNER (nV/Hz) VOLTAGE NOISE DENSITY (nV/Hz) 1k 100 10 80 70 60 50 40 30 20 1k 10k 100k 1M 10M FREQUENCY (Hz) 0 10238-053 100 Figure 59. Voltage Noise Density vs. Frequency, VSY = 5 V and VSY = 15 V 0 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (Hz) 10238-153 10 1 10 Figure 62. Voltage Noise Corner vs. Frequency, VSY = 15 V and VSY = 5 V 100 1 VSY = 15V VSY = 5V 10 THD + NOISE (%) 0.01 BANDWIDTH = 80kHz BANDWIDTH = 500kHz BANDWIDTH = 80kHz BANDWIDTH = 500kHz 1 0.1 0.01 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 0.0001 10 100 1k 10k 100k FREQUENCY (Hz) Figure 60. THD + Noise vs. Frequency, VSY = 5 V Figure 63. THD + Noise vs. Frequency, VSY = 15 V VSY = 15V VSY = 5V TIME (1s/DIV) Figure 64. 0.1 Hz to 10 Hz Noise, VSY = 15 V Figure 61. 0.1 Hz to 10 Hz Noise, VSY = 5 V Rev. E | Page 19 of 27 10238-058 INPUT VOLTAGE (50nV/DIV) 10238-054 TIME (1s/DIV) 10238-158 0.0001 10238-155 0.001 INPUT VOLTAGE (50nV/DIV) THD + NOISE (%) 0.1 ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet 100 200 VSY = 15V -100 IB (pA) -200 -300 -400 -500 -600 -700 -900 -1000 -20 -15 -10 -5 0 5 10 15 20 VCM (V) 1 0.1 10238-219 MEAN +3 MEAN MEAN -3 -800 10 1 10 100 1k 10k 100k FREQUENCY (Hz) Figure 65. Input Bias Current (IB) vs. Common-Mode Voltage (VCM) 10238-267 0 CURRENT NOISE DENSITY (pA/Hz) VSY = 15V -15V VCM +15V TA = 25C 100 Figure 67. Current Noise Density, VSY = 15 V 0 100 VSY = 5V -60 -80 -100 -120 VSY = 15V VIN = 10V p-p AV = +1 RL = 10k -140 -160 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 66. Channel Separation, VSY = 15 V (See Figure 69) 10 1 0.1 1 10 100 1k 10k FREQUENCY (Hz) Figure 68. Current Noise Density, VSY = 5 V Rev. E | Page 20 of 27 100k 10238-268 CURRENT NOISE DENSITY (pA/Hz) -40 10238-244 CHANNEL SEPARATION (dB) -20 Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 TEST CIRCUIT 10k VCC - - + VIN VEE CH A 2k 2k + VEE CH B, CH C, CH D 1k 10238-469 VCC Figure 69 Test Circuit for Channel Separation vs. Frequency Rev. E | Page 21 of 27 ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet THEORY OF OPERATION The ADA4077-1/ADA4077-2/ADA4077-4 are the sixth generation of the Analog Devices, Inc., industry-standard OP07 amplifier family. The ADA4077-1/ADA4077-2/ADA4077-4 are high precision, low noise operational amplifiers with a combination of extremely low offset voltage and very low input bias currents. Unlike JFET amplifiers, the low bias and offset currents are relatively insensitive to ambient temperatures, even up to 125C. The Analog Devices proprietary process technology and linear design expertise have produced high voltage amplifiers with superior performance to the OP07/OP77/OP177/OP1177 in tiny, 8-lead SOIC and 8-lead MSOP packages (ADA4077-1 and ADA4077-2) and 14-lead TSSOP and 14-lead SOIC packages (ADA4077-4). Despite their small size, the ADA4077-1/ ADA4077-2/ADA4077-4 offer numerous improvements, including low wideband noise, wide bandwidth, lower offset and offset drift, lower input bias current, and complete freedom from phase inversion. The ADA4077-1/ADA4077-2/ADA4077-4 have an operating temperature range of -40C to +125C with an MSL1 rating, which is as wide as any similar device in a plastic surface-mount package. This MSL1 rating is increasingly important as printed circuit board (PCB) and overall system sizes continue to shrink, causing internal system temperatures to rise. In the ADA4077-1/ADA4077-2/ADA4077-4, the power consumption is reduced by a factor of four compared to the OP177, and the bandwidth and slew rate are both increased by a factor of six. The low power dissipation and very stable performance vs. temperature also reduce warmup drift errors to insignificant levels. Inputs are protected internally from overvoltage conditions referenced to either supply rail. Like any high performance amplifier, maximum performance is achieved by following appropriate circuit and PCB guidelines. Rev. E | Page 22 of 27 Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 APPLICATIONS INFORMATION OUTPUT PHASE REVERSAL +15V Phase reversal is defined as a change of polarity in the amplifier transfer function. Many operational amplifiers exhibit phase reversal when the voltage applied to the input is greater than the maximum common-mode voltage. In some instances, this phase reversal can cause permanent damage to the amplifier. In feedback loops, it can result in system lockups or equipment damage. The ADA4077-1/ADA4077-2/ADA4077-4 are immune to phase reversal problems even at input voltages beyond the power supply settings. 0.1F 500 FULL-SCALE ADJ ADR4525 0.1F 4.37k 4.12k 200 6 4.12k 1/2 ADA4077-2 100 7 VOUT 5 100 20 RP, ZERO ADJ 49.9k 100 RTD 5k LINEARITY ADJ V+ 2 8 3 4 V- 2 1 10238-064 1/2 1 ADA4077-2 Figure 71. Low Power Linearized RTD Circuit PROPER BOARD LAYOUT CH1 5.00V CH2 5.00V M10.0ms T 0.000% A CH1 300mV 10238-063 The ADA4077-1/ADA4077-2/ADA4077-4 are high precision devices. To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid leakage currents, maintain a clean and moisture free board surface. Coating the surface creates a barrier to moisture accumulation, and reduces parasitic resistance on the board. Figure 70. No Phase Reversal LOW POWER LINEARIZED RTD A common application for a single element varying bridge is an RTD thermometer amplifier, as shown in Figure 71. The excitation is delivered to the bridge by a 2.5 V reference applied at the top of the bridge. RTDs can have a thermal resistance as high as 0.5C/mW to 0.8C/mW. To minimize errors due to resistor drift, keep the current low through each leg of the bridge. In this circuit, the amplifier supply current flows through the bridge. However, at a maximum supply current of 500 A for the ADA4077-2, the RTD dissipates less than 0.1 mW of power, even at the highest resistance. Therefore, errors due to power dissipation in the bridge are kept under 0.1C. Calibration of the bridge is made at the minimum value of the temperature to be measured by adjusting RP until the output is zero. To calibrate the output span, set the full-scale and linearity potentiometers to midpoint, and apply a 500C temperature to the sensor, or substitute the equivalent 500C RTD resistance. Adjust the full-scale potentiometer for a 5 V output. Finally, apply 250C or the equivalent RTD resistance, and adjust the linearity potentiometer for a 2.5 V output. The circuit achieves higher than 0.5C accuracy after adjustment. Keeping supply traces short and properly bypassing the power supplies minimizes the power supply disturbances caused by the output current variation, such as when driving an ac signal into a heavy load. Connect bypass capacitors as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the amplifier. It is recommended that the signal traces be kept at least 5 mm from supply lines to minimize coupling. A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple effects, orient resistors so that heat sources warm both ends equally. Ensure, where possible, that input signal paths contain matching numbers and types of components, to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Place matching components in close proximity to each other, and orient them in the same manner. Ensure that leads are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from amplifier input circuitry as is practical. The use of a ground plane is highly recommended. A ground plane reduces electromagnetic interference (EMI) noise and maintains a constant temperature across the circuit board. Rev. E | Page 23 of 27 ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet LONG-TERM DRIFT TEMPERATURE HYSTERESIS The stability of a precision signal path over its lifetime or between calibration procedures is dependent on the long-term stability of the analog components in the path, such as op amps, references, and data converters. To help system designers predict the longterm drift of circuits that use the ADA4077-1/ADA4077-2/ ADA4077-4, Analog Devices measured the offset voltage of multiple units for 10,000 hours (more than 13 months) using a high precision measurement system, including an ultrastable oil bath. To replicate real-world system performance, the devices under test (DUTs) were soldered onto an FR4 PCB using a standard reflow profile (as defined in the JEDEC J-STD-020D standard), as opposed to testing them in sockets. This manner of testing is important because expansion and contraction of the PCB can apply stress to the integrated circuit (IC) package and contribute to shifts in the offset voltage. In addition to stability over time as described in the Long-Term Drift section, it is useful to know the temperature hysteresis, that is, the stability vs. cycling of temperature. Hysteresis is an important parameter because it tells the system designer how closely the signal returns to its starting amplitude after the ambient temperature changes and subsequent return to room temperature. Figure 73 shows the change in input offset voltage as the temperature cycles three times from room temperature to 125C to -40C and back to room temperature. The dotted line is an initial preconditioning cycle to eliminate the original temperature-induced offset shift from exposure to production solder reflow temperatures. In the three full cycles, the offset hysteresis is typically only 1 V, or 1.5% of its 65 V maximum offset voltage over the full operating temperature range. The histogram in Figure 74 shows that the hysteresis is larger when the device is cycled through only a half cycle, from room temperature to 125C and back to room temperature. 30 VSY = 10V 10 MEAN MEAN PLUS ONE STANDARD DEVIATION MEAN MINUS ONE STANDARD DEVIATION 6 4 2 0 -2 10 0 -10 -20 -30 -40 -4 -6 NUMBER OF DEVICES 10,000 10238-071 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 -10 TIME (Hours) 0 20 40 60 TEMPERATURE (C) 80 100 120 Figure 73. Change in Offset Voltage over Three Full Temperature Cycles VSY = 10V 27 UNITS TA = 25C SAMPLE 1 SAMPLE 2 SAMPLE 3 -8 -20 Figure 72. Measured Long-Term Drift of the ADA4077-1/ADA4077-2/ ADA4077-4 Offset Voltage over 10,000 Hours 40 VSY = 10V 35 27 UNITS x 3 CYCLES HALF CYCLE = +26C, +125C, +26C 30 FULL CYCLE = +26C, +125C, +26C, -40C, +26C 25 20 15 10 5 0 40 35 30 25 20 15 10 5 0 -12 -10 -8 -6 -4 -2 0 2 4 HALF CYCLE FULL CYCLE 6 OFFSET VOLTAGE HYSTERESIS (V) 8 10 12 10238-073 CHANGE IN OFFSET VOLTAGE (V) 8 PRECONDITION CYCLE 1 CYCLE 2 CYCLE 3 20 10238-072 CHANGE IN OFFSET VOLTAGE (V) The ADA4077-1/ADA4077-2/ADA4077-4 have extremely low long-term drift (LTD). Figure 72 shows the LTD of the ADA4077-1 (SOIC package). The red, blue, and green traces show sample units. Note that the mean drift over 10,000 hours is less than 0.5 V, or less than 2% of their maximum specified offset voltage of 25 V at room temperature. Figure 74. Histogram Showing the Temperature Hysteresis of the Offset Voltage over Three Full Cycles and over Three Half Cycles Rev. E | Page 24 of 27 Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.80 0.55 0.40 0.23 0.09 6 0 0.40 0.25 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 75. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 76. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Rev. E | Page 25 of 27 012407-A 8 4.00 (0.1574) 3.80 (0.1497) ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 0.30 0.19 0.75 0.60 0.45 8 0 SEATING PLANE 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 77. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 78. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. E | Page 26 of 27 060606-A 4.00 (0.1575) 3.80 (0.1496) Data Sheet ADA4077-1/ADA4077-2/ADA4077-4 ORDERING GUIDE Model 1 ADA4077-1ARMZ ADA4077-1ARMZ-R7 ADA4077-1ARMZ-RL ADA4077-1ARZ ADA4077-1ARZ-R7 ADA4077-1ARZ-RL ADA4077-1BRZ ADA4077-1BRZ-R7 ADA4077-1BRZ-RL ADA4077-2ARMZ ADA4077-2ARMZ-R7 ADA4077-2ARMZ-RL ADA4077-2ARZ ADA4077-2ARZ-R7 ADA4077-2ARZ-RL ADA4077-2BRZ ADA4077-2BRZ-R7 ADA4077-2BRZ-RL ADA4077-4ARUZ ADA4077-4ARUZ-R7 ADA4077-4ARUZ-RL ADA4077-4ARZ ADA4077-4ARZ-R7 ADA4077-4ARZ-RL 1 2 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C MSL Rating 2 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 MSL1 Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N Z = RoHS Compliant Part. See the Absolute Maximum Ratings section. (c)2012-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10238-0-5/17(E) Rev. E | Page 27 of 27 Package Option RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RU-14 RU-14 RU-14 R-14 R-14 R-14 Branding A35 A35 A35 A2X A2X A2X