S6AP412A 3ch DC/DC Converter with I2C Interface and Internal SW FETs S6AP412A contains 2ch buck DC/DC converter and 1ch buck-boost DC/DC converter. One of the buck DC/DC converter is available for Multi-phase method. Multi-phase DC/DC converter is possible to load high current until 4A. S6AP412A can supply the main power line in several systems by using only its chip. The current mode control is adopted for the DC/DC converter, and it is possible to use the small chip inductor with the high switching frequency operation which contains internal switching FETs. S6AP412A contains the output setting resistor and the phase compensation circuit, and contributes to reduce the number of external components and its mount area. Also it contains the CTL input pin which can control the ON/OFF for each DC/DC converter, 2 the Power Good signal output pin and I C communication interface, therefore it is easy to design the power supply sequence. It is 2 possible to tune in the output voltage exactly using the I C communication. Features Operating input voltage range: 2.5V to 5.5V (Maximum rating: 6.5V) Output voltage setting range: DD1*:0.7V to 1.32V (20mV/step) DD2*:1.2V to 1.95V (50mV/step) DD3*:2.8Vto 3.5V (100mV/step) Maximum output current: DD1:4A, DD2:1.2A, DD3:0.6A Internal switching FETs, output voltage setting resistor, phase compensation circuit and output discharge resistor (all DC/DC converters) Buck-boost DC/DC converter is seamless to change operation mode Soft start time setting range: 1 ms to 16 ms (approximately 1ms/step) Switching frequency for the DC/DC converter: 3 MHz 2 Communication interface: I C (ON/OFF, Output voltage, Soft start time) Internal PFM/PWM auto switching mode Each DC/DC converter Power Good function (open drain) Several protection functions: Under voltage lockout (UVLO), Over current protection (OCP), Thermal shut down (TSD) Small package: QFN32 (5mm x 5mm x 0.71mm, 0.5mm pitch) *: DD1, DD2, DD3 : DC/DC converter block 1,2,3 Applications Network equipment, Factory automation, Security system, Surveillance camera, Electrical music instrument, Multi-function printer, Scanner, Printer, Copy machine, Home appliances,Data storage (HDD, SSD), Mobile equipment for Li+ battery (1 cell) Cypress Semiconductor Corporation Document Number: 002-08447 Rev.*A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised March 28, 2016 S6AP412A Contents 1. Application Circuit Example ............................................................................................................................................ 4 2. Recommended Application Specification ....................................................................................................................... 5 3. Pin Configuration .............................................................................................................................................................. 7 4. Pin Descriptions ................................................................................................................................................................ 8 5. Block Diagram ................................................................................................................................................................. 10 6. Absolute Maximum Ratings ........................................................................................................................................... 11 7. Recommended Operating Conditions ........................................................................................................................... 12 8. Electrical Characteristics ............................................................................................................................................... 13 8.1 Reference Control Block.............................................................................................................................................. 13 8.2 DD1 ............................................................................................................................................................................. 14 8.3 DD2 ............................................................................................................................................................................. 15 8.4 DD3 ............................................................................................................................................................................. 16 8.5 Digital Block................................................................................................................................................................. 17 9. Operation Mode List ....................................................................................................................................................... 18 10. State Transition Diagram................................................................................................................................................ 19 11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3)..................................................................... 20 12. Turning ON and OFF Sequence (AVCC CTLMAINCTL1CTL2 CTL3) ............................................................ 21 2 13. Turning ON and OFF Sequence (AVCCCTLMAINI C) ........................................................................................... 22 14. CTL Pin, MODE Pin, ADDSEL Pin Threshold Voltage .................................................................................................. 23 15. Protection Operation Sequence..................................................................................................................................... 24 16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit ..................................................... 25 17. DD Soft Start Operation .................................................................................................................................................. 26 18. Discharge Operation ....................................................................................................................................................... 27 19. PG Function ..................................................................................................................................................................... 28 2 20. I C Interface ..................................................................................................................................................................... 29 2 20.1 Structure of I C Interface ............................................................................................................................................. 29 20.2 Definition of Signal Lines ............................................................................................................................................. 29 20.3 Validity of Data ............................................................................................................................................................ 30 20.4 Definition of Start and Stop Condition.......................................................................................................................... 30 20.5 ACK Signal .................................................................................................................................................................. 31 2 20.6 I C Interface Input Timing ............................................................................................................................................ 32 20.7 Slave Address ............................................................................................................................................................. 33 2 20.8 Bit Structure of Data on I C Interface .......................................................................................................................... 34 2 21. Structure of I C Interface and Data ................................................................................................................................ 36 21.1 About DD1 Output Voltage Setting .............................................................................................................................. 37 21.2 About DD2 Output Voltage Setting .............................................................................................................................. 38 21.3 About DD3 Output Voltage Setting .............................................................................................................................. 39 21.4 About Soft Start Time .................................................................................................................................................. 40 21.5 DC/DC Operation Mode .............................................................................................................................................. 41 21.6 ON/OFF for DC/DC ..................................................................................................................................................... 42 21.7 About Error Monitor ..................................................................................................................................................... 43 21.8 About Power Good Monitor ......................................................................................................................................... 44 22. I/O Pin Equivalent Circuit Diagram ................................................................................................................................ 45 23. Measurement Circuit for Characteristics of General Operation ................................................................................. 48 24. Reference Data ................................................................................................................................................................ 50 25. Ordering Information ...................................................................................................................................................... 62 26. Preset Code List .............................................................................................................................................................. 63 Document Number: 002-08447 Rev.*A March 28, 2016 Page 2 of 68 S6AP412A 27. Layout .............................................................................................................................................................................. 64 28. Package Dimensions ...................................................................................................................................................... 65 29. Major Changes ................................................................................................................................................................ 66 Document History ................................................................................................................................................................. 67 Document Number: 002-08447 Rev.*A March 28, 2016 Page 3 of 68 S6AP412A 1. Application Circuit Example Figure 1. Application Circuit Document Number: 002-08447 Rev.*A March 28, 2016 Page 4 of 68 S6AP412A 2. Recommended Application Specification [Input Voltage Range] Input voltage Vin(V) Min Typ 2.5 Max 3.3 5.5 (Ta=+25C) Document Number: 002-08447 Rev.*A Soft-start Time (ms) Output Capacitance (F) Inductor(H) Min Mode Max Switching Frequency (MHz) Max 0.708 0.729 0.749 0.769 0.789 0.810 0.830 0.850 0.870 0.891 0.911 (*1) 0.931 0.951 0.972 0.992 1.012 (*1) 1.032 1.052 1.073 1.093 1.113 (*1) 1.133 1.154 1.174 1.194 1.214 (*1) 1.235 1.255 1.275 1.295 1.316 1.336 Limit Current(mA) Typ 0.700 0.720 0.740 0.760 0.780 0.800 0.820 0.840 0.860 0.880 0.900 (*1) 0.920 0.940 0.960 0.980 1.000 (*1) 1.020 1.040 1.060 1.080 1.100 (*1) 1.120 1.140 1.160 1.180 1.200 (*1) 1.220 1.240 1.260 1.280 1.300 1.320 Output Current(mA) Accuracy 1.2% Min 0.692 0.711 0.731 0.751 0.771 0.790 0.810 0.830 0.850 0.869 0.889 (*1) 0.909 0.929 0.948 0.968 0.988 (*1) 1.008 1.028 1.047 1.067 1.087 (*1) 1.107 1.126 1.146 1.166 1.186 (*1) 1.205 1.225 1.245 1.265 1.284 1.304 Remarks VO1 Output Voltage (V) Discharge Resistance (k) DD1 Symbol Channel [Output specification] 5.0 Multi PhaseBuilt-in SWFET Built-in output setting resistors Built-in phase compensation circuit 1 to 16ms 4000 (4800) Buck (synchronous rectification) Multi Phase C-mode March 28, 2016 3.0 1.0 22 At the time of 1.0V setting, the details are cf. Contents 17 Page 5 of 68 DD2 DD3 VO2 VO3 1.2% 1.250 1.265 1.284 1.300 1.316 1.334 (*1) 1.350 (*1) 1.366 (*1) 1.383 1.400 1.417 1.433 1.450 1.467 1.482 (*1) 1.500 (*1) 1.518 (*1) 1.531 1.550 1.569 1.581 1.600 1.619 1.630 1.650 1.670 1.680 1.700 1.720 1.729 1.750 1.771 1.778 (*1) 1.800 (*1) 1.822 (*1) 1.828 1.850 1.872 1.877 1.900 1.923 1.927 1.950 1.973 2.74 (*1) 2.80 (*1) 2.86 (*1) 2.84 2.90 2.96 2.94 (*1) 3.00 (*1) 3.06 (*1) 3.04 3.10 3.16 3.14 3.20 3.26 3.23 (*1) 3.30 (*1) 3.37 (*1) 3.33 3.40 3.47 3.43 (*1) 3.50 (*1) 3.57 (*1) 1.8% Remarks Inductor(H) Mode Min Discharge Resistance (k) 1.235 Max Soft-start Time (ms) Max 1.214 (*1) Output Capacitance(F) Typ 1.200 (*1) Switching frequency(MHz) Min 1.186 (*1) Limit Current(mA) Output Voltage (V) Output Current(mA) Accuracy Symbol Channel S6AP412A 1 to 16ms 1200 (1500) Buck (synchronous rectification) C-mode 3.0 1.0 10 At the time of 1.8V setting, the details are cf. Contents 17 5.0 Built-in SWFET Built-in output setting resistors Built-in phase compensation circuit 5.0 Built-in SWFET Built-in output setting resistors Built-in phase compensation circuit 1 to 16ms 600 (750) Buck-boost (synchronous rectification) C-mode 3.0 1.0 22 At the time of 3.3V setting, the details are cf. Contents 17 *1: default (It is selectable with the default output voltage) Document Number: 002-08447 Rev.*A March 28, 2016 Page 6 of 68 S6AP412A 3. Pin Configuration VO3 IN3 PG3 PG2 PG1 AVCC VREF18 CTLMAIN (TOP VIEW) 32 31 30 29 28 27 26 25 LX3-2 1 24 IN1 PGND3 2 23 PVCC1A LX3-1 3 22 LX1A PVCC3 4 21 PGND1A PVCC2 5 20 PGND1B LX2 6 19 LX1B PGND2 7 18 PVCC1B IN2 8 17 ADDSEL CTL2 CTL3 MODE 13 14 15 16 DVCC 12 SDA 11 SCL 10 GND 9 CTL1 EP(Exposed Pad) (WNT032) Document Number: 002-08447 Rev.*A March 28, 2016 Page 7 of 68 S6AP412A 4. Pin Descriptions Block DD1 Multi-phase DD2 Buck DD3 Buck-boost CTL Pin Name Pin Num ber I/O Description Pulldown Resistor Unus ed DD1 Unused DD2 Unused DD3 Unused 2 IC IN1 24 I DD1 output voltage feedback - GND - - - PVCC1A 23 - DD1 Phase1 output block power supply - AVCC - - - LX1A 22 O DD1 Phase1 inductor connection - Open - - - PG1 28 O DD1 Power Good output - GND - - - - GND - - - PGND1A 21 - DD1 Phase1 output block ground PVCC1B 18 - DD1 Phase2 output block power supply - AVCC - - - LX1B 19 O DD1 Phase2 inductor connection - Open - - - PGND1B 20 - DD1 Phase2 output block ground - GND - - - IN2 8 I DD2 output voltage feedback - - GND - - PVCC2 5 - DD2 output block power supply - - AVCC - - LX2 6 O DD2 inductor connection - - Open - - PG2 29 O DD2 Power Good output - - GND - - PGND2 7 - DD2 output block ground - - GND - - IN3 31 I DD3 output voltage feedback - - - GND - PVCC3 4 - Power supply for DD3 output block - - - AVCC - VO3 32 O Output voltage for DD3 - - - GND - LX3-1 3 O DD3 inductor connection1 - - - Open - LX3-2 1 O DD3 inductor connection2 - - - Open - PG3 30 O Output for DD3 Power Good - - - GND - PGND3 2 - Ground for DD3 output block - - - GND - CTLMAI N 25 I Control for reference voltage output Exist - - - - CTL1 9 I DD1 control Exist Open - - - CTL2 10 I DD2 control Exist - Open - - CTL3 11 I DD3 control Exist - - Open - - - - - GND - - - - Open 2 DVCC 2 IC SCL 16 14 I I Power supply for I C communication 2 Clock for I C communication 2 SDA 15 I/O Data for I C communication Exist - - - Open ADDSEL 17 I Switch for slave address - - - - Open Document Number: 002-08447 Rev.*A March 28, 2016 Page 8 of 68 S6AP412A Block Pin Name AVCC Reference control Pin Numb er I/ O 27 - Pulldown Resist or Unuse d DD1 Unused DD2 Unused DD3 Unus ed 2 IC Power supply for reference voltage - - - - - Exist - - - - Description MODE 12 I Select for DC/DC converter operation mode (H: PFM/PWM mode, L=PWM mode, common for all DCDC converter ) VREF18 26 O Output reference voltage - - - - - GND 13 - Ground for reference voltage - - - - - GND EP - Ground for reference voltage - - - - - Document Number: 002-08447 Rev.*A March 28, 2016 Page 9 of 68 S6AP412A 5. Block Diagram IN1 PVCC1A <<DD1>> VCC:2.5V to 5.5V L Priority A VCC VCC VCC A PWM Logic Control ErrAMP ctl1 ICOMP VREF18 LX1A AST UVLO LV CNV POR PGND1A SLP CMP DAC PG1 mode clk PVCC1B VCC VCC PWM Logic Control ICOMP LX1B AST LV CNV PGND1B SLP CMP cs1 IN2 scp1 xclk PVCC2 <<DD2>> L Priority B VCC VCC VCC ErrAMP ctl2 VREF18 B LX2 PWM Logic Control ICOMP AST UVLO LV CNV POR PGND2 SLP CMP DAC PG2 cs2 IN3 scp2 mode clk PVCC3 <<DD3>> L Priority C VCC VCC VCC ErrAMP ctl3 VREF18 PWM Logic Control ICOMP LX3-1 AST UVLO LV CNV POR SLP CMP DAC C VO3 LX3-2 AST PGND3 PG3 cs3 mode xclk scp3 VREF18 DVCC SCL Logic Control SDA Output Voltage Ajuster AVCC CTL1 ctl1 CTL2 ctl2 CTL3 Common Block Logic Control CTLMAIN VREF BGR ctl3 Under Voltage Locked-Out Thermal Shut Down ADDSEL VREF18 MODE mode scp* (1.8V) Short Circuit Protection (Timer & Latch) Soft Start Control cs* OSC clk CT RT xclk GND Document Number: 002-08447 Rev.*A March 28, 2016 Page 10 of 68 S6AP412A 6. Absolute Maximum Ratings Parameter Symbol Rating Condition Min Unit Max VVCC1 AVCC,PVCC input voltage -0.3 6.5 V VVCC2 DVCC input voltage -0.3 6.5 V VCTL1 CTL1,CTL 2,CTL3 input voltage -0.3 6.5 V VCTL2 CTLMAIN input voltage -0.3 6.5 V VMODE MODE input voltage -0.3 6.5 V VLOGIC SDA,SCL input voltage -0.3 6.5 V VADD ADDSEL input voltage -0.3 6.5 V VPG PG1, PG2, PG3 drain voltage -0.3 6.5 V VOUT IN1, IN2, IN3 input voltage -0.3 6.5 V LX voltage VLX LX1, LX2, LX3 voltage -1.0 6.5 V Permission loss PD Ta+25C Thermal resistance (ja): (29.2C /W(*1)) 0 3420 mW Maximum junction temperature Tjmax - - +125 C Storage temperature TSTG - -55 +125 C Power supply voltage Terminal voltage *1: When the IC is mounted on 74mm x 74mm four-layer square epoxy board. IC is mounted on a four-layer epoxy board, which terminal bias, and the IC's thermal pad is connected to the epoxy board. WARNING: 1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. Figure 2. Power Dissipation vs. Operation Ambient Temperature Power dissipation vs. Operation ambient temperature 4000 3500 3000 Pd [mW] 2500 2000 1500 1000 500 0 -40 -20 0 20 40 60 80 100 Temperature[C] Document Number: 002-08447 Rev.*A March 28, 2016 Page 11 of 68 S6AP412A 7. Recommended Operating Conditions Parameter Symbol Value Condition Min Typ Unit Max 1. Reference control block Power supply voltage VVCC AVCC 2.5 3.3 5.5 V Output current for reference voltage IREF VREF18 -1 - 0 mA Operating temperature Ta - -30 +25 +85 C Power supply voltage VVCC PVCC1, PVCC2, PVCC3 2.5 3.3 5.5 V Input voltage VOUT IN1,IN2 0 - AVCC V Input voltage VOUT IN3 0 - 5.5 V PG input voltage VPG PG1, PG2, PG3 0 - 5.5 V VCTL VMODE CTL1, CTL 2, CTL3, MODE CTLMAIN 0 - AVCC V Power supply voltage VVCC DVCC 1.70 - 3.50 V Input voltage VLOGIC SDA,SCL 0 - DVCC V Input voltage VADD ADDSEL 0 - AVCC V 2. DC/DC channel 3. Input block Input voltage 4. I2C communication block WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. Any use of semiconductor devices will be under their recommended operating condition. 3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. 4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Document Number: 002-08447 Rev.*A March 28, 2016 Page 12 of 68 S6AP412A 8. Electrical Characteristics 8.1 Reference Control Block (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25C, unless otherwise noted. ) Parameter Symbol Condition 1. Reference voltage Output voltage Value Min Typ Max Unit [ VREF18 ] VVREF1 VREF18 pin = 0mA 1.773 1.800 1.827 V VVREF2 AVCC pin = 2.5V to 5.5V VREF18 pin = 0mA 1.768 1.800 1.832 V VVREF3 VREF18 pin = 0mA to -1mA 1.768 1.800 1.832 V 2. Under voltage lockout [ VCC UVLO ] Threshold voltage VTH AVCC rising 2.156 2.20 2.244 V Hysteresis width VH - - 0.20(*1) - V 0.9 1 1.1 ms 3. Over current protection Timer [ OCP ] tOCP1 DD1, DD2, DD3 4. Thermal shut down Stop temperature [ TSD ] TTSDH - 5. Input block (CTL,MODE,CTLMAIN) 125(*2) 150 - C [ CTL,MODE,CTLMAIN ] Input voltage VIH CTL1, CTL2, CTL3,MODE pin CTLMAIN pin AVCC x0.7 - AVCC V Input voltage VIL CTL1, CTL2, CTL3,MODE pin CTLMAIN pin 0 - 0.4 V ICTLH IMODEH CTL1, CTL2, CTL3,MODE pin = 3.3V CTLMAIN pin = 3.3V 2.5 3.3 4.7 A ICTLL IMODEL CTL1, CTL2, CTL3,MODE pin = 0V CTLMAIN pin = 0V - - 1 A RP CTL1, CTL2, CTL3,MODE pin CTLMAIN pin - 1(*1) - M Input current Input pull-down resistor 6. Consumption current (DC/DC converter block) IVCCS1 CTL1, CTL2, CTL3 pin = 0V CTLMAIN pin = 0V - 0 1.0 A IVCCS2 CTL1, CTL2, CTL3 pin = 0V CTLMAIN pin =3.3V - 30 45 A IVCC DD1,DD2,DD3=ON,MODE=3.3V, All DD are 0mA (operation mode: PFM/PWM mode) - 430 630 A IVCC DD1,DD2,DD3=ON,MODE=0V All DD are 0mA (operation mode: Fixed PWM mode) - 18 27 mA Power supply current *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08447 Rev.*A March 28, 2016 Page 13 of 68 S6AP412A 8.2 DD1 AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25C, unless otherwise noted. ) Parameter Symbol Value Condition 1. DC/DC converter block Min Typ Unit Max [ DD1 ] Output voltage VOUT IOUT = -10mA, Output voltage setting: 1.0V 0.988 1.000 1.012 V Input stability VLINE IOUT = -10mA, PVCC1= 2.5V to 5.5V -5 - +5 mV Load stability VLOAD IOUT = -1mA to -4000mA (Fixed PWM mode) -10 - +10 mV Load stability VLOAD IOUT = -1mA to -4000mA (PFM/PWM mode) -10 - +15 mV IN1 input impedance RIN IN1 = 2.0V - 190(*1) - k SW PMOS-Tr on resistance RPMOS LX1A,1B = -30mA - 120(*1) - m SW NMOS-Tr on resistance RNMOS LX1A,1B = 30mA - 80(*1) - m SW PMOS-Tr leakage current ILEAK LX1A,1B = 0V -3 - - A SW NMOS-Tr Leakage current ILEAK LX1A,1B = 3.3V - - 3 A Over current protection value ILIMIT L=1.0H 4900(*2) - - mA PFM/PWM mode changeover current IPFM L=1.0H - 100(*1) - mA Discharge resistor RDIS - - 5(*1) - k Soft start time Tss Soft start time setting: 1ms 0.9 1 1.1 ms Switching frequency fOSC 2.7 3.0 3.3 MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08447 Rev.*A March 28, 2016 Page 14 of 68 S6AP412A 8.3 DD2 (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25C, unless otherwise noted. ) Parameter Symbol Value Condition 2. DC/DC converter block Min Typ Unit Max [ DD2 ] Output voltage VOUT IOUT = -10mA, Output voltage setting:1.8V 1.778 1.800 1.822 V Input stability VLINE IOUT = -10mA PVCC2= 2.5V to 5.5V -5 - +5 mV Load stability VLOAD IOUT = -1mA to -1200mA (Fixed PWM mode) -10 - +10 mV Load stability VLOAD IOUT = -1mA to -1200mA (PFM/PWM mode) -10 - +20 mV IN2 input impedance RIN IN2 = 2.0V - 150(*1) - k SW PMOS-Tr on resistance RPMOS LX2 = -30mA - 190(*1) - m SW NMOS-Tr on resistance RNMOS LX2 = 30mA - 135(*1) - m SW PMOS-Tr leakage current ILEAK LX2 = 0V -3 - - A SW NMOS-Tr leakage current ILEAK LX2 = 3.3V - - 3 A Over current protection value ILIMIT L=1.0H 1500(*2) - - mA PFM/PWM mode changeover current IPFM L=1.0H - 65(*1) - mA Discharge resistor RDIS - - 5 - k Soft start time Tss Soft start time setting:1ms 0.9 1 1.1 ms Switching frequency fOSC - 2.7 3.0 3.3 MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08447 Rev.*A March 28, 2016 Page 15 of 68 S6AP412A 8.4 DD3 (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25C, unless otherwise noted. ) Parameter Symbol Value Condition 3. DC/DC converter block Unit Min Typ Max 3.241 3.300 3.359 V -5 - +5 mV -10 - +10 mV -10 - +15 mV - 550(*1) - k [ DD3 ] Output voltage VOUT Input stability VLINE Load stability VLOAD Load stability VLOAD IN2 input impedance SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr on resistance SW NMOS-Tr on resistance SW PMOS-Tr leakage current SW NMOS-Tr leakage current SW PMOS-Tr leakage current SW NMOS-Tr leakage current Over current protection value PFM/PWM mode changeover current Discharge resistor Soft start time Switching frequency RIN IOUT = -10mA, Output voltage setting:3.3V IOUT = -10mA, PVCC3= 2.5V to 5.5V IOUT = -1mA to -600mA (Fixed PWM mode) IOUT = -1mA to -600mA (PFM/PWM mode) IN3 = 2.0V RPMOS LX3-1 = -30mA - 115(*1) - m RNMOS LX3-1 = 30mA - 140(*1) - m RPMOS LX3-2 = -30mA - 155(*1) - m RNMOS LX3-2 = 30mA - 220(*1) - m ILEAK LX3-1 = 0V -3 - - A ILEAK LX3-1 = 3.3V - - 1 A ILEAK LX3-2 = 0V -3 - - A ILEAK LX3-2 = 3.3V - - 1 A ILIMIT L=1.0H 1000(*2) - - mA IPFM L=1.0H - 200(*1) - mA RDIS Tss fOSC Soft start time setting:1ms - 0.9 2.7 5(*1) 1 3.0 1.1 3.3 k ms MHz *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. *2: No production tested, ensure by design. Document Number: 002-08447 Rev.*A March 28, 2016 Page 16 of 68 S6AP412A 8.5 Digital Block (AVCC = PVCC1A=PVCC1B=PVCC2=PVCC3 = 3.3V, supply, PGND1A=PGND1B=PGND2=PGND3=GND=0V. Ta = +25C, unless otherwise noted. ) Parameter Symbol Value Condition 1. Power Good block Min Typ Max Unit [ Power Good ] Output voltage VOL PG1, PG2, PG3 IOL = 1mA - - 0.4 V Output current IOL PG1, PG2, PG3 1 - - mA Low voltage detection VTH IN1, IN2, IN3 = falling - Vo x0.90(*1) - V Power on detection VTH IN1, IN2, IN3 = rising - Vo x0.93(*1) - V 2 2 2. I C block [I C] VIH SCL,SDA DVCC x0.7 - DVCC V VIL SCL,SDA 0 - DVCC x0.3 V IIH SCL,SDA DVCC = 3.3V - - 10 A IIL SCL,SDA DVCC = 3.3V -10 - - A Output voltage VOL SDA IOL = 3mA - - 0.4 V Output current IOL SDA 3 - - mA Input voltage Input current 3. ADDSEL block [ ADDSEL ] Input voltage VIH ADDSEL AVCC x0.7 - AVCC V Input voltage VIL ADDSEL 0 - 0.4 V IADD ADDSEL = 3.3V 2.5 3.3 4.7 A IADD ADDSEL = 0V - - 1 A Input current Input pull-down RP ADDSEL 1(*1) resistor *1: This parameter is not be specified. This should be used as a reference to support designing the circuits. Document Number: 002-08447 Rev.*A March 28, 2016 M Page 17 of 68 S6AP412A 9. Operation Mode List Table 1. Operation Mode List Mode CTLMAIN (external) 2 CTL1 (external/I C) 2 CTL2 (external/I C) 2 CTL3 (external/I C) Reference Digital DD1 DD2 DD3 CTL signal Operation Block 2 2 Stand-by L L L L OFF OFF OFF OFF OFF Stand-by2 H L L L ON ON OFF OFF OFF Normal H H/L(*1) H/L(*1) H/L(*1) ON ON ON/OFF ON/OFF ON/OFF Error Detection H X X X ON ON OFF OFF OFF I C communication I C communication disable enable enable enable Protection operating Thermal shut down (TSD) Not available Not available available (*2) Over current protection (OCP) Not available Not available available (*2) *1: normal mode means that CTLMAIN pin is "H" level and each DD CTL pin is "H" level *2: This state is after each err detection. Error state will release, when the power supply voltage or CTLMAIN pin will turn off and on. 2 Priority of the External CTL pin and I C Communication CTLMAIN (External) CTL1, CTL2, CTL3 (External) 30h Resistor 2 (I C) Relevant Channel H H 1 ON H H 0 ON H L 1 ON H L 0 OFF L X disable OFF 2 Priority of the External MODE pin and I C Communication 20h Resistor MODE Operation Mode 2 (External) (I C) H 1 PFM/PWM H 0 PFM/PWM L 1 PFM/PWM L 0 Fixed PWM Notes: 2 * The I C communication is valid after the reference control block and digital block activation setting the external CTLMAIN pin to "H" level. 2 * Please attention below note about ON/OFF control of DD1, DD2, DD3 by I C communication. 2 When each DD control is turned off by I C communication and external CTL pin remains "H" level, DCDC converter keep operating. Document Number: 002-08447 Rev.*A March 28, 2016 Page 18 of 68 S6AP412A 10. State Transition Diagram Stand-by (1) (2) Stand-by 2 (3) (2) (4) General (6) (5) Error detection (1) External CTLMAIN pin is "H" level. (2) External CTLMAIN pin is "L" level. (3) External CTL pin or I C communication "relevant CH_ON" (4) External CTL pin or I C communication "relevant CH_OFF" (5) Error detection (TSD, OCP 1ms continuation) (6) Turning on the power supply again (equal to or less than uvlo_vcc rest voltage) or setting CTLMAIN to "L" level 2 2 Document Number: 002-08447 Rev.*A March 28, 2016 Page 19 of 68 S6AP412A 11. Turning ON and OFF Sequence (AVCC=CTLMAIN, CTL1, CTL2, CTL3) 2.0V 2.2V AVCC CTLMAIN CTL* 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) 93% Discharge 93% Discharge 93% Discharge DD1 PG1 DD2 PG2 DD3 PG3 UVLO release to DD* activation Soft-start time Time till start (*1) Typ : (820)s Max : TBD s *1: CTL1, CTL2, CTL3 *2: DD1, DD2, DD3 *3: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0F Document Number: 002-08447 Rev.*A March 28, 2016 Page 20 of 68 S6AP412A 12. Turning ON and OFF Sequence (AVCC CTLMAINCTL1CTL2 CTL3) AVCC 3.3V CTLMAIN 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) CTL1 93% Discharge DD1 PG1=CTL2 93% Discharge DD2 PG2=CTL3 93% Discharge DD3 PG3 UVLO release to DD* activation Time till start (*1) Typ : (820)s Max : TBD s *1: DD1, DD2, DD3 *2: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0F Document Number: 002-08447 Rev.*A March 28, 2016 Page 21 of 68 S6AP412A 13. Turning ON and OFF Sequence (AVCCCTLMAINI2C) AVCC 3.3V CTLMAIN 1.8V VREF18 osc (IC internal signal) uvlo_vcc (IC internal signal) I2C(DD ON/OFF) OFF ON OFF ctl* 93% Discharge 93% Discharge 93% Discharge DD1 PG1 DD2 PG2 DD3 PG3 UVLO release to DD* activation Soft-start time Time till start (*1) Typ : (820)s Max : TBD s *1: CTL1, CTL2, CTL3 *2: DD1, DD2, DD3 *3: VREF18 activations depend on the VREF18 pin capacitance. Time in the sequence figure above is applied for the following condition. VREF18 pin capacitance: 1.0F Document Number: 002-08447 Rev.*A March 28, 2016 Page 22 of 68 S6AP412A 14. CTL Pin, MODE Pin, ADDSEL Pin Threshold Voltage The input circuit structure for the CTL(*1) pin is the schmitt trigger style, and the threshold voltage shows the hysteresis characteristics when CTL(*1) OFF to ON and ON to OFF. (See "CTL(*1) pin equivalent circuit diagram" below.) Also, the threshold voltage level depends on the VCC pin voltage. Moreover, make sure to input either the "H" level (>"VCCx0.7"V) or "L" level (<0.4V) to the CTL(*1) and MODE and ADDSEL pin when in use. Figure 3. CTL (*1), MODE, ADDSEL Pin Equivalent Circuit Diagram The CTL threshold voltage shows the hysteresis characteristics. AVCC ESD protection element CTL*(*1) MODE ADDSEL ESD protection element GND *1: CTLMAIN, CTL1, CTL2, CTL3 Document Number: 002-08447 Rev.*A March 28, 2016 Page 23 of 68 S6AP412A 15. Protection Operation Sequence Over Current Protection (DD channel) The DD channel monitors the peak current of FET at any time during the operation. When the DD output becomes the over current state, the output voltage is decreased. Afterward, the timer operation is performed and the output stops after about 1ms progress. When one of each DD channel stops operation by over current protection, all DD channels stop operation. Thermal Shut Down If the temperature at the junction part reaches +150C, the thermal shutdown protection circuit turns all channels off. Error Detection Sequence Figure 4. Error Detection Sequence DD1,DD2,DD3 The whole IC Normal operation Normal operation Over current detection Thermal shutdown protection Voltage drop No 1ms Continue for 1ms? Yes Error detection mode Error signal output (I2C address 40h) Error Detection Mode Release It is necessary to turn the power supply turning on again, or to turn CTLMAIN turning on again to release the error detection mode. Document Number: 002-08447 Rev.*A March 28, 2016 Page 24 of 68 S6AP412A 16. Operation Condition, Stop Circuit and Release Condition for Protection Circuit Operation Whilst Under Protection Channel Under Voltage Lockout Protection (UVLO) Over Current Protection (OCP) Operating condition: Input voltage drop Operating condition: After about 1ms progress in the over current condition DD1,DD2,DD3 Discharge Process during protection operation: DD1, DD2, DD3 stop Process during protection operation: DD1, DD2, DD3 stop Recovery condition: Input voltage rise Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted UVLO operates only when CTLMAIN is "H" (at VREF18 output). Thermal Shutdown Protection (TSD) Operating condition: Chip temperature increment Process during protection operation: DD1, DD2, DD3 stop Recovery condition: (1) Power supply reasserted (2) CTLMAIN reasserted Only when CTLMAIN is in the "H" state and CTL(*1) is in the "H" state, or when DD(*2) in 2 operating condition by I C, will operate. Error output Write "1" when detecting No change Write "1" when detecting TSD (address 40h) OCP Thermal shutdown protection (TSD) operation during over current protection timer operation When the thermal shutdown protection (TSD) operated during the over current protection (OCP) timer operation, the thermal shutdown protection has priority. Operation when releasing under voltage lockout protection (UVLO) 2 * DD1,DD2,DD3,DD4: Activation following the condition for CTL(*1) pin or I C Note: 2 * When VREF18 decreases at the time of UVLO operation, I C register is reset, and all DD does OFF. It is necessary to let you do ON by CTL(*1) pin and communication again to let DD have ON." *1: CTL1, CTL2, CTL3 *2: DD1, DD2, DD3 Document Number: 002-08447 Rev.*A March 28, 2016 Page 25 of 68 S6AP412A 17. DD Soft Start Operation The soft-start operation for DD1, DD2 and DD3 is enabled in order to prevent the rush current during the DD activation. The 2 soft-start time can be controlled by I C. About output voltage changing option, soft start time is showed by follow equation. Tss=Tslp x Vset/Vdef (ms) Tss: soft start time Tslp: slope coefficient of soft start Vset: output voltage setting Vdef: DD1=1.0, DD2=1.8, DD3=3.3 Figure 5. DD Soft Start Output voltage2 setting value Output voltage1 setting value Output voltage3 setting value Soft-start time Channel ON/OFF signal (internal signal) t Document Number: 002-08447 Rev.*A March 28, 2016 Page 26 of 68 S6AP412A 18. Discharge Operation DD Channel When executing the DD OFF operation at the channel ON/OFF signal, the DC/DC smooth capacitance charged for each output voltage is discharged using resistor for discharge which is set in the IC and the output voltage is decreased gradually. However, the discharge time changes depending on the DC/DC converter load current. The discharge time is calculated by the following equation. Discharge time (time till the output becomes 10% without load) toff(s) 2.3 xR_DIS xCOUT (F) Note: * See the table in Electrical Characteristics for the discharge resistor value. IN(*1) A R1 Resistor for discharge PVCC(*2) A Error Amp R2 LX(*3) Cout Reference voltage DAC PGND(*4) Channel ON/OFF Cont. *1: IN1, IN2, IN3 *2: PVCC1, PVCC2, PVCC3 *3: LX1, LX2, LX3 *4: PGND1, PGND2, PGND3 Document Number: 002-08447 Rev.*A March 28, 2016 Page 27 of 68 S6AP412A 19. PG Function The following pins for each channel Power Good output are prepared. PG1 It is the pin for DD1 Power Good output. When the output voltage exceeds 93% of the setting value at the DD1 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD1 OFF mode. PG2 It is the pin for DD2 Power Good output. When the output voltage exceeds 93% of the setting value at the DD2 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD2 OFF mode. PG3 It is the pin for DD3 Power Good output. When the output voltage exceeds 93% of the setting value at the DD3 ON mode, "H" is output. Also, when the output voltage becomes equal or lower than 90% of the setting value after the "H" output, "L" is output. "L" is output at the DD3 OFF mode. Document Number: 002-08447 Rev.*A March 28, 2016 Page 28 of 68 S6AP412A 20. I2C Interface 2 20.1 Structure of I C Interface 2 The I C interface executes the data communication in 1 byte (8-bit) units using two signal lines (bus), a SCL (serial clock line) and a SDA (serial data line). This bus is connected to multiple devices; master: device to generate the clock signal and to control the data transfer (CPU and so on) slave: device that an address is specified by a master. This IC is set as the slave and has no function to be the master. Each device is defined due to the communication direction as described below. transmitter: device to send data to bus receiver: device to receive data from bus The IC has the function both transmitter and receiver. SCL SDA transmitter receiver receiver maser slave1 transmitter slave2 The IC defines the followings; Write : data is transmitted from master and the IC receives data Read : The IC transmits data and master receives data. 20.2 Definition of Signal Lines SCL and SDA are connected to the power supply by the pull-up resistor. The output circuit is the open Drain output. When a bus is not used (waiting state), the open "H" is set changing the open Drain to the OFF state. Note: 2 * SCL and SDA pins adopt a different ESD protection system from standard I C specification because of ESD enhancement (see 22 I/O Pin Equivalent Circuit Diagram). When the power supply is in the bus line, do not shut off the power supply for an IC (DVCC). I2C bus line power supply R R Pull Up SCL SDA input Inside of IC Document Number: 002-08447 Rev.*A March 28, 2016 input output Page 29 of 68 S6AP412A 20.3 Validity of Data Data has the following characteristics; Change when SCL is the "L" level Valid if the state is kept while SCL is the "H" level. SCL SDA data state data change data state The SDA signal change means the start or stop condition when SCL is the "H" level. 20.4 Definition of Start and Stop Condition The start and stop conditions are output from the master and shows start and stop of communications to the slave. Start: SDA changes from "H" to "L" when SCL is "H". Stop: SDA changes from "L" to "H" when SCL is "H". SCL SDA S start condition Document Number: 002-08447 Rev.*A P stop condition March 28, 2016 Page 30 of 68 S6AP412A 20.5 ACK Signal This is a signal to confirm the data reception during communication. The receiver replies the ACK signal to show the data reception to a transmitter every time 1 byte (8-bit) of data is received. The ACK signal is sent in 9clk after sending data 8-bit matching to the SCL signal that the master generates. A transmitter keeps SDA output "open H" in SCL9clk. A receiver informs the data reception situation to a transmitter outputting the followings in SCL 9 clk; when data was received : SDA output "L" (ACK) when no data was received : SDA output "open H" (NACK) However, if the master is changed to the receiver, ACK is not replied after the last data reception because the bus keeps open stopping the data transmission to the slave transmitter. In this case, the slave transmitter opens the bus (open H) and is set to the stop condition reception waiting state from the master. SCL from master SDA by transmitter 1 8 bit0 bit7 9 H hold 10 bit0 NACK SDA by receiver ACK Document Number: 002-08447 Rev.*A March 28, 2016 Page 31 of 68 S6AP412A 2 20.6 I C Interface Input Timing (within recommended operating conditions) Value Parameter Symbol SCL=100kHz Min SCL=400kHz Max Min Unit Max SCL clock frequency fSCL - 100 - 400 kHz Start condition hold time tHD:start 4.0 - 0.6 - s Restart condition setup time tSU:start 4.7 - 0.6 - s Stop condition setup time tSU:stop 4.0 - 0.6 - s Stop to Start bus open time tbuf 4.7 - 1.3 - s SCL "L" time tLow 4.7 - 1.3 - s SCL "H" time tHigh 4.0 - 0.6 - s SCL/SDA rising time tr - 1.0 - 0.3 s SCL/SDA falling time tf - 0.3 - 0.3 s Data hold time tHD:data 0.0 - 0.0 - s Data setup time tSU:data 0.25 - 0.10 - s Cb - 400 - 400 pF SCL/SDA capacitor load VIH/VIL level reference 2 Conform to I C bus specifications S tr tf tHigh tLow Sr P SCL tbuf SDA tHD:start tSU:data Document Number: 002-08447 Rev.*A tHD:data tSU:start March 28, 2016 tSU:stop Page 32 of 68 S6AP412A 20.7 Slave Address 2 This is a slave address when communicating with the I C interface. The slave address of this IC is set by the first seven bits as shown below. The seventh bit follows the ADDSEL pin and "0"/"1" are variable. The eighth bit is called the least significant bit (LSB) and determines the message direction. The bit "0" shows that information will be written from the master to the slave. The bit "1" shows that the master reads information from the slave. This does not support the general call address. When the ADDSEL pin is in "H" slave address S T A R T 0 1 0 1 1 0 1 MSB R/W A C K S T O P A C K S T O P LSB When the ADDSEL pin is in "L" slave address S T A R T Document Number: 002-08447 Rev.*A 0 1 0 1 1 MSB 0 0 R/W LSB March 28, 2016 Page 33 of 68 S6AP412A 2 20.8 Bit Structure of Data on I C Interface 1. Writing Data to Register and Reading Data The data line is sent/received in the order from the most significant bit (MSB) to the least significant bit (LSB). S T A R T No. A C K slave address 1 2 3 4 5 6 7 8 register address 1 S 0 1 0 1 1 0 0 W A C K 2 3 4 5 6 7 8 0 0 0 0 0 0 1 0 S A T C O K P data 1 2 3 4 5 6 7 8 a b c d e f g h P register data address 00H 01H 02H 03H 04H : : D07 D06 D05 D04 D03 D02 D01 D00 a b c d e f g h Output the "stop" condition after sending the Write data. : Signal which a master sends, Document Number: 002-08447 Rev.*A : Signal which this IC sends March 28, 2016 Page 34 of 68 S6AP412A 2 2. I C Interface Data Format 2 1. 2. 3. 4. About I C Communication When a different slave address comes, non-matching ID is informed by not replying ACK after receiving the slave address. All registers write to internal registers in the ACK signal after receiving the 8-bit data of each setting. If a non-existing register address is specified, data is not written to a register. Output the "stop" condition after sending the write data. <Write(W)> S T A R T A C K slave address register address A C K data S A T C O K P S 0 1 0 1 1 0 0 W P Write is allowed per one address. (Sequential writing is not allowed.) Send register address and data as one unit. : Signal which a master sends, : Signal which this IC sends <Read(R)> S T A R T slave address S 0 1 0 1 1 0 0 W A C K register address S T A A C R K T slave address A C K S 0 1 0 1 1 0 0 R data S A T C O K P P Read is allowed per one address. Be sure to perform read by specifying the register addresses. (Sequential reading is not allowed.) : Signal which a master sends, Document Number: 002-08447 Rev.*A : Signal which this IC sends March 28, 2016 Page 35 of 68 S6AP412A 21. Structure of I2C Interface and Data Table 2. Register Map Data Address Output voltage Soft start DD operation mode ON/OFF Error Remarks d07 d06 d05 d04 d03 d02 d01 d00 00H 0 0 0 D04 D03 D02 D01 D00 0FH ACK DD1 output voltage setting 01H 0 0 0 0 D03 D02 D01 D00 0CH ACK DD2 output voltage setting 02H 0 0 0 0 0 D02 D01 D00 05H ACK DD3 output voltage setting 03H 0 0 0 (*1) (*1) (*1) (*1) (*1) 0FH ACK Unused 10H 0 0 0 0 D03 D02 D01 D00 00H ACK DD1 soft-start time setting 11H 0 0 0 0 D03 D02 D01 D00 00H ACK DD2 soft-start time setting 12H 0 0 0 0 D03 D02 D01 D00 00H ACK DD3 soft-start time setting 13H 0 0 0 0 (*1) (*1) (*1) (*1) 00H ACK Unused ACK DD operation mode setting "0": Fixed PWM mode, "1": PFM/PWM mode ACK DD output ON/OFF setting "0": Output OFF / "1": Output ON - DD error state monitoring register (read only) "0": Normal / "1": Error detection 20H 30H 40H 0 0 0 0 0 0 0 0 0 0 0 D04 (*1) (*1) (*1) D02 D02 D02 D01 D01 D01 D00 D00 D00 Default Writin g Timing 00H 00H 00H PG 50H 0 0 0 0 (*1) D02 D01 D00 00H - DD PG state monitoring register (read only) "0": Non-output / "1": output For test EXH - - - - - - - - - - Disabled For test FXH - - - - - - - - - - Disabled *1: Unused register. Write/read is possible, but does not influence IC movement. Note: * Address FXH and address EXH are for test. Donot write/read FXH and EXH. Document Number: 002-08447 Rev.*A March 28, 2016 Page 36 of 68 S6AP412A 21.1 About DD1 Output Voltage Setting Address 00H DD1 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD1 is controlled by writing data to address 00 H. Data S T A R T 0 0 0 D04 D03 MSB D02 D01 D00 LSB A C K S T O P Address 00H: For DD1 output voltage setting D04 to D00: Set the output voltage DD1 Output Voltage Setting Table Data 00H Output Voltage (V) 0.700 Data 10H Output Voltage (V) 1.020 01H 0.720 11H 1.040 02H 0.740 12H 1.060 03H 0.760 13H 1.080 04H 0.780 14H 1.100 (*1) 05H 0.800 15H 1.120 06H 0.820 16H 1.140 07H 0.840 17H 1.160 08H 0.860 18H 1.180 09H 0.880 19H 1.200 (*1) 0AH 0.900 (*1) 1AH 1.220 0BH 0.920 1BH 1.240 0CH 0.940 1CH 1.260 0DH 0.960 1DH 1.280 0EH 0.980 1EH 1.300 0FH 1.000 (*1) 1FH 1.320 *1: Preset value Document Number: 002-08447 Rev.*A March 28, 2016 Page 37 of 68 S6AP412A 21.2 About DD2 Output Voltage Setting Address 01H DD2 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD2 is controlled by writing data to address 01 H. Data S T A R T 0 0 0 0 D03 MSB D02 D01 D00 LSB A C K S T O P address01H: For DD2 output voltage setting D03 to D00: Set the output voltage DD2 Output Voltage Setting Table Data Output Voltage (V) 00H 1.200 (*1) 01H 1.250 02H 1.300 03H 1.350 (*1) 04H 1.400 05H 1.450 06H 1.500 (*1) 07H 1.550 08H 1.600 09H 1.650 0AH 1.700 0BH 1.750 0CH 1.800 (*1) 0DH 1.850 0EH 1.900 0FH 1.950 *1: Preset value Document Number: 002-08447 Rev.*A March 28, 2016 Page 38 of 68 S6AP412A 21.3 About DD3 Output Voltage Setting Address 02H DD3 is allocated as resisters for the DC/DC output voltage setting. The DC/DC output voltage setting of DD3 is controlled by writing data to address 02H. Data S T A R T 0 0 0 0 0 MSB D02 D01 D00 LSB A C K S T O P address02H: For DD3 output voltage setting D02 to D00: Set the output voltage DD3 Output Voltage Setting Table Data Output Voltage(V) 00H 2.80 (*1) 01H 2.90 02H 3.00 (*1) 03H 3.10 04H 3.20 05H 3.30 (*1) 06H 3.40 07H 3.50 (*1) *1: Preset value Document Number: 002-08447 Rev.*A March 28, 2016 Page 39 of 68 S6AP412A 21.4 About Soft Start Time Address 10H to 12H are allocated as registers for the soft start time control. The soft start time control is controlled by writing data to addresses 10 H to 12H. Data S T A R T 0 0 0 0 D03 MSB D02 D01 D00 LSB A C K S T O P address10H: For DD1 soft start time setting address11H: For DD2 soft start time setting address12H: For DD3 soft start time setting D03 to D00: Set the soft start time Tss=Tslp x Vset/Vdef (ms) Tss: soft start time Tslp: slope coefficient of soft start:refer to follow table Vset: output voltage setting Vdef: DD1=1.0, DD2=1.8, DD3=3.3 Soft Start Time Setting Data Tslp 00H 1.0 01H 2.0 02H 3.0 03H 4.0 04H 5.0 05H 6.0 06H 7.0 07H 8.0 08H 9.0 09H 10.0 0AH 11.0 0BH 12.0 0CH 13.0 0DH 14.0 0EH 15.0 0FH *1: Preset value Remarks DD1,DD2,DD3 (*1) 16.0 Document Number: 002-08447 Rev.*A March 28, 2016 Page 40 of 68 S6AP412A 21.5 DC/DC Operation Mode Address 20H is allocated as a register for the DC/DC operation mode control. The DC/DC operation mode is controlled by writing data to address 20 H. Data S T A R T 0 0 0 0 D03 MSB D02 D01 D00 LSB A C K S T O P address20H: For DC/DC operation mode setting D01 to D00: Set the DC/DC operation mode Address Bit Description 20H D00 0: DD1 Fixed PWM (*1) 1: DD1 PFM/PWM 20H D01 0: DD2 Fixed PWM (*1) 1: DD2 PFM/PWM 20H D02 0: DD3 Fixed PWM (*1) 1: DD3 PFM/PWM 20H D03 *1: Preset value Out of use Document Number: 002-08447 Rev.*A March 28, 2016 Page 41 of 68 S6AP412A 21.6 ON/OFF for DC/DC Address 30H is allocated as a register for the DC/DC ON/OFF. The DC/DC ON/OFF is controlled by writing data to address 30 H. Data S T A R T 0 0 0 0 D03 D02 MSB D01 D00 LSB A C K S T O P address30H: For DC/DC ON/OFF D02 to D00: Set ON/OFF for DC/DC Address Bit Description 30H D00 0: DD1 output OFF (*1) 1: DD1 output ON 30H D01 0: DD2 output OFF (*1) 1: DD2 output ON 30H D02 0: DD3 output OFF (*1) 1: DD3 output ON D03 Out of use 30H *1: Preset value Document Number: 002-08447 Rev.*A March 28, 2016 Page 42 of 68 S6AP412A 21.7 About Error Monitor Address 40H is allocated as error status monitor of each DC/DC output and thermal shut down. Address 40H is read only resistor. Data S T A R T 0 0 0 D04 D03 D02 MSB D01 D00 LSB A C K S T O P address40H: For error monitor of each DC/DC output and thermal shut down D04 to D00: read only resistor. (Not allowed write resistor) Address Bit Description 40H D00 0: DD1 OCP non detection (*1) 1: DD1 OCP detection 40H D01 0: DD2 OCP non detection (*1) 1: DD2 OCP detection 40H D02 0: DD3 OCP non detection (*1) 1: DD3 OCP detection 40H D03 Out of use 40H D04 0: TSD non detection (*1) 1: TSD detection *1:Preset value Document Number: 002-08447 Rev.*A March 28, 2016 Page 43 of 68 S6AP412A 21.8 About Power Good Monitor Address 50H is allocated as output monitor of each DC/DC output. Address 50H is read only resistor. Data S T A R T 0 0 0 0 D03 MSB D02 D01 D00 LSB A C K S T O P address50H: For output monitor of each DC/DC output. Detection level is over 93% of DCDC output voltage setting. D04 to D00: read only resistor. (Not allowed write resistor) Address Bit Description 50H D00 0: DD1 non output (*1) 1: DD1 output 50H D01 0: DD2 non output (*1) 1: DD2 output 50H D02 0: DD3 non output (*1) 1: DD3 output 50H D03 *1: Preset value Out of use Document Number: 002-08447 Rev.*A March 28, 2016 Page 44 of 68 S6AP412A 22. I/O Pin Equivalent Circuit Diagram <<AVCC>> AVCC ESD protection element GND <<VREF18>> AVCC VREF18 GND <<IN1,IN2, LX1,LX2, PGND1<PGND2>> AVCC IN* GND IN*: IN1, IN2 LX*: LX1, LX2 PGND*: PGND1, PGND2 Document Number: 002-08447 Rev.*A LX* PGND* March 28, 2016 Page 45 of 68 S6AP412A <<PVCC1,PVCC2> AVCC PVCC*: PVCC1, PVCC2 LX*: LX1, LX2 PGND*: PGND1, PGND2 PVCC* LX* PGND* GND <<IN3,PGND3 > IN3 GND PGND3 <<PVCC3,LX3-1,LX3-2,VO3>> AVCC PVCC3 LX3-1 VO3 LX3-2 PGND3 GND Document Number: 002-08447 Rev.*A March 28, 2016 Page 46 of 68 S6AP412A <<CTL*, ADDSEL, MODE>> <<PG*>> AVCC AVCC PG*: PG1, PG2, PG3 PG* CTL* ADDSEL MODE GND GND CTL*: CTLMAIN, CTL1, CTL2, CTL3 <<SCL>> <<SDA>> DVCC DVCC SCL SDA GND GND Document Number: 002-08447 Rev.*A March 28, 2016 Page 47 of 68 S6AP412A 23. Measurement Circuit for Characteristics of General Operation S6AP412A Input Voltage: 2.5V to 5.5V C1 0.1mF IN1 AVCC L1 C2 4.7mF PVCC1A LX1A C7 C8 22mF 22mF 1.0mH DD1:1.0V Io(max):4000mA PGND1A C3 4.7mF PVCC1B L2 LX1B CTL1 1.0mH PGND1B R1 100kW PG1 PG1 C4 4.7mF IN2 PVCC2 LX2 CTL2 L3 C9 22mF 1.0mH DD2:1.80V Io(max):1200mA PGND2 R2 100kW C5 4.7mF PVCC3 PG2 PG2 LX3-1 CTL3 L4 1.0mH CTLMAIN 3.3V SCL SDA LX3-2 DVCC IN3 SCL SDA VO3 C10 33mF DD3:3.30V Io(max):600mA PGND3 MODE ADDSEL VREF18 R3 100kW PG3 PG3 GND C6 1.0mF Document Number: 002-08447 Rev.*A March 28, 2016 Page 48 of 68 S6AP412A Table 3. Parts list Symbol Parts Part number Specifications Vendor L1 Inductor 1276AS-H-1R0M 1.0H TOKO L2 Inductor 1276AS-H-1R0M 1.0H TOKO L3 Inductor 1276AS-H-1R0M 1.0H TOKO L4 Inductor 1276AS-H-1R0M 1.0H TOKO C1 Ceramic Capacitor C1608X5R1H104K 0.1F TDK C2 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C3 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C4 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C5 Ceramic Capacitor C1608X5R1V475K 4.7F TDK C6 Ceramic Capacitor C2012X5R1A336M 1.0F TDK C7 Ceramic Capacitor C1608X5R1H105K 22F TDK C8 Ceramic Capacitor C1608X5R1H105K 22F TDK C9 Ceramic Capacitor C1608X5R1H105K 22F TDK C10 Ceramic Capacitor C2012X5R1A336M 33F TDK R1 Resistor RR0816P-104-D 100k SSM R2 Resistor RR0816P-104-D 100k SSM R3 Resistor RR0816P-104-D 100k SSM TOKO TDK SSM : TOKO, INC. : TDK Corporation : SUSUMU CO., LTD. Document Number: 002-08447 Rev.*A March 28, 2016 Page 49 of 68 S6AP412A 24. Reference Data DCDC Convertor Efficiency Data Inductor and capacitor value refer to section 26. DD1 Input voltage = 3.3V, Vo=1.0V setting Input voltage = 3.3V, Vo=1.2V setting 90 80 80 70 70 Efficiency[%] 100 90 Efficiency[%] 100 60 50 40 30 20 50 40 30 20 Fixed PWM 10 0 0.00001 60 0.001 0.1 Load current[A] 0 0.00001 10 Input voltage = 5.5V, Vo = 1.0V setting 80 70 70 Efficiency[%] 90 80 Efficiency[%] 100 90 60 50 40 30 0 0.00001 0.001 0.1 Load current[A] 10 60 50 40 30 20 Fixed PWM 10 PFM/PWM Input voltage = 5.5V, Vo = 1.2V setting 100 20 Fixed PWM 10 PFM/PWM 0.001 0.1 Load current[A] Fixed PWM PFM/PWM 10 PFM/PWM 0 0.00001 10 0.001 0.1 Load current[A] 10 DD2 Input voltage = 3.3V, Vo = 1.8V setting 100 100 90 90 80 80 70 70 Efficiency[%] Efficiency[%] Input Voltage = 3.3V, Vo = 1.5V setting 60 50 40 30 60 50 40 30 20 Fixed PWM 20 10 PFM/PWM 10 0 0.00001 0.001 0.1 Load current[A] Document Number: 002-08447 Rev.*A 10 March 28, 2016 0 0.00001 Fixed PWM PFM/PWM 0.001 0.1 Load current[A] 10 Page 50 of 68 S6AP412A DD2 Input voltage = 5.5V, Vo = 1.5V setting Input Voltage = 5.5V, Vo = 1.8V setting 100 100 90 90 80 Efficiency[%] Efficiency[%] 80 70 60 50 40 30 60 50 40 30 20 20 Fixed PWM 10 0 0.00001 70 PFM/PWM 0.001 0.1 Load current[A] Fixed PWM 10 0 0.00001 10 PFM/PWM 0.001 0.1 Load current[A] 10 DD3 Input Voltage = 5.5V, Vo = 3.3V setting 100 100 90 90 80 80 70 70 Efficiency[%] Efficiency[%] Input voltage = 3.3V, Vo = 3.3V setting 60 50 40 30 60 50 40 30 20 Fixed PWM 20 10 PFM/PWM 10 0 0.00001 0.001 0.1 Load current[A] Document Number: 002-08447 Rev.*A 10 March 28, 2016 0 0.00001 Fixed PWM PFM/PWM 0.001 0.1 Load current[A] 10 Page 51 of 68 S6AP412A DCDC Convertor Regulation Data DD1 Input voltage = 3.3V, Vo=1.2V setting 1.020 1.220 1.015 1.215 1.010 1.210 Output voltage[V] Output voltage[V] Input voltage = 3.3V, Vo = 1.0V setting 1.005 1.000 0.995 0.990 Fixed PWM 0.985 PFM/PWM 0.980 1.200 1.195 1.190 Fixed PWM 1.185 PFM/PWM 1.180 0.0 1.0 2.0 3.0 Load current[A] 4.0 Input voltage = 5.5V, Vo = 1.0V setting 0.0 1.0 2.0 3.0 Load current[A] 4.0 Input voltage = 5.5V, Vo = 1.2V setting 1.220 1.020 1.215 Output voltage[V] 1.015 Output voltage[V] 1.205 1.010 1.005 1.000 0.995 0.990 Fixed PWM 0.985 PFM/PWM 1.210 1.205 1.200 1.195 1.190 Fixed PWM 1.185 PFM/PWM 1.180 0.980 0.0 1.0 2.0 3.0 Load current[A] 0.0 4.0 1.0 2.0 3.0 Load current[A] 4.0 DD2 Input voltage = 3.3V, Vo = 1.8V setting 1.520 1.820 1.515 1.815 1.510 1.810 Output voltage[V] Output voltage[V] Input Voltage = 3.3V, Vo = 1.5V setting 1.505 1.500 1.495 1.490 Fixed PWM 1.485 PFM/PWM 1.480 0.0 0.4 0.8 Load current[A] Document Number: 002-08447 Rev.*A 1.2 March 28, 2016 1.805 1.800 1.795 1.790 Fixed PWM 1.785 PFM/PWM 1.780 0.0 0.4 0.8 Load current[A] 1.2 Page 52 of 68 S6AP412A DD2 Input Voltage = 5.5V, Vo = 1.8V setting 1.520 1.820 1.515 1.815 1.510 1.810 Output voltage[V] Output voltage[V] Input voltage = 5.5V, Vo = 1.5V setting 1.505 1.500 1.495 1.490 Fixed PWM 1.485 PFM/PWM 1.480 1.805 1.800 1.795 1.790 Fixed PWM 1.785 PFM/PWM 1.780 0.0 0.4 0.8 Load current[A] 1.2 0.0 0.4 0.8 Load current[A] 1.2 DD3 Input Voltage = 5.5V, Vo = 3.3V setting 3.320 3.320 3.315 3.315 3.310 3.310 Output voltage[V] Output voltage[V] Input voltage = 3.3V, Vo = 3.3V setting 3.305 3.300 3.295 3.290 Fixed PWM 3.285 PFM/PWM 3.280 3.305 3.300 3.295 3.290 Fixed PWM 3.285 PFM/PWM 3.280 0.0 0.2 0.4 0.6 Load current[A] Document Number: 002-08447 Rev.*A 0.0 0.2 0.4 0.6 Load current[A] March 28, 2016 Page 53 of 68 S6AP412A DCDC Convertor Output Ripple Voltage DD1 Input voltage = 3.3V, Vo = 1.0V setting Load current = 0mA , Fixed PWM Input voltage = 3.3V, Vo=1.0V setting Load current = 4000mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 4000mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo = 1.0V setting Load current = 0mA , PFM/PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo=1.0V setting Load current = 4000mA,PFM/PWM 10mV/div, 0.5s/div 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , PFM/PWM Input voltage = 5.5V, Vo = 1.0V setting Load current = 4000mA,PFM/PWM 10mV/div, 2ms/div Document Number: 002-08447 Rev.*A March 28, 2016 10mV/div, 0.5s/div Page 54 of 68 S6AP412A DD2 Input voltage = 3.3V, Vo = 1.8V setting Load current = 0mA , Fixed PWM Input voltage = 3.3V, Vo=1.8V setting Load current = 1200mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.8V setting Load current = 0mA , Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 1.8V setting Load current =1200mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo = 1.8V setting Load current = 0mA , PFM/PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo=1.8V setting Load current =1200mA,PFM/PWM 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.8V setting Load current = 0mA , PFM/PWM Input voltage = 5.5V, Vo = 1.8V setting Load current = 1200mA,PFM/PWM 10mV/div, 2ms/div Document Number: 002-08447 Rev.*A 10mV/div, 0.5s/div March 28, 2016 10mV/div, 0.5s/div Page 55 of 68 S6AP412A Input voltage = 3.3V, Vo = 3.3V setting Load current = 0mA , Fixed PWM Input voltage = 3.3V, Vo=3.3V setting Load current = 600mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 3.3V setting Load current = 0mA , Fixed PWM 10mV/div, 0.5s/div Input voltage = 5.5V, Vo = 3.3V setting Load current =600mA, Fixed PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo = 3.3V setting Load current = 0mA , PFM/PWM 10mV/div, 0.5s/div Input voltage = 3.3V, Vo=3.3V setting Load current = 600mA,PFM/PWM 10mV/div, 0.5s/div 10mV/div, 2ms/div Input voltage = 5.5V, Vo = 1.0V setting Load current = 0mA , PFM/PWM Input voltage = 3.3V, Vo =3.3V setting Load current = 600mA,PFM/PWM 10mV/div, 2ms/div Document Number: 002-08447 Rev.*A March 28, 2016 10mV/div, 0.5s/div Page 56 of 68 S6AP412A DCDC Convertor Enable/Disable DD1(Fixed PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = 4000mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.0V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG1(6V/div) PG1(6V/div) 1.01ms Vo(0.5V/div) Vo(0.5V/div) 200us/div 510ms 200ms/div IIN(1.0A/div) IIN(40mA/div) DD1(PFM/PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = 4000mA, Tss = 1ms setting 8 Input voltage = 3.3V, Vo=1.0V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG1(6V/div) PG1(6V/div) 1.01ms Vo(0.5V/div) Vo(0.5V/div) 200us/div 515ms 200ms/div IIN(1.0A/div) IIN(40mA/div) DD2(Fixed PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = 1200mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.8V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG2(6V/div) PG2(6V/div) 1.02ms Vo(1V/div) Vo(1V/div) 200us/div 200ms 50ms/div IIN(500mA/div) IIN(40mA/div) Document Number: 002-08447 Rev.*A March 28, 2016 Page 57 of 68 S6AP412A DD2(PFM/ PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = 1200mA, Tss = 1ms setting Input voltage = 3.3V, Vo=1.8V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG2(6V/div) PG2(6V/div) 1.03ms Vo(1V/div) Vo(1V/div) 200us/div 204ms 50ms/div IIN(500mA/div) IIN(40mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG3(6V/div) PG3(6V/div) 0.99ms Vo(2V/div) Vo(2V/div) 270ms 200us/div 100ms/div IIN(500mA/div) IIN(40mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting SCL(3V/div) SCL(3V/div) PG3(6V/div) PG3(6V/div) 1.0ms Vo(2V/div) 200us/div Vo(2V/div) 270ms 100ms/div IIN(500mA/div) IIN(40mA/div) Document Number: 002-08447 Rev.*A March 28, 2016 Page 58 of 68 S6AP412A DCDConvertor Load Transient DD1(Fixed PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = from 0mA to 4000mA per 10us Input voltage = 3.3V, Vo=1.0V setting Load current = from 4000mA to 0mA per 10us Vo1(100mV/div) offset1.000V 82.5mV Vo1(100mV/div) offset1.000V 82.5mV 10us 10us Io(2.0A/div) Io(2.0A/div) DD1(PFM/PWM) Input voltage = 3.3V, Vo = 1.0V setting Load current = from 0mA to 4000mA per 10us Input voltage = 3.3V, Vo=1.0V setting Load current = from 4000mA to 0mA per 10us Vo1(100mV/div) offset1.000V 84.1mV Vo1(100mV/div) offset1.000V 82.5mV 50ms 10us Io(2.0A/div) Io(2.0A/div) DD2(Fixed PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = from 0mA to 1200mA per 10us Input voltage = 3.3V, Vo=1.8V setting Load current = from 1200mA to 0mA per 10us Vo2(50mV/div) offset1.8V 54.1mV Vo1(50mV/div) offset1.8V 54.8mV 10us 10us Io(1.0A/div) Io(1.0A/div) Document Number: 002-08447 Rev.*A March 28, 2016 Page 59 of 68 S6AP412A DD2(PFM/ PWM) Input voltage = 3.3V, Vo = 1.8V setting Load current = from 0mA to 1200mA per 10us Input voltage = 3.3V, Vo=1.8V setting Load current = from 1200mA to 0mA per 10us 57.1mV Vo2(50mV/div) offset1.8V Vo1(50mV/div) offset1.8V 54.0mV 10ms 10us Io(1.0A/div) Io(1.0A/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting Vo3(50mV/div) offset3.3V 54.7mV Vo3(50mV/div) offset3.3V 59.5mV 10us 10us Io(500mA/div) Io(500mA/div) DD3 (Fixed PWM) Input voltage = 3.3V, Vo = 3.3V setting Load current = 600mA, Tss = 1ms setting Input voltage = 3.3V, Vo=3.3 V setting Load current = 0mA, Tss = 1ms setting Vo3(50mV/div) offset3.3V 84mV Vo3(50mV/div) offset3.3V 83mV 20ms 10us Io(500mA/div) Io(500mA/div) Document Number: 002-08447 Rev.*A March 28, 2016 Page 60 of 68 S6AP412A DCDC Convertor DVFS Function DD1 (Fixed PWM) Input voltage = 3.3V, Input voltage = 3.3V 2 2 Vo =from 0.7V to 1.32V setting by I C Vo =from 1.32V to 0.7V setting by I C SCL (2V/div) SCL (2V/div) PG (5V/div) PG (5V/div) Vo1 (200mV/div) offset0.7V Document Number: 002-08447 Rev.*A 100us Vo1 (200mV/div) offset0.7V March 28, 2016 100us Page 61 of 68 S6AP412A 25. Ordering Information Table 4. Ordering Information Part Number Package Remarks S6AP412A18GN1C000 S6AP412A28GN1C000 S6AP412A38GN1C000 S6AP412A58GN1C000 S6AP412A68GN1C000 S6AP412A78GN1C000 S6AP412A98GN1C000 32-pin plastic QFN (WNT032) S6AP412AA8GN1C000 S6AP412AB8GN1C000 S6AP412AD8GN1C000 S6AP412AE8GN1C000 S6AP412AF8GN1C000 Document Number: 002-08447 Rev.*A March 28, 2016 Page 62 of 68 S6AP412A 26. Preset Code List Preset Code DD1 Output Voltage Preset Code Value DD2 Output Voltage Preset Code Value DD3 Output Voltage Preset Code Value 18 0.90V 1.35V 3.30V 28 0.90V 1.50V 3.30V 38 0.90V 1.80V 3.30V 58 1.00V 1.35V 3.30V 68 1.00V 1.50V 3.30V 78 1.00V 1.80V 3.30V 98 1.10V 1.35V 3.30V A8 1.10V 1.50V 3.30V B8 1.10V 1.80V 3.30V D8 1.20V 1.35V 3.30V E8 1.20V 1.50V 3.30V F8 1.20V 1.80V 3.30V Document Number: 002-08447 Rev.*A March 28, 2016 Page 63 of 68 S6AP412A 27. Layout Consider the points listed below and do the layout design. Provide the ground plane as much as possible on the IC mounted face. GND and PGNDx provide the through hole proximal to GND and PGNDx pins of IC, and connect it with GND of internal layer. Provide the power plane as much as possible to lower impedance of VCC. Play the most attention to the loop composed of input capacitor (CPVCCx) and SWFET. Input capacitor (CPVCCx) connected with PVCCx should be placed close to the pin as much as possible to make the current loop as small as possible. Also connect the GND pin of the input capacitor with PGNDx. Output capacitor (CVO3) connected with VO3 should be placed close to the pin as much as possible. Also connect the GND pin of the output capacitor with PGND3. GND pins of the switching system parts provide the through hole at the proximal place, and connect it with GND of internal layer. By-pass capacitor (CVREF, CAVCC) connected with VREF and AVCC should be placed close to the pin as much as possible. Also connect the GND pin of the by-pass capacitor with GND of internal layer in the proximal through-hole. Pull the feedback line to be connected to the INx pin of the IC separately from near the output capacitor pin, whenever possible. Consider the line connected with INx pins to keep away from a switching system parts as much as possible because it is sensitive to the noise. There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and parts sensitive to noise should be considered to be placed away from the inductor (or backside of place equipped with inductor). Switching system parts: Input capacitor(CPVCCx), Inductor(L), Output capacitor(CVOx) Note: * x: Each channel number Figure 6. Layout Example Layout example of IC Layout example of switching components 1 GND CPVCC1A PGNDx PVCC1B PGND1B PVCC1A PGND1A CPVCC1B PVCCx CPVCCx CVREF L VREF To the LXx pin Through Hole AVCC CAVCC CVOx GND Output voltage VOx feedback (Top View) Layout example of switching components 2 EP(Exposed Pad) Output voltage VO3 feedback PVCC2 CVO3 To the LX3-2 pin PVCC3 PGND3 GND 1pin Surface Layer PVCC3 PGND3 CVO3 PGND2 VO3 CPVCC3 L CPVCC2 Inner Layer Document Number: 002-08447 Rev.*A To the LX3-1 pin March 28, 2016 CPVCC3 GND Page 64 of 68 S6AP412A 28. Package Dimensions Document Number: 002-08447 Rev.*A March 28, 2016 Page 65 of 68 S6AP412A 29. Major Changes Spansion Publication Number: S6AP412A_DS405-00018 Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 - - Preliminary Full production 50 26. Measurement Circuit for Characteristics of General Operation Revised the Parts number of Component list 1278AS-H-1R0M 1276AS-H-1R0M 63 28. Ordering Information Revised the Part number of Ordering Information NOTE: Please see "Document History" about later revised information. Document Number: 002-08447 Rev.*A March 28, 2016 Page 66 of 68 S6AP412A Document History 2 Document Title: S6AP412A 3ch DC/DC Converter with I C Interface and Internal SW FETs Document Number: 002-08447 Revision ECN Orig. of Change Submission Date ** TAOA 12/26/2014 *A 5157734 TAOA 03/28/2016 Updated to Cypress template Document Number: 002-08447 Rev.*A Description of Change Migrated to Cypress and assigned document number 002-08447. No change to document contents or format. March 28, 2016 Page 67 of 68 S6AP412A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 002-08447 Rev.*A March 28, 2016 Page 68 of 68