2010 Microchip Technology Inc. DS41302D
PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
DS41302D-page 2 2010 Microchip Technology Inc.
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2010 Microchip Technology Inc. DS41302D-page 3
PIC12F609/615/617/12HV609/615
High-Performance RISC CPU:
Only 35 Instructions to Lea rn:
- All single-cycle instructions except branches
Ope rati ng Speed:
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
Interrupt Capability
8-Level Deep Hardware Stack
Direct, Indirect and Relative Addressing modes
S pecial Microcontroller Features:
Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Softwa re selectable frequency: 4 MHz or
8 MHz
Power-Saving Sleep mode
Volt a ge Range:
- PIC12F609/615/617: 2.0V to 5.5V
- PIC12HV609/615: 2.0V to user defined
maximum (see note)
Indus tri al and Extended Tem pe ratu r e Range
Power-on Reset (P OR)
Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Brown-out Reset (BOR)
Watchdog Timer (WDT) with independent
Oscillator for Reliable Operation
Multiplexed Master Clear with Pull-up/Input Pin
Programmable Code Protection
High Endurance Flash:
- 10 0,000 write Flash endurance
- F lash r etention: > 40 y ears
Self Read/ Write Program Memory (PIC12F617
only)
Low-Power Features:
Standby Current:
- 50 nA @ 2.0V, typical
Ope rati ng Curren t:
-11A @ 32 kHz, 2.0V, typical
-260A @ 4 MHz, 2.0V, typical
Watchdog Timer Current:
-1A @ 2.0V, typical
Note: Voltage across the shunt regulator should
not exceed 5V.
Peripheral Feat ures:
Shunt Voltage Regulator (PIC12HV609/615 only):
- 5 volt regulati on
- 4 mA to 50 mA shunt range
5 I/O Pins and 1 Input Only
High Current Source/Sink for Direct LED Drive
- Interrupt-on-pin change or pins
- Individually programmable weak pull-ups
Analog Comparator mo dule with:
- One analog comparator
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and output externally
accessible
- Built-In Hysteresis (software selectable)
Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Timer1 Gate (cou nt enab le )
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
- Option to use system clock as Timer1
In-C ircuit Seri al Prog ram mingTM (ICSPTM) via Two
Pins
PIC12F615/617/HV615 ONLY:
Enhanced Capture, Compare, PWM module:
- 1 6-bit Capture, max. resolution 12.5 ns
- Compare, max. resolution 200 ns
- 10-bit PWM with 1 or 2 output channels, 1
output channel programmable “dead time,”
max. frequency 20 kHz, auto-shutdown
A/D Converter:
- 10-bit resolution and 4 channels, samples
internal voltage references
Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
PIC12F609/615/617/12HV609/615
DS41302D-page 4 2010 Microchip Technology Inc.
8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)
TABLE 1: PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
Device
Program
Memory Data Me mo ry Self Read/
Self Write I/O 10-bit A/D
(ch) Comparators ECCP Timers
8/16-bit Voltage Range
Flash
(words) SRAM (bytes)
PIC12F609 1024 64 50 1 1/1 2.0V-5.5V
PIC12HV609 1024 64 50 1 1/1 2.0V-user defined
PIC12F615 1024 64 5 4 1 YES 2/1 2.0V-5.5V
PIC12HV615 1024 64 5 4 1 YES 2/1 2.0V-u ser defined
PIC12F617 2048 128 YES 5 4 1 YES 2/1 2.0V-5.5V
I/O Pin Comparators Timer Interrupts Pull-ups Basic
GP0 7CIN+ IOC YICSPDAT
GP1 6 CIN0- IOC Y ICSPCLK
GP2 5COUT T0CKI INT/IOC Y
GP3(1) 4— IOC Y(2) MCLR/VPP
GP4 3CIN1- T1G IOC YOSC2/CLKOUT
GP5 2 T1CKI IOC Y OSC1/CLKIN
1 VDD
8 ——— VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR.
1
2
3
45
6
7
8
PIC12F609/
HV609
VSS
GP0/CIN+/ICSPDAT
GP1/CIN0-/ICSPCLK
GP2/T0CKI/INT/COUT
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/CIN1-/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
2010 Microchip Technology Inc. DS41302D-page 5
PIC12F609/615/617/12HV609/615
8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)
TABLE 2: PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
I/O Pin Analog Comparator
sTimer CCP Interrupts Pull-ups Basic
GP0 7AN0 CIN+ P1B IOC YICSPDAT
GP1 6 AN1 CIN0- IOC Y ICSPCLK/VREF
GP2 5AN2 COUT T0CKI CCP1/P1A INT/IOC Y
GP3(1) 4— T1G*— IOCY
(2) MCLR/VPP
GP4 3AN3 CIN1- T1G P1B* IOC YOSC2/CLKOUT
GP5 2 T1CKI P1A* IOC Y OSC1/CLKIN
1 VDD
—8 VSS
* Alternate pin function.
Note 1: Input only.
2: Only when pin is configured for external MCLR.
1
2
3
45
6
7
8
PIC12F615/
617/HV615
VSS
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
VDD
GP5/T1CKI/P1A*/OSC1/CLKIN
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
GP3/T1G*/MCLR/VPP
* Alternate pin function.
PIC12F609/615/617/12HV609/615
DS41302D-page 6 2010 Microchip Technology Inc.
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7
2.0 Memory Organization.................................................. ...... .... ............... .... ............. ...... .......... ...... ...... ......... ...... ...... ...... ..... ...... .. 11
3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................... .... .. ....... .... .... .. .... ....... ............................ 27
4.0 Oscillator Module ....................................................................................................................................................................... 37
5.0 I/O Port ...................................................................................................................................................................................... 43
6.0 Timer0 Module .......................................................................................................................................................................... 53
7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57
8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65
9.0 Comparator Module ................................................................................................................................................................... 67
10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) .............. .... .. ......... .... .... .. .... ......... ........................... 79
11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89
12.0 Special Features of the CPU ............. .......... ........... .......... ................................ .......... ............................................................. 107
13.0 Voltage Regulator .................................................................................................................................................................... 127
14.0 Instr u ction Set Su mma ry ..... ........... .......... ........... ..................... .......... ..................... ............................................................... 129
15.0 Development Support ....................................... ......... .. .... .. .... ....... .... .. .... .. ......... .. .... .. .... ......................................................... 139
16.0 Electrical Specifications ........................................................................................................................................................... 143
17.0 DC and AC Characteristics Graphs and Tables ........................................................................ .... .......................................... 171
18.0 Pack a ging Information ... .......... ........... .......... ..................... ..................... ........... ..................................................................... 195
Appendix A: Data Sheet Revision History ............................................................. ........... .... ...... ....................................................... 203
Appendix B: Migrating from other PIC® Devices ........................ ........... .......... ........... .......... ........... ...... ..................... .......... ............. 203
Index................................................................................................................................................................................................. 205
The Micro chip Web Site ......... ............................... ........... ..................... ..................... .......... ............................................................. 209
Customer Change Notification Service ....................................................... ...... ................. ........ ....................................................... 209
Customer Support ............................................................................................................................................................................. 209
Reader Response ............................................................................................................................................................................. 210
Product Identification System ............................................................................................................................................................ 211
Worldwide Sa les and Service ............ ........... .......... ........... .......... ........... .......... ........... .......... ... ........................................................ 212
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2010 Microchip Technology Inc. DS41302D-page 7
PIC12F609/615/617/12HV609/615
1.0 DEVICE OVERVIEW
The PIC12F609/615/617/12HV609/615 devices are
covered by this data sheet. They are available in 8-pin
PDIP, SOIC, MSOP and DFN packages.
Block Diagrams and pinout descriptions of the devices
are as follows:
PIC12F609/HV609 (Figure 1-1, Table 1-1)
PIC12F615/617/HV615 (Figure 1-2, Table 1-2)
FIGURE 1-1: PIC12F 60 9/HV609 BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack 64 Bytes
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
Timer0 Timer1
GP0
GP1
GP2
GP3
GP4
GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
and Reference
T1G VDD
Block
CIN+
CIN0-
CIN1-
COUT
Comparator Voltage Reference
Absolute V oltage Reference
Shunt Regulator
(PIC12HV609 only)
PIC12F609/615/617/12HV609/615
DS41302D-page 8 2010 Microchip Technology Inc.
FIGURE 1-2: PIC12F615/617/HV615 BLOCK DIAGRAM
Flash
Program
Memory
13 Data Bus 8
14
Program
Bus
Instruction Reg
Program Counter
RAM
File
Registers
Direct Addr 7
RAM Addr 9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
GPIO
8
8
8
3
8-Level Stack 64 Bytes and
1K X 14
(13-Bit)
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
MCLR VSS
Brown-out
Reset
Timer0 Timer1
GP0
GP1
GP2
GP3
GP4
GP5
Analog Comparator
T0CKI
INT
T1CKI
Configuration
Internal
Oscillator
VREF
and Reference
T1G VDD
Timer2
Block Shunt Regulator
(PIC12HV615 only)
Analog-To-Digital Converter
AN0
AN1
AN2
AN3
CIN+
CIN0-
CIN1-
COUT
ECCP
CCP1/P1A
P1B
P1A*
P1B*
Comparator Voltage Reference
Absolute V oltage Reference
* Altern ate pin func ti on.
** For the PIC12F617 only.
T1G*
2K X 14* *
and
128 Bytes**
2010 Microchip Technology Inc. DS41302D-page 9
PIC12F609/615/617/12HV609/615
TABLE 1-1: PIC12F609/HV609 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/CIN+/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN+ AN Comparator non-inverting input
ICSPDAT S T C MOS Serial Programm ing Data I/O
GP1/CIN0-/ICSPCLK GP1 TTL CMOS General purpose I/O with prog. pull-up and int errupt -on-c hange
CIN0- AN Comparator inverting input
ICSPCLK ST Serial Programm ing Clock
GP2/T0CKI/INT/COUT GP2 ST CMOS General purpose I/O with prog. pull-up and interrupt-on-change
T0CKI ST Timer0 clock input
INT ST External Interrupt
COUT CMOS Comparator output
GP3/MCLR/VPP GP3 TTL General purpose input with interrupt-on-change
MCLR ST Master Clear w/internal pull-up
VPP HV Programming voltage
GP4/CIN1-/T1G/OSC2/
CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN1- AN Comparator inverting input
T1G ST Timer1 gate (count enable)
OSC2 XTAL Crystal/Resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-change
T1CKI ST Timer1 clock input
OSC1 XTAL Crystal/Resonator
CLKIN ST External clock input/RC oscillator connection
VDD VDD Power Positive supply
VSS VSS Power Ground reference
Legend: AN=A nalog input or output CMOS= CMOS com patible input or output HV= High Voltage
ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input XTAL=Crystal
PIC12F609/615/617/12HV609/615
DS41302D-page 10 2010 Microchip Technology Inc.
TABLE 1-2: PIC12F615/617/HV615 PINOUT DESCRIPTION
Name Function Input
Type Output
Type Description
GP0/AN0/CIN+/P1B/ICSPDAT GP0 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN0 AN A/ D Channel 0 input
CIN+ AN Comparator non-inverting input
P1B CMOS PWM output
ICSPDAT S T C MOS Serial Programm ing Data I/O
GP1/AN1/CIN0-/VREF/ICSPCLK GP1 TTL C MOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN1 AN A/ D Channel 1 input
CIN0- AN Comparator inverting input
VREF AN Ext ernal Voltage Reference for A/D
ICSPCLK ST Serial Programm ing Clock
GP2/AN2/T0CKI/INT/COUT/CCP1/
P1A GP2 ST CMO S General purpose I/O with prog. pull-up and interrupt-on-
change
AN2 AN A/ D Channel 2 input
T0CKI ST Timer0 clock input
INT ST External Interrupt
COUT CMOS Comparator output
CCP1 ST CMOS Capt ure input/Compare input/PWM output
P1A CMOS PWM output
GP3/T1G*/MCLR/VPP GP3 TTL General purpose input with interrupt-on-change
T1G* ST Timer1 gate (count enable), alternate pin
MCLR ST Master Clear w/internal pull-up
VPP HV Programming voltage
GP4/AN3/CIN1-/T1G/P1B*/OSC2/
CLKOUT GP4 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN3 AN A/ D Channel 3 input
CIN1- AN Comparator inverting input
T1G ST Timer1 gate (count enable)
P1B* CMOS PWM output, alternate pin
OSC2 XTAL Crystal/Resonator
CLKOUT CMOS FOSC/4 output
GP5/T1CKI/P1A*/OSC 1/CLKIN GP5 TTL CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
T1CKI ST Timer1 clock input
P1A* CMOS PWM output, alternate pin
OSC1 XTAL Crystal/Resonator
CLKIN ST External clock input/RC oscillator connection
VDD VDD Power Positive supply
VSS VSS Power Ground reference
* Alternate pin function.
Legend: A N=Analog in put or output CMOS= C MO S com patible input or output HV= High Voltage
ST=Schmitt Trigger input with CMOS levels TTL =TTL compatible input XTAL=Crystal
2010 Microchip Technology Inc. DS41302D-page 11
PIC12F609/615/617/12HV609/615
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F609/615/617/12HV609/615 has a 13-bit
program counter capable of addressing an 8K x 14
progra m mem ory sp a ce. On ly the fi rst 1 K x 14 (0 000 h-
03FFh) for the PIC12F609/615/12HV609/615 is
physically implemented. For the PIC12F617, the first
2K x 14 (0000h-07FFh) is physically implemented.
Accessing a location above these boundaries will
cause a wrap-around within the first 1K x 14 space for
PIC12F609/615/12HV609/615 devices, and within the
first 2K x 14 space for the PIC12F617 device. The
Reset vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F617
2.2 Data Memory Organization
The data memory (see Figure 2-3) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. For the PIC12F617, the register locations
20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general
purpose registers implemented as Static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
0 when read. The RP0 bit of the STATUS register is the
bank select bit.
RP0
0Bank 0 is selected
1Bank 1 is selected
PC<12:0>
13
0000h
0004h
0005h
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Wraps to 0000h-03FFh
Note: The IRP and RP1 bits of the STATUS
register are reserved and should always be
maint ained as 0’s.
PC<12:0>
13
0000h
0004h
0005h
07FFh
Stack Level 1
Stack Level 8
Re set Vector
Interrupt Vector
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Page 0
On-Chip
Program
Memory
Wraps to 0000h-07FF h 0800h
1FFFh
PIC12F609/615/617/12HV609/615
DS41302D-page 12 2010 Microchip Technology Inc.
2.2.1 GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615, and as 128 x 8 in the
PIC12F617. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
(see Section 2.4 “Indirect Addressing, INDF and
FSR Registers” ).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
FIGURE 2-3: DATA MEMORY MAP OF
THE PIC12F60 9/HV 609
Indirect Addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented da ta memory locations, read as ‘0’.
Note 1: Not a physical register.
General
File
Address File
Address
WPU
IOC
Indirect Addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
ANSEL
Accesses 70h-7Fh F0h
VRCON
CMCON0
OSCTUNE
40h
3Fh
CMCON1
EFh
T1CON
Purpose
Registers
64 Bytes
Accesses 70h-7Fh
6Fh
70h
2010 Microchip Technology Inc. DS41302D-page 13
PIC12F609/615/617/12HV609/615
FIGURE 2-4: DATA MEMORY MAP OF
THE PIC12F615/617/HV615
Indirect Addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
7Fh
Bank 0
Unimplemented da ta memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Used for the PIC12F617 only.
File
Address File
Address
WPU
IOC
Indirect Addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
FFh
Bank 1
ADRESH
ADCON0
ADRESL
ANSEL
Accesses 70h-7Fh F0h
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
VRCON
CMCON0
OSCTUNE
PR2
40h
3Fh
CMCON1
EFh
APFCON
General
Purpose
Registers
64 Bytes
Acc esses 70h-7Fh
6Fh
70h
PMCON1
(2)
PMCON2
(2)
PMADRL
(2)
PMADRH
(2)
PMDATL
(2)
PMDATH
(2)
General
Purpose
Registers
96 Bytes from
20h-7Fh(2) Unimplemented for
PIC12F615/HV615
General
Purpose
Registers
32 Bytes(2)
Unimplemented for
PIC12F615/HV615
BFh
C0h
PIC12F609/615/617/12HV609/615
DS41302D-page 14 2010 Microchip Technology Inc.
TABLE 2-1: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 115
01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 115
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 115
03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 18, 115
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 115
05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 115
06h Unimplemented
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 115
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 2 0, 115
0Ch PIR1 —CMIF—TMR1IF---- 0--0 22, 115
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 115
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 6 2, 115
11h Unimplemented
12h Unimplemented
13h Unimplemented
14h Unimplemented
15h Unimplemented
16h Unimplemented
17h Unimplemented
18h Unimplemented
19h VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116
1Ah CMCON0 CMON COUT CMOE CMPOL —CMR—CMCH0000 -0-0 72, 116
1Bh
1Ch CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 73, 116
1Dh Unimplemented
1Eh Unimplemented
1Fh Unimplemented
Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: Read only register.
2010 Microchip Technology Inc. DS41302D-page 15
PIC12F609/615/617/12HV609/615
TABLE 2-2: PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on
POR, BOR Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116
01h TMR0 Timer0 Module’s Register xxxx xxxx 53, 116
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 25, 116
03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 18, 116
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116
05h GPIO GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 43, 116
06h Unimplemented
07h Unimplemented
08h Unimplemented
09h Unimplemented
0Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 20, 116
0Ch PIR1 ADIF CCP1IF —CMIF—TMR2IFTMR1IF-00- 0-00 22, 116
0Dh Unimplemented
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 57, 116
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 62, 116
11h TMR2(3) Timer2 Module Register 0000 0000 65, 116
12h T2CON(3) TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 66, 116
13h CCPR1L(3) Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 90, 116
14h CCPR1H(3) Capture/Compare/PWM Register 1 High Byte XXXX XXXX 90, 116
15h
CCP1CON
(3)
P1M DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 89, 116
16h
PWM1CON
(3)
PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 105,
116
17h ECCPAS(3) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 102,
116
18h Unimplemented
19h VRCON CMVREN VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 76, 116
1Ah CMCON0 CMON COUT CMOE CMPOL —CMR—CMCH0000 -0-0 72, 116
1Bh
1Ch CMCON1 T1ACS CMHYS T1GSS CMSYNC ---0 0-10 73, 116
1Dh Unimplemented
1Eh
ADRESH
(2, 3)
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 85, 116
1Fh ADCON0
(3)
ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 84, 116
Legend: – = Unimpl em ent ed locat io ns rea d as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: Read only register.
3: PIC12F615/617/HV615 only.
PIC12F609/615/617/12HV609/615
DS41302D-page 16 2010 Microchip Technology Inc.
TABLE 2-3: PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25, 116
81h OPTION_RE
GGPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 19, 116
82h PCL Program Coun ter’s (PC) Least Significa nt Byt e 0000 0000 25, 116
83h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 18, 116
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 25, 116
85h TRISIO TRISIO5 TRISIO4 TRISIO3(4) TRISIO2 TRISIO1 TRISIO0 --11 1111 44, 116
86h Unimplemented
87h Unimplemented
88h Unimplemented
89h Unimplemented
8Ah PCLATH Write Buffer for upper 5 bits of Program Counter ---0 0000 25, 116
8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF(3) 0000 0000 20, 116
8Ch PIE1 —CMIE—TMR1IE---- 0--0 21, 116
8Dh Unimplemented
8Eh PCON —PORBOR ---- --qq 23, 116
8Fh Unimplemented
90h OSCTUNE TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 41, 116
91h Unimplemented
92h Unimplemented
93h Unimplemented
94h Unimplemented
95h WPU(2) —WPU5WPU4 WPU2 WPU1 WPU0 --11 -111 46, 116
96h IOC IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 --00 0000 46, 116
97h Unimplemented
98h Unimplemented
99h Unimplemented
9Ah Unimplemented
9Bh Unimplemented
9Ch Unimplemented
9Dh Unimplemented
9Eh Unimplemented
9Fh ANSEL —ANS3 ANS1 ANS0 ---- 1-11 45, 117
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: GP3 pull-up is enabled when MCLRE is1’ in the Configuration Word register.
3: MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4: TRISIO3 always reads as ‘1’ since it is an input only pin.