BQ29702DSET - Texas Instruments

±4.0

±3.5

±3.0

±2.5

±2.0

±1.5

±1.0

±0.5

0.0

±40 ±20 0 20 40 60 80 100 120

OCD Detection Accuracy (mV)

Temperature (C)

C012

DOUT

COUT

V–

BAT

VSS

PACK +

PACK–

CELLN

CELLP

S S

0.1 µF

2.2 k

DSGCHG

330

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bq297xy Cost-Effective Voltage and Current Protection Integrated Circuit for Single-Cell

Li-Ion/Li-Polymer Batteries

1 Features 2 Applications

1• Input Voltage Range Pack+: VSS – 0.3 V to 12 V • Tablet PC

• FET Drive: • Mobile Handset

• Handheld Data Terminals

– CHG and DSG FET Drive Output

• Voltage Sensing Across External FETs for 3 Description

Overcurrent Protection (OCP) Is Within ± 5 mV The bq297xy battery cell protection device provides

(Typical) an accurate monitor and trigger threshold for

• Fault Detection overcurrent protection during high discharge/charge

– Overcharge Detection (OVP) current operation or battery overcharge conditions.

– Over-Discharge Detection (UVP) The bq297xy device provides the protection functions

– Charge Overcurrent Detection (OCC) for Li-Ion/Li-Polymer cells, and monitors across the

external power FETs for protection due to high

– Discharge Overcurrent Detection (OCD) charge or discharge currents. In addition, there is

– Load Short-Circuit Detection (SCP) overcharge and depleted battery monitoring and

• Zero Voltage Charging for Depleted Battery protection. These features are implemented with low

• Factory Programmed Fault Protection Thresholds current consumption in NORMAL mode operation.

– Fault Detection Voltage Thresholds Device Information(1)

– Fault Trigger Timers PART NUMBER PACKAGE BODY SIZE (NOM)

– Fault Recovery Timers bq29700 (2) WSON (6) 1.50 mm × 1.50 mm

• Modes of Operation Without Battery Charger (1) For all available packages, see the orderable addendum at

Enabled the end of the datasheet.

– NORMAL Mode ICC = 4 µA (2) For available released devices, see the Released Device

Configurations table.

– Shutdown Iq = 100 nA

• Operating Temperature Range TA= –40°C to

85°C

• Package:

– 6-Pin DSE (1.50 mm × 1.50 mm × 0.75 mm)

OCD Detection Accuracy Versus Temperature

4 Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

9.3 Test Circuit Diagrams ............................................. 14

1 Features.................................................................. 110 Detailed Description ........................................... 14

2 Applications ........................................................... 110.1 Overview ............................................................... 14

3 Description............................................................. 110.2 Functional Block Diagram..................................... 15

4 Simplified Schematic............................................. 110.3 Feature Description .............................................. 15

5 Revision History..................................................... 210.4 Device Functional Modes...................................... 15

6 Released Device Configurations.......................... 311 Applications and Implementation...................... 19

7 Pin Configuration and Functions......................... 311.1 Application Information.......................................... 19

7.1 Pin Descriptions........................................................ 311.2 Typical Application................................................ 19

8 Specifications......................................................... 412 Power Supply Recommendations ..................... 22

8.1 Absolute Maximum Ratings ...................................... 413 Layout................................................................... 22

8.2 Handling Ratings....................................................... 413.1 Layout Guidelines ................................................ 22

8.3 Recommended Operating Conditions....................... 413.2 Layout Example .................................................... 22

8.4 Thermal Information.................................................. 514 Device and Documentation Support................. 23

8.5 DC Characteristics.................................................... 514.1 Related Links ........................................................ 23

8.6 Programmable Fault Detection Thresholds ............. 514.2 Trademarks........................................................... 23

8.7 Programmable Fault Detection Timer Ranges ........ 614.3 Electrostatic Discharge Caution............................ 23

8.8 Typical Characteristics.............................................. 614.4 Glossary................................................................ 23

9 Parameter Measurement Information ................ 10 15 Mechanical, Packaging, and Orderable

9.1 Timing Charts.......................................................... 10 Information ........................................................... 23

9.2 Test Circuits............................................................ 12

5 Revision History

Changes from Original (March, 2014) to Revision A Page

• Changed part number in document to "bq297xy" from "bq29700"......................................................................................... 1

• Added notes to see the orderable addendum and Released Device Configurations table ................................................... 1

• Added Released Device Configurations table for part numbers bq29700 through bq29707................................................. 3

• Changed Terminal to Pin ....................................................................................................................................................... 3

• Added ohm symbol to value .................................................................................................................................................. 5

• Changed "RANGE" to "CONDITION" and "ACCURACY" to "MIN, TYP, and MAX" column headings ................................ 5

• Added prefix "Factory Device Configuration:" ....................................................................................................................... 5

• Added Factory Programmable Options reference ............................................................................................................... 14

• Added Factory Programmable Options table ....................................................................................................................... 14

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DOUT

1V–

COUT

BAT

VSS

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6 Released Device Configurations

PART OVP OVP OVP UVP UVP UVP OCC OCC OCC OCD OCD OCD SCD SCD

NUMBER (V) DELAY REC (V) DELAY REC (V) DELAY REC (V) DELAY REC (V) DELAY

(s) DELAY (ms) DELAY (ms) DELAY (ms) DELAY (µs)

(ms) (ms) (ms) (ms)

bq29700 4.275 1.25 12 2.800 144 8 0.100 8 8 0.100 20 8 0.5 250

bq29701 4.280 1.25 12 2.300 144 8 0.100 8 8 0.125 8 8 0.5 250

bq29702 4.350 1 12 2.800 96 8 0.155 8 8 0.160 16 8 0.3 250

bq29703 4.425 1.25 12 2.300 20 8 0.100 8 8 0.160 8 8 0.5 250

bq29704 4.425 1.25 12 2.500 20 8 0.100 8 8 0.125 8 8 0.5 250

bq29705 4.425 1.25 12 2.500 20 8 0.100 8 8 0.150 8 8 0.5 250

bq29706 3.850 1.25 12 2.500 144 8 0.150 8 8 0.200 8 8 0.6 250

bq29707 4.280 1 12 2.800 96 8 0.090 6 8 0.090 16 8 0.3 250

7 Pin Configuration and Functions

(DSE) 6 PIN

Pin Functions

PIN NAME PIN NUMBER TYPE DESCRIPTION

BAT 5 P VDD pin

COUT 2 O Gate Drive Output for Charge FET

DOUT 3 O Gate Drive Output for Discharge FET

NC 1 NC No Connection (electrically open, do not connect to BAT or VSS)

VSS 4 P Ground pin

V– 6 I/O Input pin for charger negative voltage

7.1 Pin Descriptions

7.1.1 Supply Input: BAT

This pin is the input supply for the device and is connected to the positive terminal of the battery pack. There is a

0.1-µF input capacitor to ground for filtering noise.

7.1.2 Cell Negative Connection: VSS

This pin is an input to the device for cell negative ground reference. Internal circuits associated with cell voltage

measurements and overcurrent protection input to differential amplifier for either Vds sensing or external sense

resistor sensing will be referenced to this node.

7.1.3 Voltage Sense Node: V–

This is a sense node used for measuring several fault detection conditions, such as overcurrent charging or

overcurrent discharging configured as Vds sensing for protection. This input, in conjunction with VSS, forms the

differential measurement for the stated fault detection conditions. A 2.2-kΩresistor is connected between this

input pin and Pack– terminal of the system in the application.

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Pin Descriptions (continued)

7.1.4 Discharge FET Gate Drive Output: DOUT

This pin is an output to control the discharge FET. The output is driven from an internal circuitry connected to the

BAT supply. This output will transition from high to low when a fault is detected, and requires the DSG FET to

turn OFF. A high impedance resistor of 5 MΩis connected from DOUT to VSS for gate capacitance discharge

when the FET is turned OFF.

7.1.5 Charge FET Gate Drive Output: COUT

This pin is an output to control the charge FET. The output is driven from an internal circuitry connected to the

BAT supply. This output transitions from high to low when a fault is detected, and requires the CHG FET to turn

OFF. A high impedance resistor of 5 MΩis connected from COUT to Pack– for gate capacitance discharge when

FET is turned OFF.

8 Specifications

8.1 Absolute Maximum Ratings(1)

MIN MAX UNIT

Input Voltage: BAT –0.3 12 V

Supply Control/Input V– Pin(Pack–) BAT – 28 BAT + 0.3 V

DOUT (Discharge FET Output), GDSG (Discharge FET Gate Drive) VSS – 0.3 BAT + 0.3 V

FET Drive and COUT (Charge FET Output), GCHG (Charge FET Gate Drive) BAT – 28 BAT + 0.3 V

Protection Operating Temperature: TFUNC –40 85 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 Handling Ratings MIN MAX UNIT

Tstg Storage temperature range –55 150 °C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(2) -2 2 kV

VESD(1) Electrostatic Charged device model (CDM), per JEDEC specification JESD22-C101,

Discharge -500 500 V

all pins(3)

(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges

into the device.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 1000 V

may have higher performance.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V

may have higher performance.

8.3 Recommended Operating Conditions(1)

MIN MAX UNIT

Positive Input Voltage: BAT –0.3 8 V

Supply Control/Input Negative Input Voltage: V– BAT – 25 BAT V

Discharge FET Control: DOUT VSS BAT V

FET Drive and

Protection Charge FET Control: COUT BAT – 25 BAT V

Operating Temperature: TAmb –40 85 °C

Storage Temperature: TS–55 150 °C

Temperature Ratings Lead Temperature (Soldering 10 s) 300 °C

Thermal Resistance Junction to Ambient, θJA(1) 250 °C/W

(1) For more information about traditional and new thermal metrics, see the IC package Thermal Metrics application report, SPRA953.

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8.4 Thermal Information

THERMAL METRIC(1) DSE (12 PINS) UNIT

RθJA, High K Junction-to-ambient thermal resistance(2) 190.5

RθJC(top) Junction-to-case(top) thermal resistance(3) 94.9

RθJB Junction-to-board thermal resistance(4) 149.3 °C/W

ψJT Junction-to-top characterization parameter(5) 6.4

ψJB Junction-to-board characterization parameter(6) 152.8

RθJC(bottom) Junction-to-case(bottom) thermal resistance(7) N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

8.5 DC Characteristics

Typical Values stated where TA= 25°C and BAT = 3.6 V. Min/Max values stated where TA= –40°C to 85°C, and BAT = 3.0 V

to 4.2 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT CONSUMPTION

BAT – VSS 1.5 8

VBAT Device Operating Range V

BAT – V– 1.5 28

INORMAL Current Consumption in NORMAL Mode BAT = 3.8 V, V– = 0 V 4 5.5 µA

IPower_down Current Consumption in Power Down Mode BAT = V– = 1.5 V 0.1 µA

FET OUTPUT, DOUT and COUT

VOL Charge FET Low Output IOL = 30 µA, BAT = 3.8 V 0.4 0.5 V

VOH Charge FET High Output IOH = –30 µA, BAT = 3.8 V 3.4 3.7 V

VOL Discharge FET Low Output IOL = 30 µA, BAT = 2.0 V 0.2 0.5 V

VOH Discharge FET High Output IOH = –30 µA, BAT = 3.8 V 3.4 3.7 V

PULL UP INTERNAL RESISTANCE ON V–

RV–D Resistance between V– and VBAT VBAT = 1.8 V, V– = 0 V 100 300 550 kΩ

CURRENT SINK ON V–

IV–S Current sink on V– to VSS VBAT = 3.8 V 8 24 µA

LOAD SHORT DETECTION ON V–

Vshort Short detection voltage VBAT = 3.8 V and RPackN = 2.2 kΩVBAT – 1 V V

0-V BATTERY CHARGE FUNCTION

V0CHG 0-V battery charging starter voltage 0-V battery charging function allowed 1.7 V

V0INH 0-V battery charging inhibit voltage 0-V battery charging function disallowed 0.75 V

8.6 Programmable Fault Detection Thresholds

PARAMETER CONDITION MIN TYP MAX UNIT

TA= 25°C –10 10 mV

Factory Device Configuration: 3.85 V to

VOVP Overcharge detection voltage TA= 0°C to

4.60 V in 50-mV steps –20 20 mV

60°C

Overcharge release hysteresis 100 mV and (VSS – V–) > OCC (min) for release, TA=

VOVP–Hys –20 20 mV

voltage 25°C

Product Folder Links: bq29700

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050

±40 ±20 0 20 40 60 80 100 120

Current Consumption (A)

Temperature (C)

C001

±40 ±20 0 20 40 60 80 100 120

Current Consumption (A)

Temperature (C)

C002

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Programmable Fault Detection Thresholds (continued)

PARAMETER CONDITION MIN TYP MAX UNIT

Over-discharge detection Factory Device Configuration: 2.00 V to 2.80 V in 50-mV

VUVP –50 50 mV

voltage steps, TA= 25°C

Over-discharge release

VUVP+Hys 100 mV and (BAT – V–) > 1 V for release, TA= 25°C –50 50 mV

hysteresis voltage TA= 25°C –10 10 mV

Discharging overcurrent Factory Device Configuration: 90 mV to

VOCD TA= –40°C to

detection voltage 200 mV in 5-mV steps –15 15 mV

85°C

Release of Release of discharging Release when BAT – V– > 1 V 1 V

VOCD overcurrent detection voltage TA= 25°C –10 10 mV

Charging overcurrent detection Factory Device Configuration: –45 mV to

VOCC TA= –40°C to

voltage –155 mV in 5-mV steps –15 15 mV

85°C

Release of Release of overcurrent Release when VSS – V– ≥OCC (min) 40 mV

VOCC detection voltage Factory Device Configuration: 300 mV,

VSCC Short Circuit detection voltage TA= 25°C –100 100 mV

400 mV, 500 mV, 600 mV

Release of Short Circuit

VSCCR Release when BAT – V– ≥1 V 1 V

detection voltage

8.7 Programmable Fault Detection Timer Ranges

PARAMETER CONDITION MIN TYP MAX UNIT

tOVPD Overcharge detection delay time Factory Device Configuration: 0.25 s, 1.0 s, 1.25 s, 4.5 s –20% 20% s

Over-discharge detection delay Factory Device Configuration: 20 ms, 96 ms, 125 ms, 144

tUVPD –20% 20% ms

time ms

Discharging overcurrent detection

tOCDD Factory Device Configuration: 8 ms, 16 ms, 20 ms, 48 ms –20% 20% ms

delay time

Charging overcurrent detection

tOCCD Factory Device Configuration: 4 ms, 6 ms, 8 ms, 16 ms –20% 20% ms

delay time

tSCCD Short Circuit detection delay time 250 µs (fixed) –50% 50% µs

8.8 Typical Characteristics

VBAT = 3.9 V

VBAT = 1.5 V

Figure 2. 3.9-V IBAT Versus Temperature

Figure 1. 1.5-V IBAT Versus Temperature

Product Folder Links: bq29700

1100

1150

1200

1250

1300

1350

±40 ±20 0 20 40 60 80 100 120

OVP Detection Delay Time (ms)

Temperature (C)

C007

±12

±10

±8

±6

±4

±2

±40 ±20 0 20 40 60 80 100 120

UVP Detection Accuracy Threshold (mV)

Temperature (C)

C008

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

±40 ±20 0 20 40 60 80 100 120

BAT ± VSS Voltage (V)

Temperature (C)

C005

±12

±10

±8

±6

±4

±2

±40 ±20 0 20 40 60 80 100 120

OVP Deetction Threshold Accuracy (mV)

Temperature (C)

C006

1.18

1.20

1.22

1.24

1.26

1.28

1.30

1.32

1.34

±40 ±20 0 20 40 60 80 100 120

Internal Oscillator Frequency (kHz)

Temperature (C)

C003

±1.46

±1.44

±1.42

±1.40

±1.38

±1.36

±1.34

±1.32

±40 ±20 0 20 40 60 80 100 120

V(±) ± BAT Voltage (V)

Temperature (C)

C004

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Typical Characteristics (continued)

FOSC, Setting = 1.255 kHz VBAT, Setting = 0 V

Figure 3. Internal Oscillator Frequency Versus Temperature Figure 4. 0-V Charging Allowed Versus Temperature

OVP, Setting = 4.275 V

Figure 5. 0-V Charging Disallowed Versus Temperature Figure 6. OVP Detection Accuracy Versus Temperature

tOVPD, Setting = 1.25 s UVP, Setting = 2.800 V

Figure 7. OVP Detection Dely Time Versus Temperature Figure 8. UVP Detection Accuracy Versus Temperature

Product Folder Links: bq29700

18.5

19.0

19.5

20.0

20.5

21.0

21.5

22.0

22.5

±40 ±20 0 20 40 60 80 100 120

OCD Detection Delay Time (ms)

Temperature (C)

C013

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

±40 ±20 0 20 40 60 80 100 120

SCC Detection Accuracy (mV)

Temperature (C)

C014

7.0

7.2

7.4

7.6

7.8

8.0

8.2

8.4

8.6

±40 ±20 0 20 40 60 80 100 120

OCC Detection Delay Time (ms)

Temperature (C)

C011

±4.0

±3.5

±3.0

±2.5

±2.0

±1.5

±1.0

±0.5

0.0

±40 ±20 0 20 40 60 80 100 120

OCD Detection Accuracy (mV)

Temperature (C)

C012

130

135

140

145

150

155

160

±40 ±20 0 20 40 60 80 100 120

UVP Detection Delay Time (ms)

Temperature (C)

C009

±1.8

±1.6

±1.4

±1.2

±1.0

±0.8

±0.6

±0.4

±0.2

0.0

±40 ±20 0 20 40 60 80 100 120

OCC Detection Accuracy (mV)

Temperature (C)

C010

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Typical Characteristics (continued)

tUVPD, Setting = 144 ms VOCC, Setting = –100 mV

Figure 9. UVP Detection Delay Time Versus Temperature Figure 10. OCC Detection Accuracy Versus Temperature

tOCCD, Setting = 8 ms VOCD, Setting = 100 mV

Figure 11. OCC Detection Delay Time Versus Temperature Figure 12. OCD Detection Accuracy Versus Temperature

tUVPD, Setting = 20 ms VSCC, Setting = 500 mV

Figure 13. OCD Detection Delay Time Versus Temperature Figure 14. SCC Detection Accuracy Versus Temperature

Product Folder Links: bq29700

3.7135

3.7140

3.7145

3.7150

3.7155

3.7160

±40 ±20 0 20 40 60 80 100 120

VOH (V)

Temperature (C)

C017

1.10

1.12

1.14

1.16

1.18

1.20

1.22

1.24

±40 ±20 0 20 40 60 80 100 120

Power On Reset Threshold (V)

Temperature (C)

C015

3.765

3.770

3.775

3.780

3.785

3.790

3.795

±40 ±20 0 20 40 60 80 100 120

VOH (V)

Temperature (C)

C016

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Typical Characteristics (continued)

VBAT, Setting = 3.9 V

Figure 15. Power On Reset Versus Temperature Figure 16. COUT Versus Temperature with Ioh = –30 µA

VBAT, Setting = 3.9 V

Figure 17. DOUT Versus Temperature with Ioh = –30 µA

Product Folder Links: bq29700

BAT

DOUT

COUT

V–

OVP

VOVP–Hys

tOVPD

VUVP

BAT

VSS

BAT

VSS

PACK–

BAT

VSS

PACK–

OCD

Normal Overcharge Normal

Over-

Discharge Normal

tUVPD

Charger

Connected

Charger

Connected

Load

Connected

UVP–Hys

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9 Parameter Measurement Information

9.1 Timing Charts

Figure 18. Overcharge Detection, Over-Discharge Detection

Product Folder Links: bq29700

BAT

DOUT

COUT

V–

VOVP

OVP–Hys

tOCDD

UVP

BAT

VSS

BAT

VSS

PACK–

BAT

VSS

OCD

Normal Discharge Overcurrent Normal Normal

tSCCD

Load

Connected

VSCC

Load Short-

Circuit

Discharge Overcurrent

Load

Disconnected

VUVP+Hys

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Timing Charts (continued)

Figure 19. Discharge Overcurrent Detection

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9.2 Test Circuits

The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than the

threshold voltage of the external logic level FETs and regarded as ON state. Conversely, “L” is less than the turn

ON threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the

DOUT pin is with respect to VSS.

1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):

The overcharge detection voltage (VOVP) is measured between the BAT and VSS pins, respectively. Once V1

is increased, the over-detection is triggered, and the delay timer expires, COUT transitions from a high to low

state and then reduces the V1 voltage to check for the overcharge hysteresis parameter (VOVP-Hys). This delta

voltage between overcharge detection voltages (VOVP) and the overcharge release occurs when the CHG

FET drive output goes from low to high.

2. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):

Over-discharge detection (VUVP) is defined as the voltage between BAT and VSS at which the DSG drive

output goes from high to low by reducing the V1 voltage. V1 is set to 3.5 V and gradually reduced while V2 is

set to 0 V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the

DOUT drive output transition from low to high when V1 voltage is gradually increased from a VUVP condition.

The overcharge hysteresis voltage is defined as the delta voltage between VUVP and the instance at which

the DOUT output drive goes from low to high.

3. Discharge overcurrent detection voltage (Test Circuit 2):

The discharge overcurrent detection voltage (VOCD) is measured between V– and VSS pins and triggered

when the V2 voltage is increased above VOCD threshold with respect to VSS. This delta voltage once

satisfied will trigger an internal timer tOCDD before the DOUT output drive transitions from high to low.

4. Load short circuit detection voltage (Test Circuit 2):

Load short-circuit detection voltage (VSCC) is measured between V– and VSS pins and triggered when the V2

voltage is increased above VSCC threshold with respect to VSS within 10 µs. This delta voltage, once

satisfied, triggers an internal timer tSCCD before the DOUT output drive transitions from high to low.

5. Charge overcurrent detection voltage (Test Circuit 2):

The charge overcurrent detection voltage (VOCC) is measured between VSS and V– pins and triggered when

the V2 voltage is increased above VOCC threshold with respect to V–. This delta voltage, once satisfied, l

triggers an internal timer tOCCD before the COUT output drive transitions from high to low.

6. Operating current consumption (Test Circuit 2):

The operating current consumption IBNORMAL is the current measured going into the BAT pin under the

following conditions: V1 = 3.9 V and V2 = 0 V.

7. Power down current consumption (Test Circuit 2):

The operating current consumption IPower_down is the current measured going into the BAT pin under the

following conditions: V1 = 1.5 V and V2 = 1.5 V.

8. Resistance between V– and BAT pin (Test Circuit 3):

Measure the resistance (RV_D) between V– and BAT pins by setting the following conditions: V1 = 1.8 V and

V2 = 0 V.

9. Current sink between V– and VSS (Test Circuit 3):

Measure the current sink IV–S between V– and VSS pins by setting the following condition: V1 = 4 V.

10. COUT current source when activated High (Test Circuit 4):

Measure ICOUT current source on the COUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V and

V3 = 3.4 V.

11. COUT current sink when activated Low (Test Circuit 4):

Measure ICOUT current sink on COUT pin by setting the following conditions: V1 = 4.5 V, V2 = 0 V and V3 =

0.5 V.

Product Folder Links: bq29700

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

www.ti.com

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

Test Circuits (continued)

12. DOUT current source when activated High (Test Circuit 4):

Measure IDOUT current source on DOUT pin by setting the following conditions: V1 = 3.9 V, V2 = 0 V and V3

= 3.4 V.

13. DOUT current sink when activated Low (Test Circuit 4):

Measure IDOUT current sink on DOUT pin by setting the following conditions: V1 = 2.0 V, V2 = 0 V and V3 =

0.4 V.

14. Overcharge detection delay (Test Circuit 5):

The overcharge detection delay time tOVPD is the time delay before the COUT drive output transitions from

high to low once the voltage on V1 exceeds the VOVP threshold. Set V2 = 0 V and then increase V1 until BAT

input exceeds the VOVP threshold and to check the time for when COUT goes from high to low.

15. Over-discharge detection delay (Test Circuit 5):

The over-discharge detection delay time tUVPD is the time delay before the DOUT drive output transitions

from high to low once the voltage on V1 decreases to VUVP threshold. Set V2 = 0 V and then decrease V1

until BAT input reduces to the VUVPthreshold and to check the time of when DOUT goes from high to low.

16. Discharge overcurrent detection delay (Test Circuit 5):

The discharge overcurrent detection delay time tOCDD is the time for DOUT drive output to transition from

high to low after the voltage on V2 is increased from 0 V to 0.35 V, with V1 = 3.5 V and V2 starts from 0 V

and increases to trigger threshold.

17. Load short circuit detection delay (Test Circuit 5):

The load short-circuit detection delay time tSCCD is the time for DOUT drive output to transition from high to

low after the voltage on V2 is increased from 0 V to V1 – 1 V, with V1 = 3.5 V and V2 starts from 0 V and

increases to trigger threshold.

18. Charge overcurrent detection delay (Test Circuit 5):

The charge overcurrent detection delay time tOCCD is the time for COUT drive output to transition from high to

low after the voltage on V2 is decreased from 0 V to –0.3 V, with V1 = 3.5 V and V2 starts from 0 V and

decreases to trigger threshold.

19. 0-V battery charge starting charger voltage (Test Circuit 2):

The 0-V charge for start charging voltage V0CHA is defined as the voltage between BAT and V– pins at which

COUT goes high when voltage on V2 is gradually decreased from a condition of V1 = V2 = 0 V.

20. 0-V battery charge inhibition battery voltage (Test Circuit 2):

The 0-V charge inhibit for charger voltage V0INH is defined as the voltage between BAT and VSS pins at

which COUT should go low as V1 is gradually decreased from V1 = 2 V and V2 = –4 V.

Product Folder Links: bq29700

COUT

DOUT

V-

BAT

VSS

3 4

Oscilloscope

COUT

DOUT

V-

BAT

VSS

3 4

IBAT

IV-

COUT

DOUT

V-

BAT

VSS

IDOUT

ICOUT

3 4

COUT

DOUT

V-

BAT

VSS

220Ω

VDOUT

VCOUT

3 4

COUT

DOUT

V-

BAT

VSS

VDOUT

VCOUT

3 4

IBAT

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

www.ti.com

9.3 Test Circuit Diagrams

Figure 20. Test Circuit 1 Figure 21. Test Circuit 2

Figure 22. Test Circuit 3 Figure 23. Test Circuit 4

Figure 24. Test Circuit 5

10 Detailed Description

10.1 Overview

This bq297xy device is a primary protector for a single-cell Li-Ion/Li-Polymer battery pack. The device uses a

minimum number of external components to protect for overcurrent conditions due to high discharge/charge

currents in the application. In addition, it monitors and helps to protect against battery pack overcharging or

depletion of energy in the pack. The bq297xy device is capable of having an input voltage of 8 V from a charging

adapter and can tolerate a voltage of BAT – 25 V across the two input pins. In the condition when a fault is

triggered, there are timer delays before the appropriate action is taken to turn OFF either the CHG or DSG FETs.

There is also a timer delay for the recovery period once the threshold for recovery condition is satisfied. These

parameters are fixed once they are programmed. There is also a feature called zero voltage charging that

enables depleted cells to be charged to a acceptable level before the battery pack can be used for normal

operation. Zero voltage charging is allowed if the charger voltage is above 1.7 V. For Factory Programmable

Options, see Table 1.

Table 1. Factory Programmable Options

PARAMETER FACTORY DEVICE CONFIGURATION

VOVP Overcharge detection voltage 3.85 V to 4.60 V in 50-mV steps

VUVP Over-discharge detection voltage 2.00 V to 2.80 V in 50-mV steps

VOCD Discharging overcurrent detection voltage 90 mV to 200 mV in 5-mV steps

VOCC Charging overcurrent detection voltage –45 mV to –155 mV in 5-mV steps

VSCC Short Circuit detection voltage 300 mV, 400 mV, 500 mV, 600 mV

tOVPD Overcharge detection delay time 0.25s, 1.00s, 1.25s, 4.50 s

tUVPD Over-discharge detection delay time 20 ms, 96 ms, 125 ms, 144 ms

tOCDD Discharging overcurrent detection delay time 8 ms, 16 ms, 20 ms, 48 ms

Product Folder Links: bq29700

Overcharge

Comparator (OVP)

with Hys

Over-Discharge

Comparator (UVP)

with Hys

Oscillator Counter

Over-Discharge

Current Comparator

Overcharge

Current

Comparator

Logic circuit

Delay

Logic circuit

Short Detect

BAT

VSS

DOUT

V–

5COUT

Charger

Detection

Circuit

BAT

IV–S

RV–D

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

www.ti.com

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

Overview (continued)

Table 1. Factory Programmable Options (continued)

PARAMETER FACTORY DEVICE CONFIGURATION

tOCCD Charging overcurrent detection delay time 4 ms, 6 ms, 8 ms, 16 ms

tSCCD Short Circuit detection delay time 250 µs (fixed)

For available released devices, see the Released Device Configurations table.

10.2 Functional Block Diagram

10.3 Feature Description

The bq297xy family of devices measures voltage drops across several input pins for monitoring and detection of

the following faults: OCC, OCD, OVP, and UVP. An internal oscillator initiates a timer to the fixed delays

associated with each parameter once the fault is triggered. Once the timer expires due to a fault condition, the

appropriate FET drive output (COUT or DOUT) is activated to turn OFF the external FET. The same method is

applicable for the recovery feature once the system fault is removed and the recovery parameter is satisfied, then

the recovery timer is initiated. If there are no reoccurrences of this fault during this period, the appropriate gate

drive is activated to turn ON the appropriate external FET.

10.4 Device Functional Modes

10.4.1 Normal Operation

This device monitors the voltage of the battery connected between BAT pin and VSS pin and the differential

voltage between V– pin and VSS pin to control charging and discharging. The system is operating in NORMAL

mode when the battery voltage range is between the over-discharge detection threshold (VUVP) and the

overcharge detection threshold (VOVP), and the V– pin voltage is within the range for charge overcurrent

threshold (VOCC) to over-discharge current threshold (VOCD) when measured with respect to VSS. If these

conditions are satisfied, the device turns ON the drive for COUT and DOUT FET control.

Product Folder Links: bq29700

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

www.ti.com

Device Functional Modes (continued)

CAUTION

When the battery is connected for the first time, the discharging circuit may not be

enabled. In this case, short the V– pin to the VSS pin.

Alternatively, connect the charger between the Pack+ and Pack– terminals in the

system.

10.4.2 Overcharge Status

This mode is detected when the battery voltage measured is higher than the overcharge detection threshold

(VOVP) during charging. If this condition exists for a period greater than the overcharge detection delay (tOVPD) or

longer, the COUT output signal is driven low to turn OFF the charging FET to prevent any further charging of the

battery.

The overcharge condition is released if one of the following conditions occurs:

• If the V– pin is higher than the overcharge detection voltage (VOCC_Min), the device releases the overcharge

status when the battery voltage drops below the overcharge release voltage (VOVP-Hys).

• If the V– pin is higher than or equal to the over-discharge detection voltage (VOCD), the device releases the

overcharge status when the battery voltage drops below the overcharge detection voltage (VOVP).

The discharge is initiated by connecting a load after the overcharge detection. The V– pin rises to a voltage

greater than VSS due to the parasitic diode of the charge FET conducting to support the load. If the V– pin

voltage is higher than or equal to the discharge overcurrent detection threshold (VOCD), the overcurrent condition

status is released only if the battery voltage drops lower than or equal to the overcharge detection voltage (VOVP).

CAUTION

1. If the battery is overcharged to a level greater than overcharge detection (VOVP) and the

battery voltage does not drop below the overcharge detection voltage (VOVP) with a heavy

load connected, the discharge overcurrent and load short-circuit detection features do not

function until the battery voltage drops below the overcharge detection voltage (VOVP). The

internal impedance of a battery is in the order of tens of mΩ, so application of a heavy load

on the output should allow the battery voltage to drop immediately, enabling discharge

overcurrent detection and load short-circuit detection features after an overcharge release

delay.

2. When a charger is connected after an overcharge detection, the overcharge status does not

release even if the battery voltage drops below the overcharge release threshold. The

overcharge status is released when the V– pin voltage exceeds the overcurrent detection

voltage (VOCD) by removing the charger.

10.4.3 Over-Discharge Status

If the battery voltage drops below the over-discharge detection voltage (VUVP) for a time greater than (tUVPD) the

discharge control output, DOUT is switched to a low state and the discharge FET is turned OFF to prevent

further discharging of the battery. This is referred to as an over-discharge detection status. In this condition, the

V– pin is internally pulled up to BAT by the resistor RV–D. When this occurs, the voltage difference between V–

and BAT pins is 1.3 V or lower, and the current consumption of the device is reduced to power-down level

ISTANDBY. The current sink IV–S is not active in power-down state or over-discharge state. The power-down state is

released when a charger is connected and the voltage delta between V– and BAT pins is greater than 1.3 V.

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is lower than

–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the

discharge FET once the battery voltage exceeds over-discharge detection voltage (VUVP).

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is higher than

–0.7 V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the

discharge FET once the battery voltage exceeds over-discharge detection release hysteresis voltage (VUVP +Hys).

Product Folder Links: bq29700

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

www.ti.com

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

Device Functional Modes (continued)

10.4.4 Discharge Overcurrent Status (Discharge Overcurrent, Load Short-Circuit)

When a battery is in normal operation and the V– pin is equal to or higher than the discharge overcurrent

threshold for a time greater than the discharge overcurrent detection delay, the DOUT pin is pulled low to turn

OFF the discharge FET and prevent further discharge of the battery. This is known as the discharge overcurrent

status. In the discharge overcurrent status, the V– and VSS pins are connected by a constant current sink IV–S.

When this occurs and a load is connected, the V– pin is at BAT potential. If the load is disconnected, the V– pin

goes to VSS (BAT/2) potential.

This device detects the status when the impedance between Pack+ and Pack– (see Figure 26) increases and is

equal to the impedance that enables the voltage at the V– pin to return to BAT – 1 V or lower. The discharge

overcurrent status is restored to the normal status.

Alternatively, by connecting the charger to the system, the device returns to normal status from discharge

overcurrent detection status, because the voltage at the V– pin drops to BAT – 1 V or lower.

The resistance RV–D between V– and BAT is not connected in the discharge overcurrent detection status.

10.4.5 Charge Overcurrent Status

When a battery is in normal operation status and the voltage at V– pin is lower than the charge overcurrent

detection due to high charge current for a time greater than charge overcurrent detection delay, the COUT pin is

pulled low to turn OFF the charge FET and prevent further charging to continue. This is known as charge

overcurrent status.

The device is restored to normal status from charge overcurrent status when the voltage at the V– pin returns to

charge overcurrent detection voltage or higher by removing the charger from the system.

The charge overcurrent detection feature does not work in the over-discharge status.

The resistance RV–D between V– and BAT and the current sink IV–S is not connected in the charge overcurrent

status.

10.4.6 0-V Charging Function (Available)

This feature enables recharging a connected battery that has very low voltage due to self-discharge. When the 0-

V battery charge starting charger voltage V0CHG or higher voltage is applied to Pack+ and Pack– connections by

the charger, the COUT pin gate drive is fixed by the BAT pin voltage.

Once the voltage between the gate and the source of the charging FET becomes equal to or greater than the

turn ON voltage due to the charger voltage, the charging FET is ON and the battery is charged with current flow

through the charging FET and the internal parasitic diode of the discharging FET. Once the battery voltage is

equal to or higher than the over-discharge release voltage, the device enters normal status.

CAUTION

1. Some battery providers do not recommend charging a depleted (self-discharged) battery.

Consult the battery supplier to determine whether to have the 0-V battery charger function.

2. The 0-V battery charge feature has a higher priority than the charge overcurrent detection

function. In this case, the 0-V charging will be allowed and the battery charges forcibly,

which results in charge overcurrent detection being disabled if the battery voltage is lower

than the over-discharge detection voltage.

10.4.7 0-V Charging Function (Unavailable)

This feature inhibits recharging a battery that has an internal short circuit of a 0-V battery. If the battery voltage is

below the charge inhibit voltage V0INH or lower, the charge FET control gate is fixed to the Pack– voltage to

inhibit charging. When battery is equal to V0INH or higher, charging can be performed.

Product Folder Links: bq29700

Time

DOUT

V–

BAT

VSS

VSCC

OCD

0≤tD≤ tSCCD

tD˂tOCDD

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

www.ti.com

Device Functional Modes (continued)

CAUTION

Some battery providers do not recommend charging a depleted (self-discharged)

battery. Consult the battery supplier to determine whether to enable or inhibit the 0-V

battery charger function.

10.4.8 Delay Circuit

The detection delay timers are based from an internal clock with a frequency of 10 kHz.

Figure 25. Delay Circuit

If the over-discharge current is detected, but remains below the over-discharge short circuit detection threshold,

the over-discharge detection conditions must be valid for a time greater than or equal to over-discharge current

delay tOCCD time before the DOUT goes low to turn OFF the discharge FET. However, during any time the

discharge overcurrent detection exceeds the short circuit detection threshold for a time greater than or equal to

load circuit detection delay tSCCD, the DOUT pin goes low in a faster delay for protection.

Product Folder Links: bq29700

DOUT

COUT

V–

BAT

VSS

PACK +

PACK–

CELLN

CELLP

S S

0.1 µF

2.2k

DSGCHG

330

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

www.ti.com

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

11 Applications and Implementation

11.1 Application Information

The bq297xy devices are a family of primary protectors used for protection of the battery pack in the application.

The application drives two low-side NMOS FETs that are controlled to provide energy to the system loads or

interrupt the power in the event of a fault condition.

11.2 Typical Application

NOTE: The 5-M resistor for an external gate-source is optional.

Figure 26. Typical Application Schematic, bq297xy

11.2.1 Design Requirements

DESIGN PARAMETER EXAMPLE VALUE at TA= 25°C

Input voltage range 4.5 V to 7 V

Maximum operating discharge current 7 A

Maximum Charge Current for battery pack 4.5 A

Overvoltage Protection (OVP) 4.275 V

Overvoltage detection delay timer 1.2 s

Overvoltage Protection (OVP) release voltage 4.175 V

Undervoltage Protection (UVP) 2.8 V

Undervoltage detection delay timer 150 ms

Undervoltage Protection (UVP) release voltage 3.1 V

Charge Overcurrent detection (OCC) voltage –70 mV

Charge Overcurrent Detection (OCC) delay timer 9 ms

Discharge Overcurrent Detection (OCD) voltage 100 mV

Discharge Overcurrent Detection (OCD) delay timer 18 ms

Load Short Circuit Detection SCC) voltage, BAT to –V ≤threshold 500 mV

Load Short Circuit Detection (SCC) delay timer 250 µs

Load Short Circuit release voltage, BAT to –V ≥Threshold 1 V

Product Folder Links: bq29700

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

www.ti.com

11.2.2 Detailed Design Procedure

NOTE

The external FET selection is important to ensure the battery pack protection is sufficient

and complies to the requirements of the system.

• FET Selection: Because the maximum desired discharge current is 7 A, ensure that the Discharge

Overcurrent circuit does not trigger until the discharge current is above this value.

• The total resistance tolerated across the two external FETs (CHG + DSG) should be 100 mV/7 A = 14.3 mΩ.

• Based on the information of the total ON resistance of the two switches, determine what would be the Charge

Overcurrent Detection threshold, 14.3 mΩ× 4.5 A = 65 mV. Selecting a device with a 70-mV trigger threshold

for Charge Overcurrent trigger is acceptable.

• The total Rds ON should factor in any worst-case parameter based on the FET ON resistance, de-rating due

to temperature effects and minimum required operation, and the associated gate drive (Vgs). Therefore, the

FET choice should meet the following criteria:

Vdss = 25 V

Each FET Rds ON = 7.5 mΩat Tj = 25°C and Vgs = 3.5 V

• Imax > 50 A to allow for short Circuit Current condition for 350 µs (max delay timer). The only limiting factor

during this condition is Pack Voltage/(Cell Resistance + (2 × FET_RdsON) + Trace Resistance).

• Use the CSD16406Q3 FET for the application.

• An RC filter is required on the BAT for noise, and enables the device to operate during sharp negative

transients. The 330-Ωresistor also limits the current during a reverse connection on the system.

• It is recommended to place a high impedance 5-MΩacross the gate source of each external FET to deplete

any charge on the gate-source capacitance.

Product Folder Links: bq29700

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

www.ti.com

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

11.2.3 Application Performance Plots

Orange Line (Channel 1) = Power Up Ramp on BAT Pin Orange Line (Channel 1) = Power Down Ramp on BAT Pin

Turquoise Line (Channel 2) = DOUT Gate Drive Output Turquoise Line (Channel 2) = DOUT Date Drive Output

DOUT goes from low to high when UVP Recovery = UVP Set DOUT goes from high to low when UVP threshold = UVP set

Threshold +100 mV Threshold + set delay time

Figure 27. UVP Recovery Figure 28. UVP Set Condition

Orange Line (Channel 1) = Power Up Ramp on BAT pin Orange Line (Channel 1) = Power Up Ramp on BAT Pin

Turquoise Line (Channel 2) = DOUT Gate Drive Output Turquoise Line (Channel 2) = COUT Gate Drive Output

Figure 29. Initial Power Up, DOUT Figure 30. Initial Power Up, COUT

Orange Line (Channel 1) = Decrease Voltage on BAT Pin

Orange Line (Channel 1) = Power Up Ramp on BAT Pin Turquoise Line (Channel 2) = COUT Gate Drive Output

Turquoise Line (Channel 2) = COUT Gate Drive Output COUT goes from low to high when OVP Recovery = OVP Set

COUT goes from high to low when OVP threshold = OVP set Threshold –100 mV

Threshold + set delay time

Figure 32. OVP Recovery Condition

Figure 31. OVP Set Condition

Product Folder Links: bq29700

COUT

DOUT

V–

BAT

VSS

4D5

CSD16406Q3 CSD16406Q3

Power Trace

Power Trace Line

PACK+

PACK–

Via connects between two layers

Power Trace Line

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

www.ti.com

12 Power Supply Recommendations

The recommended power supply for this device is a maximum 8-V operation on the BAT input pin.

13 Layout

13.1 Layout Guidelines

The following are the recommended layout guidelines:

1. Ensure the external power FETs are adequately compensated for heat dissipation with sufficient thermal

heat spreader based on worst-case power delivery.

2. The connection between the two external power FETs should be very close to ensure there is not an

additional drop for fault sensing.

3. The input RC filter on the BAT pin should be close to the terminal of the IC.

13.2 Layout Example

Figure 33. bq297xy Board Layout

Product Folder Links: bq29700

bq29700, bq29701, bq29702

bq29703, bq29704, bq29705

bq29706, bq29707

www.ti.com

SLUSBU9A –MARCH 2014–REVISED JUNE 2014

14 Device and Documentation Support

14.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &

PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

bq29700 Click here Click here Click here Click here Click here

bq29701 Click here Click here Click here Click here Click here

bq29702 Click here Click here Click here Click here Click here

bq29703 Click here Click here Click here Click here Click here

bq29704 Click here Click here Click here Click here Click here

bq29705 Click here Click here Click here Click here Click here

bq29706 Click here Click here Click here Click here Click here

bq29707 Click here Click here Click here Click here Click here

14.2 Trademarks

All trademarks are the property of their respective owners.

14.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

14.4 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: bq29700

PACKAGE OPTION ADDENDUM

www.ti.com 23-Jul-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

BQ29700DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FA

BQ29700DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FA

BQ29701DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FY

BQ29701DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FY

BQ29702DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FZ

BQ29702DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FZ

BQ29703DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F1

BQ29703DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F1

BQ29704DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F2

BQ29704DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F2

BQ29705DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F3

BQ29705DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F3

BQ29706DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F4

BQ29706DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F4

BQ29707DSER ACTIVE WSON DSE 6 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F5

BQ29707DSET ACTIVE WSON DSE 6 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 F5

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

PACKAGE OPTION ADDENDUM

www.ti.com 23-Jul-2015

Addendum-Page 2

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

BQ29700DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29700DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29701DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29701DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29702DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29702DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29703DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29703DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29704DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29704DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29705DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29705DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29706DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29706DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29707DSER WSON DSE 6 3000 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

BQ29707DSET WSON DSE 6 250 180.0 8.4 1.75 1.75 1.0 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Jul-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ29700DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29700DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29701DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29701DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29702DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29702DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29703DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29703DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29704DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29704DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29705DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29705DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29706DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29706DSET WSON DSE 6 250 210.0 185.0 35.0

BQ29707DSER WSON DSE 6 3000 210.0 185.0 35.0

BQ29707DSET WSON DSE 6 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Jul-2015

Pack Materials-Page 2

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Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

BQ29700DSET BQ29700DSER BQ29705DSET BQ29707DSER BQ29701DSER BQ29705DSER BQ29704DSER

BQ29703DSER BQ29707DSET BQ29703DSET BQ29706DSET BQ29704DSET BQ29702DSET BQ29701DSET

BQ29706DSER BQ29702DSER