IRDC3831W
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USER GUIDE FOR IR3831W EVALUATION BOARD
DESCRIPTION
The IR3831W is a synchronous buck
converter, providing a compact, high
performance and flexible solution in a small
5mmx6mm Power QFN package.
Key features offered by the IR3831W
include programmable soft-start ramp,
Power Good,thermal protection,
programmable switching frequency, tracking
input, enable input, input under-voltage
lockout for proper start-up, and pre-bias
start-up.
An output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
rectifier MOSFET for optimum cost and
performance.
This user guide contains the schematic and bill
of materials for the IR3831W evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3831W is available in the
IR3831W data sheet.
BOARD FEATURES
•Vin = +12V (13.2V Max)
•V
cc= +5V (5.5V Max)
•Vout = +0.75V @ 0- ±8A
•F
s = 400kHz
•L = 0.6uH
•Cin= 3x10uF (ceramic 1206) + 330uF (electrolytic)
•Cout= 8x22uF (ceramic 0805)
SupIRBuckTM
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A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum ±8A load should be
connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the
board are listed in Table I.
IR3831W has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate
supplies should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it
would be connected to Vcc+ and Vcc-.
If single 12V application is required, connect R7 ( zero Ohm resistor) which enables the on board bias
regulator (see schematic). In this case there is no need of external Vcc supply.
The output tracks VDDQ input. The value of R14 and R28 can be selected to provide the desired ratio
between the output voltage and the tracking input. For proper operation of IR3831W, the voltage at Vp pin
should not exceed Vcc.
CONNECTIONS and OPERATING INSTRUCTIONS
LAYOUT
The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3831W SupIRBuck and all of the
passive components are mounted on the top side of the board.
Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located
close to IR3831W. The feedback resistors are connected to the output voltage at the point of regulation
and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to
minimize the length of the on-board power ground current path.
Table I. Connections
Tracking InputVDDQ
Vout (+0.75V)VOUT+
Ground for Vcc inputVcc-
Vcc inputVcc+
EnableEnable
Power Good SignalPGood
Ground of Vout
VOUT-
Ground of Vin
VIN-
Vin (+12V)VIN+
Signal NameConnection
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Connection Diagram
Fig. 1: Connection diagram of IR383xW evaluation boards
Vin
PGood
Vo
GND
GND
Enable
SS
VDDQ
AGND
Vcc GND
Vp
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Fig. 2: Board layout, top overlay
Fig. 3: Board layout, bottom overlay
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Fig. 4: Board layout, mid-layer I
Fig. 5: Board layout, mid-layer II
Single point
connection
between AGND
and PGND.
AGND
Plane PGND
Plane
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Fig. 6: Schematic of the IR3831W evaluation board
Single point of connection between Power
Ground and Signal ( “analog” ) Ground
Vout-
1
VDDQ
1
+
C35
N/S
+
C36
N/S
Vin
C14
0.1uF
Vcc-
1
C10
22000pF
PGND
1
Vin
Vp
1
L1
600nH
R7
N/S
R28
1.50K
C24
0.1uF
C23
10nF
C26
22000pF
C13
0.1uF
R19
7.50k
R14
1.50K
SS
1
Vout
Vcc+
1
C2
10uF
C5
N/S
R9
35.7K
R1
1.48K
R10
0
C3
10uF
R3
N/S
Vcc
D1
MM3Z5V6B
21
R4
210
Optional +5V supply for Vcc
R2
6.65K
R5
3.30K
C4
10uF
Q1
MMBT3904-TP
C15
22uF
C34
0.1uF
R6
20
C16
22uF
C25
N/S
C17
22uF
R12
3.24k
C18
22uF
C19
22uF
C20
22uF
U1
IR3831W
Enable 14
Boot 13
AGnd3
15
Rt
5SW 11
Vcc
9
COMP
3
OCset
7PGnd 10
SS
6
Vp
1
FB
2
AGnd1
4
PGood
8
Vin 12
A
1
Vp
C32
0.1uF
B
1
R18
49.9K
+
C1
330uF
R*
0
C21
22uF
VCC
C8
2200pF
C7
0.1uF
VCC
Agnd
1
C22
22uF
Vin+
1
C27
N/S
Vin-
1
C28
N/S
Vout+
1
Vout-
1
R17
10.0K
PGood
1
C11
560pF
C6
N/S
Enable
1
Vin+
1
Vin-
1
Vout+
1
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Bill of Materials
Item Quantity Part Reference Value Description Manufacturer Part Number
1 1 C1 330uF SMD Elecrolytic, Fsize, 25V, 20% Panasonic EEV-FK1E331P
2 3 C2 C3 C4 10uF 1206, 16V, X5R, 20% TDK C3216X5R1E106M
3 1 C10 0.022uF 0603, 16V, X7R, 10% Panasonic- ECG ECJ-1VB1C223K
4 1 C34 10uF 0805, 10V, X5R, 20% Panasonic - ECG ECJ-GVB1A106M
5 5 C7 C13 C14 C24 C32 0.1uF 0603, 25V, X7R, 10% Panasonic - ECG ECJ-1VB1E104K
6 1 C8 2200pF 0603, 50V, NP0, 5% Murata GRM1885C1H222JA01D
7 1 C11 560pF 0603, 50V, NP0, 5% Panasonic- ECG ECJ-1VC1H561J
88
C15 C16 C17 C18 C19 C20
C21 C22 22uF 0805, 6.3V, X5R, 20% Panasonic- ECG ECJ-2FB0J226M
9 1 C25 10000pF 0603, 50V, X7R, 10% Panasonic - ECG ECJ-1VB1H103K
10 1 C26 22000pF 0603, 50V, X7R, 10% Panasonic - ECG ECJ-1VB1H223K
11 1 D1 MM3Z5V6B Zener, 5.6V Fairchild MM3Z5V6B
12 1 L1 0.6uH 11.5x10x4mm, 20%, 1.7mOhm Delta MPL104-0R6IR
13 1 Q1 MMBT3904/SOT NPN, 40V, 200mA, SOT-23 Fairchild MMBT3904/SOT
14 1 R5 3.3k Thick Film , 0603,1/10W,1% Rohm MCR03EZPFX3301
15 1 R18 49.9k Thick Film , 0603,1/10W,1% Rohm MCR03EZPFX4992
16 1 R4 210 Thick Film , 0603,1/10W,1% Panas onic - ECG ERJ-3EKF2100V
17 1 R6 20 Thick Film , 0603,1/10 W,1% Vishey/Dale CRCW060320R 0FKEA
18 1 R9 35.7k Thick Film , 0603,1/10W,1% R ohm MCR03EZPFX3572
19 1 R12 3.24k Thick Film, 0603,1/10 W,1% Rohm MCR03EZPFX3241
20 1 R17 10.0k Thick Film , 0603,1/10W,1% Rohm MCR03EZPFX1002
21 1 R19 7.5k Thick Film , 0603,1/10W,1% R ohm MCR03EZPFX7501
22 1 R10 0 Thick Film , 0603,1/10W,1% Yageo RC0603FR-100RL
23 1 R1 1.48k Thick Film , 0603,1/10W,1% R ohm MCR03EZPFX1481
24 1 R2 6.65k Thick Film , 0603,1/10W,1% R ohm MCR03EZPFX6651
25 2 R14, R28 1.50k Thick Film , 0603,1/10W,1% Rohm MCR03EZPFX1501
26 1 U1 IR3831W 8A SupIRBuck, 6mmx5mm International Rectifier IR3831WMPbF
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TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vcc=5V, Vo=0.75V, Io=0- ±8A, Room Temperature, No Air Flow
Fig. 11: Output Voltage Ripple, 8A,
sourcing current, Ch2: Vout
Fig. 9: Inductor node at 8A, sourcing
current, Ch3:SW, Ch4:Iout
Fig. 12: Short (Hiccup) Recovery
Ch2:Vout, Ch3:VSS , Ch4:PGood
Fig. 7: Start up at 8A, sourcing current
Ch1:PGood, Ch2:Vout, Ch3:SS, Ch4:VDDQ
Fig. 10: Inductor node at -3A, sinking
current, Ch3:SW, Ch4:Iout
Fig. 8: Start up with Prebias, 0A Load
Ch1:PGood, Ch2:Vout, Ch3:SS, Ch4:VDDQ
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TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=0.75V, Room Temperature, No Air Flow
Fig. 15: Transient Response, 1A/us
-0.5A to +0.5A load , Ch1:Vout, Ch3:Io
Fig. 13: Tracking 8A, sourcing current,
Ch2:Vout, Ch3:VDDQ, Ch4:PGood Fig. 14: Tracking -3A load, sinking current,
Ch2:Vout, Ch2: IL, Ch3:VDDQ, Ch4:PGood
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TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=0.75V, Io=+8A, Room Temperature, No Air Flow
Fig.16: Bode Plot at 8A load (sourcing current) shows a bandwidth of 59kHz and phase margin of 59 degrees
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Fig.18: Power loss versus load current
Fig.17: Efficiency versus load current
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vo=0.75V, Io=0- +8A, Room Temperature, No Air Flow
83
84
85
86
87
88
89
10 20 30 40 50 60 70 80 90 100
Load Percentage (%)
Efficiency (%)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
10 20 30 40 50 60 70 80 90 100
Load Percentage(%)
Power Loss (W)
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THERMAL IMAGES
Vin=12V, Vo=0.75V, Io=+8A, Room Temperature, No Air Flow
Fig.19: Thermal Image at 8A load
Test Point 1: IR3831W, Test Point 2: Inductor
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PCB Metal and Components Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum
lead to lead spacing should be ≥0.2mm to minimize shorting.
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large and inspectable toe fillet.
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to
maximum part pad length and width. However, the minimum metal to metal spacing should be no less
than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz.
Copper.
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Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD
pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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Stencil Design
• The Stencil apertures for the lead lands should be approximately 80% of the area of the
lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead
shorts. If too much solder is deposit ed on the center pad the part will fl oat and the lead
lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the
solder resist opening minus an annular 0.2mm pull back t o decrease the incidence of
shorting the center land to the lead lands when the part is pushed into the solder paste.
IRDC3831W
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Consumer market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 11/07
BOTTOM VIEW
