DATA SHEET
November 1995
Edition 1.5
Copyright 1994 by FUJITSU LIMITED
3V, 0.50 MICRON HIGH PERFORMANCE/LOW POWER
CMOS GATE ARRAYS
CG51/CE51 SERIES
DESCRIPTION
The Fujitsu CG51/CE51 is a series of ultra high performance
CMOS gate arrays. The CG51 is a high density Sea-of-Gates
array for applications requiring high levels of integration or low
power . The CE51 is a high performance embedded gate array
family offering full support of diffused high speed RAMS, ROMS
and embedded megafunctions. The CE51 series offers density
and performance approaching that achievable with standard
cell solutions with the time-to-market advantage of a gate array.
T rue 3V products, the CG51/CE51 feature very low power (1.2
microwatt/Mhz) and both 3.3V and 5.0V compatible I/Os. These
advanced product families are targeted at users who are
seeking very high performance or very high levels of
integration. Potential end-user applications include computers,
supercomputers, workstations, graphic terminals, telecom
networking, and signal processing.
FEATURES
0.5 Micron Drawn Channel Length
Triple layer metal
3.3V + 0.3V supply voltage
Chanelless, Sea-of-gates Architecture
Internal gate delay of 210ps, F/O = 2, L = 1mm
Low power consumption: 1.2 microwatt/gate/Mhz
Maximum toggle frequency: 600Mhz
High speed I/Os: PCML (PECL), LVTC
Supports 3.3V and 5.0V I/O
RAM compiler supports Single/Dual/Triple port RAM
Supports JTAG boundary scan, full and partial scan
Phase Locked Loop for interchip clock skew control
Clock net for optimized on-chip clock skew control
Advanced packaging options include QFP, PGA, BGA,
and MCM
High drive capability: 2, 4, 8, 12, or 24mA
Supports all major third party EDA tools including:
Cadence, Mentor, Synopsys
Fujitsu Microelectronics, Inc.’s CE51654
647,000 Available Gate .5 Micron Embedded
Array, Containing 28 Embedded Macro Cells
PRODUCT SUMMAR Y
Device
Name Available
Gates Number of
Pads Metal
Wiring
CG51754 753,768 496 3LM
CG51654 647,948 456 3LM
CG51484 477,632 400 3LM
CG51364 363,084 352 3LM
CG51284 277,380 304 3LM
CG51214 214,760 272 3LM
CG51164 160,140 240 3LM
CG51114 113,520 208 3LM
CG51343 34,272 120 3LM
CG51/CE51 SERIES
2
DC CHARACTERISTICS Measuring conditions: VDD = 3.3V + 0.3V,VSS = 0V, Tj = –0 to 100°C
Parameter
Symbol
Test Conditions
Requirements
Unit
Parameter Symbol Test Conditions Min. Typ. Max. Unit
CG51343 to
CG51214 –1.0 – 1.0
Supply current2IDDS Standby mode1CG51284 to
CG51484 –2.0 – 2.0 mA
CG51654 to
CG51754 –3.0 – 3.0
High level
CMOS
ll
Normal cell VDD 0.7 – VDD
High-level
in
p
ut volta
g
e3VIH
CMOS
level Schmitt trigger cell VDD 0.8 – VDD V
i
npu
t
vo
lt
age
3
VIH
TTL level Normal cell 2.2 – VDD
V
Low level
CMOS
ll
Normal cell VSS – VDD 0.2
Low-level
in
p
ut volta
g
e3VIL
CMOS
level Schmitt trigger cell VSS – VDD 0.2 V
i
npu
t
vo
lt
age
3
VIL
TTL level Normal cell VSS –0.8
V
High-level output
voltage VoH IOH = –2, –4, –8, –12, –18 VDD –0.4 – VDD V
Low-level output
voltage VOL IOL = 2, 4, 8, 12, 18 VSS 00.4 V
Input leakage current
(T i t t i i t)4
ILI
VI=0VtoV
DD
–10 – 10
µA
Input
leakage
current
(T ri-state pin input)4ILZ VI = 0V to VDD –10 – 10 µA
Input pull–up/
pull–down resistor5RPPull-up VI = VDDI
Pull-down VI = 0V 20 50 140 kΩ
Type Condition VO = VDD VO = 0V
Low power IOL = 2mA –20 +20
Output Short-circuit
t6
IO
Normal IOL = 4mA –40 +40
mA
Output
Short circuit
current6IOOutput buffer Power IOL = 8mA –80 +80 mA
Output buffer
High power IOL = 12mA –120 +120
Very high power IOL = 24mA –180 +180
NOTES:
1. When VIH = VDD and VIL = VSS, memory is in the standby mode.
2. If an input buffer with pull-up/pull-down resistor is used, the supply current may not be assured depending on the circuit configuration.
3. 5V interface is only for CMOS level.
4. If an input buffer with pull-up/pull-down resistor is used, the input leakage current may exceed the above value.
5. Either a buffer without a resistor or with a pull–up/pull–down resistor can be selected from the input and bidirectional buf fers.
6. Maximum supply current at the short–circuit of output and VDD or VSS.
CG51/CE51 SERIES
3
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Requirements Unit
Supply voltage
VDDE (External) VSS* –0.5 to 6.0
V
Supply voltage VDDI (Internal) VSS* –0.5 to 4.0 V
Input voltage VIVSS* –0.5 to VDD +0.5 V
Output voltage VOVSS* –0.5 to VDD +0.5 V
Storage ambient temperature
TST
Plastic –55 to +125 °
C
Storage ambient temperature TST Ceramic –65 to +150 °C
Supply pin current
ID
For one VDD pin 90
mA
Supply pin current IDFor one VSS pin 90 mA
Low power-type output buffer IOL = 2 mA +14
Normal-type output buffer IOL = 4mA +14
Output current
IO
Power-type output buffer IOL = 8mA +14
mA
O
utput current
I
OHigh-power type output buffer IOL = 12mA +21 m
A
Very high-power type of output buffer
IOL = 24mA +58
*V
SS = 0V
RECOMMENDED OPERATING CONDITIONS
Parameter
Requirements
Unit
Parameter Symbol Min. Typ. Max. Unit
Supply voltage
VDDE 3.0 3.3 3.6
V
Supply voltage VDDI 3.0 3.3 4.6 V
High-level input voltage
CMOS level
VDD 0.7 – VDDI
V
High-level input voltage TTL level VIH 2.2 – VDDI V
Low-level input voltage
CMOS level
VSS*– VDDI 0.2
V
Low-level input voltage TTL level VIL VSS*–0.8 V
Junction temperature Tj0 – 100 °C
*V
SS = 0V
CG51/CE51 SERIES
4
THIRD PARTY EDA TOOL SUPPORTED
Fujitsu supports a third party environment allowing an ASIC
designer the widest possible range of design options. Both
the CG51 gate array and CE51 embedded array product
families are fully supported by Fujitsu’s ASIC design kits,
running on leading workstations and provides a seamless
link from leading third party ASIC design flows to Fujitsu’s
ASIC back end environment. These kits provide an easy
environment for design entry, design rule checking. They also
provide a complete pre- and post-layout timing back
annotating capabilities. The following leading third party tools
are supported.
Cadence: Verilog-XL
Mentor: Design Architect 8.2, Autologic I, QuickSim II
Motive: Motive 4.2 (Static Timing Analyzer)
Sunrise Systems: ATPG 2.1
Synopsys: Design Analyzer 3.2a, VSS
CG51/CE51 SERIES
5
PACKAGE OPTIONS
In addition to offering plastic and ceramic versions of industry
standard packages such as PQFPs and PGAs, Fujitsu also
offers an impressive array of advanced packaging
technology. Our long experience with high speed logic and
thermal management has led us to develop some of the most
advanced packaging available anywhere. From cost
effective, single chip packages to sophisticated multichip
modules, Fujitsu has a packaging option to suit your
requirements. Whether you need a 208 PQFP, the newest in
high I/O count surface mounted Ball Grid Array (BGA)
packages or full custom packaging we can deliver the
optimal solution.
Packaging Options
343 114 164 214 284 364 484 654 754
Quad Flat Package (1.0, 0.8, 0.65 mm pin pitch)
100 P
120 P C
160 P,C P,C P,C P,C P,C P,C P,C
Shrink Quad Flat Package (0.5 mm pin pitch)
80 P
100 P
120 P
144 PPPP
176 P,C P,C P,C P,C P,C
208 P,C P,C P,C P,C P,C P,C P,C
240 P,C P,C P,C P,C P,C P,C
256 C P,C P,C P,C P,C
304 C1 C1 C C C
Fine Pitch Flat Package (0.4 mm pin pitch)
304 CCCC
Pin Grid Array Package
256 CCCCC
299 CCCCC
321 CCCC
361 CCC
401 CCCC
Ball Grid Array (BGA)
256 P P P
352 P P P
416 P1 P1
576 P1
NOTES: 1 : Under Development
C: Ceramic Package
P: Plastic Package
CG51/CE51 SERIES
6
FRONT-END DESIGN FLOW
Logic Design
Rule Check
IDRC
Netlist &
Delay
Generator
fldl_gen
FMI Design Kit
Test Pattern
Editor
ftdl_ed
Test Pattern
Generator
ftdl_gen
Netlist
FLDL
Back
Annotation
PDIL
Test
Pattern
FTDL
Logic Verification
LCADFE
Layout
GlosCAD
Netlist
Timing
Stimulus
Trace
EDIF VHDL
or any other
CAE netlist in
ascii format
Design Specification
Schematic Entry Logic
Synthesis
Simulation
CAE-Software Simulator
Hardware Accelator
CG51/CE51 SERIES
7
CLOCK SKEW CONTROL
To maximize performance in high speed, high density arrays,
a designer must maintain tight clock skew control. In addition
to an available PLL to manage interchip clock skew, Fujitsu’s
clock driven design methodology (CDDM) offers accurate on
chip clock skew control. CDDM offers accurate RC extraction
of clock tree parameters, interactive clock tree
implementation, simplifies trade-of fs between clock tree delay
and clock skew, early verification of potential design hold
time errors and race conditions.
ÍÍ
ÍÍ
Í
Í
Macro
ÍÍ
Í
Í
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
LCD
GCD
Í
Í
FF FF FF
FF
FF
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
ÍÍ
FF
CK
Root
Clock
Driver Global
Clock
Driver Local
Clock
Driver
8FF-Bars
(20FFs/FF-Bar)
LCD-FF
Skew165ps
Up to 160FFs
GCD-LCD
“0” Skew
Up to 10 LCDs
CK
Tree
CK I/O-GCD
“0” Skew
GCD
CK I/O
CG51/CE51 SERIES
8
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of
illustrating typical semiconductor applications. Complete information
sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully checked
and is believed to be reliable. However, Fujitsu assumes no
responsibility for inaccuracies.
The information contained in this document does not convey any license
under the copyrights, patent rights or trademarks claimed and owned by
Fujitsu.
Fujitsu reserves the right to change products or specifications without
notice.
This document contains information on a new product. Specification and
information herein are subject to change without notice.
No part of this publication may be copied or reproduced in any form or by
any means, or transferred to any third party without prior written consent
of Fujitsu.
This device contains circuitry to protect the inputs against damage
due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high impedance circuit.
CG51/CE51 SERIES
9
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Electronic Devices International
Sales and Engineering Support Division
1015, Kamikodanaka Nakahara-ku,
Kawasaki 211, Japan
Tel: (044) 754-3753
FAX: (044) 754-3332
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Logic Products Division
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FAX: 408-432-9044
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FUJITSU LIMITED 1994 ASIC-DS-20084-11/95