ICSVF2510YGLF-T - Integrated Device Technology

Integrated

Circuit

Systems, Inc.

General Description Features

ICSVF2510

0722B—05/06/04

Block Diagram

3.3V Phase-Lock Loop Clock Driver

Pin Configuration

The ICSVF2510 is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology to

align, in both phase and frequency , the CLKIN signal with

the CLKOUT signal. It is specifically designed for use with

synchronous SDRAMs. The ICSVF2510 operates at 3.3V

VCC and drives up to ten clock loads.

One bank of ten outputs provide low-skew, low-jitter

copies of CLKIN. Output signal duty cycles are adjusted

to 50 percent, independent of the duty cycle at CLKIN.

Outputs can be enabled or disabled via control (OE)

inputs. When the OE inputs are high, the outputs align in

phase and frequency with CLKIN; when the OE inputs are

low, the outputs are disab led to the logic lo w state.

The ICSVF2510 does not require external RC filter

components. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost. The

test mode shuts off the PLL and connects the input

directly to the output buffer. This test mode, the ICSVF2510

can be use as low skew fanout clock buffer device. The

ICSVF2510 comes in 24 pin 173mil Thin Shrink Small-

Outline package (TSSOP) package.

•Meets or exceeds PC133 registered DIMM

specification1.1

•Spread Spectrum Clock Compatible

•Distributes one clock input to one bank of ten outputs

•Operating frequency 20MHz to 200MHz

•External feedback input (FBIN) terminal is used to

synchrionize the outputs to the clock input

•No external RC network required

•Operates at 3.3V Vcc

•Plastic 24-pin 173mil TSSOP package

•Industrial temperature version available

FBIN

CLKIN

AVCC

PLL

CLK1

CLK0

FBOUT

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

CLK9

AGND 1 24 CLKIN

VCC 2 23 AVCC

CLK0 3 22 VCC

CLK1 4 21 CLK9

CLK2 5 20 CLK8

GND 6 19 GND

GND 7 18 GND

CLK3 8 17 CLK7

CLK4 9 16 CLK6

VCC 10 15 CLK5

OE 11 14 VCC

FBOUT 12 13 FBIN

24 Pi n TSSOP

4.40 mm. Bod

, 0.65 mm. Pitch

ICSVF2510

0722B—05/06/04

Pin Descriptions

Note:

1. Weak pull-ups on these inputs

Functionality

PIN # PIN NAME TYPE DESCRI PT I ON

1 A GND P WR A nalog Gr ound

2, 10, 14 VCC PWR Power Supply (3.3V)

3 CLK 0 OUT Buffere d c lock o utput.

4 CLK 1 OUT Buffere d c lock o utput.

5 CLK 2 OUT Buffere d c lock o utput.

6, 7, 18, 19 G N D P WR Grou nd

8 CLK 3 OUT Buffere d c lock o utput.

9 CLK 4 OUT Buffere d c lock o utput.

11 OE1IN Output enable (has inter nal pull_up). W hen high, nor m a l op er ation.

When low, c lock outputs are dis able d to a logic low s tate.

12 FBOUT OUT F eedb ac k ou tput

13 FBIN IN Feedback input

15 CLK 5 OUT Buffere d c lock o utput.

16 CLK 6 OUT Buffere d c lock o utput.

17 CLK 7 OUT Buffere d c lock o utput.

20 CLK 8 OUT Buffere d c lock o utput.

21 CLK 9 OUT Buffere d c lock o utput.

22 V CC P W R P owe r S upply ( 3. 3V ) digital sup ply .

23 AVCC IN A nalog power s up ply ( 3.3V). When input is gr ound PLL is off and

bypassed.

24 CLK IN IN Cloc k inp ut

OE AVCC CLK (9:0 ) F B O UT So urce

03.33 0DrivenPLLN

1 3.33 Driven Driven PLL N

00 0DrivenCLKINY

Driven Driven CLKIN Y

Test m ode:

When AVCC is 0, s huts off the PLL

and c onnects the i nput di rec tl y to the out put buf fers

Buffer Mode

INPUTS OUTPUTS PLL

Shutdow n

ICSVF2510

0722B—05/06/04

Absolute Maximum Ratings

Supply Voltage (AVCC). . . . . . . . . . . . . . . . . AVCC < (Vcc + 0.7 V)

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . 4.3 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to Vcc + 0.5 V

Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses abov e those listed under

Absolute Maximum Ratings

ma y cause permanent damage to the de vice. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

f or e xtended periods may aff ect product reliability.

Elect r i cal Char acter i st i cs - O UTPUT

TA = 0 - 70°C; V DD = VDDL = 3.3 V +/-10%; CL = 30 pF; RL = 500 Ohm s (unl es s ot herwise s tated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V OH IOH = -8 mA 2.4 2.9 V

Out put Low V oltage V OL IOL = 8 m A 0. 25 0. 4 V

VOH = 2.4 V 27

VOH = 2.0 V 39

VOL = 0. 8 V 26

VOL = 0. 55 V 19

Ri se T i me 1TrVOL = 0.8 V , V OH = 2. 0 V 0. 5 1. 1 2.1 ns

Fall Time1TfVOH = 2.0 V, VOL = 0. 8 V 0. 5 1. 1 2. 7 ns

Duty Cycle1DtVT = 1.5 V;CL= 30 pF 48 50 52 %

Cycle to Cycle jitter1TCY

- T CY

at 66-100 MHz ; l oaded out put s 75 ps

Absolute Jitter1TJABS 10000 c ycl es ; CL = 30 pF 100 ps

Skew1Tsk VT = 1.5 V (Window) Output to Output 100 ps

P hase error1T

eVT = Vdd/2; CLKI N-FBI N -75 75 ps

Delay Input-Output1DR1 VT = 1.5 V ; PLL_E N = 0 3.3 3.7 ns

1 Guaranteed by desi gn, not 100% test ed i n product i on.

Output H i gh Curre nt

Out put Low Current

IOH

IOL

ICSVF2510

0722B—05/06/04

Elect r i cal Char acter i st i cs - I nput & Supply

TA = 0 - 70°C; S upply V ol t age V DD = 3.3 V +/-10% (unless otherwise st at ed)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I nput High Vol t age V IH 2V

DD + 0.3 V

I nput Low V ol t age V IL VSS - 0.3 0.8 V

I nput High Current I IH VIN = VDD 0.1 100 uA

I nput Low Current I IL VIN = 0 V; 19 50 uA

Operati ng current I DD1CL = 0 pF; FIN @ 66MHz 170 mA

I nput Capac i t ance CIN1Logic Inputs 4 pF

1Guarant eed by desi gn, not 100% tested in producti on.

S ym bol P a ram eter T est Cond i t i ons M in . Max. Uni t

FOP Operati ng freq uency 20 200 M Hz

FCLK Input clock

frequency 25 200 MHz

Input clock

f requency duty

cycle 40 60 %

S tab i li zati on t i m e A fter po wer up 15 µs

Timing requirements over recommended ranges of supply

vol tage and operat i ng fr ee- air tempe r at ur e

Note: Time required for the PLL circuit to obtain phas e loc k of its feedback signal to its reference signal.

I n orde r f or

hase lock to be obtained

a f i xed-f re

uenc

fixed-

hase refe rence si

nal m u st be

resent at CLK.

Unt i l pha s e lo c k i s obta in ed, the s pe c i fi c a t i o ns for pa ram ete rs gi ven i n the swi t ching charact eri st i cs tabl e are not appl i cab l e.

ICSVF2510

0722B—05/06/04

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit for Outputs

Notes:

1. CL includes probe and jig capacitance.

2. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 133 MHz, ZO = 50Ω, Tr ≤ 1.2 ns, Tf≤ 1.2 ns .

3. The outputs are measured one at a time with one transition per measurement.

30pF 500Ω

From Output

UnderTest

Figure 2. V oltage Waveforms

Propagation Delay Times

Figure 3. Phase Error and Skew Calculations

ICSVF2510

0722B—05/06/04

General Layout Precautions:

An ICS2509C is used as an example. It is similar to the

ICSVF2510. The same rules and methods apply.

1) Use copper flooded ground on the top signal layer

under the clock buffer The area under U1 in figure 1

on the right is an example. Every ground pin goes to a

ground via. The vias are not visible in figure 1.

2) Use power vias for power and ground. Vias 20 mil or

larger in diameter have lower high frequency

impedance. Vias for signals may be minimum drill

size.

3) Make all power and ground traces are as wide as the

via pad for lower inductance.

4) VAA for pin 23 has a low pass RC filter to decouple

the digital and analog supplies. C9-12 may be replaced

with a single low ESR (0.8 ohm or less) device with

the same total capacitance. R2 may be replaced with a

ferrite bead. The bead should have a DC resistance of

at least 0.5 ohms. 1 ohm is better. It should have an

impedance of at least 300 ohms at 100MHz. 600 ohms

at 100MHz is better.

5) Notice that ground vias are never shared.

6) All VCC pins have a decoupling capacitor. Power is

always routed from the plane connection via to the

capacitor pad to the VCC pin on the clock buffer.

7) Component R1 is located at the clock source.

8) Component C1, if used, has the effect of adding delay.

9) Component C7 , if used, has the effect of subtracting

delay. Delaying the FBIn clock will cause the output

clocks to be earlier. A more effective method is to use

the propagation time of a trace between FBOut and

FBIn.

Component Values:

C1,C7= As necessary for delay

adjust

C[6:2]=.01uF

C8,C13=0.1uF

C[12:9]=4.7Uf

R1=10 ohm. Locate at driver

R2=10 ohm.

Figure 1.

ICSVF2510

0722B—05/06/04

Ordering Information

ICSVF2510yGLF-T

4.40 mm. Body, 0.65 mm. pitch TSSOP

(173 mil) (0.0256 Inch)

MIN MAX MIN MAX

A -- 1.20 -- .047

A1 0.05 0.15 .002 .006

A2 0.80 1.05 .032 .041

b 0.19 0.30 .007 .012

c 0.09 0.20 .0035 .008

E1 4.30 4.50 .169 .177

L 0.45 0.75 .018 .030

α0° 8° 0° 8°

aaa -- 0.10 -- .004

ARIATIONS

MIN MAX MIN MAX

24 7.70 7.90 .303 .311

10-0035

SYMBOL In M illimeters In Inches

COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS SEE VARIATIONS

6.40 BASIC 0.252 BASIC

0.65 BASIC 0.0256 BASIC

SEE VARIATIONS SEE VARIATIONS

ND mm. D (i nch)

Reference Doc.: JEDEC Publication 95, MO-153

INDEX

AREA

INDEX

AREA

1 2

E1 E

SEATING

PLANE

SEATING

PLANE

-C-

- C -

aaa C

Example:

Designation for tape and reel packaging

Lead Free (Optional)

Packag e Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

Prefix

ICS = Standard Device

ICS XXXX y G LF- T