LTC7810 150V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller FEATURES DESCRIPTION Wide VIN Range: 4.5V to 140V (150V Abs Max) nn Wide Output Voltage Range: 1V V OUT 60V nn Low Operating I : 16A (48V to 12V Q IN OUT and 3.3VOUT) nn Adjustable Gate Drive Level Up to 10V nn Optional Spread Spectrum Operation nn Very Low Dropout: 100% Duty Cycle Operation nn Low I in Dropout: 78A (One Channel On) Q nn R SENSE or Inductor DCR Current Sensing nn Out-of-Phase Controllers Reduce Required Input Capacitance and Power Supply Induced Noise nn Phase-Lockable Frequency (75kHz to 720kHz) nn Programmable Fixed Frequency (50kHz to 750kHz) nn Selectable Continuous, Pulse-Skipping, or Low Ripple Burst Mode(R) Operation at Light Loads nn Onboard LDO or External NMOS LDO for DRV CC nn EXTV CC LDO Powers Drivers from VOUT nn Programmable Input Overvoltage Lockout nn 48-Lead (7mm x 7mm) eLQFP Package The LTC(R)7810 is a high performance dual step-down DC/ DC switching regulator controller that drives all N-channel synchronous power MOSFET stages that can operate from voltages up to 140V. A constant frequency current mode architecture allows a phase-lockable frequency of up to 720kHz. nn APPLICATIONS The low no-load quiescent current extends operating run time in battery-powered systems. The LTC7810 features a precision 1V reference, enabling the output voltage to be programmed from 1V to 60V. The gate drive voltage for the LTC7810 can be programmed to 6V, 8V, or 10V to allow the use of logic-level or standard-threshold FETs and to maximize efficiency. The LTC7810 additionally features spread spectrum operation which significantly reduces the peak radiated and conducted noise on both the input and output supplies, making it easier to comply with electromagnetic interference (EMI) standards. All registered trademarks and trademarks are the property of their respective owners. Automotive and Transportation Industrial and Telecommunications nn Military/Avionics nn nn TYPICAL APPLICATION High Efficiency Dual 12V/ 5V Output Step-Down Regulator with Spread Spectrum Efficiency and Power Loss vs Load Current DRVCC VIN 12.5V to 140V RUN1 VIN RUN2 BOOST1 TG1 10H 0.1F 2.2F DRVCC 100 BOOST2 TG2 33H 0.1F SW1 EFFICIENCY SENSE1- SENSE2- EXTVCC 10m 8m VOUT1 5V/6A VOUT2 12V/5A 220k 22pF 470F 55k 12.1k 0.1F VFB1 ITH1 TRACK/SS1 DRVSET INTVCC PLLIN/SPREAD OVLO 1.5nF 0.1F GND NDRV MODE REGSD FREQ 220k 150F VFB2 ITH2 TRACK/SS2 20k 17.4k DRVCC 0.1F 1.5nF EFFICIENCY (%) SENSE2+ 80 1 POWER LOSS 0.1 70 60 50 0.001 VIN = 24V VIN = 72V VIN = 140V 0.01 0.1 1 LOAD CURRENT (A) 10 POWER LOSS (W) BG2 SENSE1+ 10 90 SW2 LTC7810 BG1 100 VOUT = 12V 0.01 0.001 7810 TA01b 7810 TA01a Rev. A Document Feedback For more information www.analog.com 1 LTC7810 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 3 Order Information........................................... 3 Pin Configuration........................................... 3 Electrical Characteristics.................................. 4 Typical Performance Characteristics.................... 7 Pin Functions............................................... 10 Functional Diagram....................................... 12 Operation................................................... 13 Main Control Loop................................................... 13 Power and Bias Supplies (VIN, NDRV, EXTVCC, DRVCC, REGSD)....................................................... 13 Boost Supply and Dropout (BOOST and SW pins).................................................................. 14 Start-Up and Shutdown (RUN, TRACK/SS, OVLO Pins).............................................................. 14 Light Load Operation: Burst Mode Operation, Pulse Skipping or Forced Continuous Mode (MODE Pin).................................................... 14 Frequency Selection, Spread Spectrum, and Phase-Locked Loop (FREQ and PLLIN/SPREAD Pins)............................................... 16 Applications Information................................. 17 Current Sense Selection.......................................... 17 Low Value Resistor Current Sensing........................ 17 Inductor DCR Sensing............................................. 17 Setting the Operating Frequency............................. 19 Selecting the Light-Load Operating Mode................ 19 Inductor Value Calculation.......................................20 2 Inductor Core Selection........................................... 21 Power MOSFET Selection........................................ 21 CIN and COUT Selection............................................22 Setting the Output Voltage.......................................22 RUN Pins and Overvoltage/Undervoltage Lockout....................................................................23 Tracking and Soft-Start (TRACK/SS1, TRACK/SS2 Pins).................................................... 24 Single Output Two-Phase Operation........................25 DRVCC Regulators....................................................25 Topside MOSFET Driver Supply (CB, DB)................. 27 Burst Clamp Programming...................................... 28 Fault Conditions: Current Limit and Current Foldback......................................................29 Fault Conditions: Overvoltage Protection (Crowbar)...............................................29 Fault Conditions: Overtemperature Protection.........29 Phase-Locked Loop and Frequency Synchronization.......................................................29 Minimum On-Time Considerations..........................30 Efficiency Considerations........................................30 Checking Transient Response.................................. 31 Design Example....................................................... 32 PC Board Layout Checklist......................................33 PC Board Layout Debugging....................................35 Typical Applications....................................... 36 Package Description...................................... 40 Revision History........................................... 41 Typical Application........................................ 42 Related Parts............................................... 42 Rev. A For more information www.analog.com LTC7810 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) 48 47 46 45 44 43 42 41 40 39 38 37 SENSE1+ VFB1 ITH1 TRACK/SS1 NC NC TG1 SW1 BOOST1 NC NC BG1 TOP VIEW SENSE1- 1 DRVSET 2 INTVCC 3 PLLIN/SPREAD 4 SGND 5 FREQ 6 REGSD 7 MODE 8 OVLO 9 NDRV 10 EXTVCC 11 SENSE2- 12 49 SGND 36 35 34 33 32 31 30 29 28 27 26 25 NC VIN NC NC RUN1 NC NC RUN2 NC NC DRVCC PGND SENSE2+ 13 VFB2 14 ITH2 15 TRACK/SS2 16 NC 17 NC 18 TG2 19 SW2 20 BOOST2 21 NC 22 NC 23 BG2 24 Input Supply Voltage (VIN)........................ -0.3V to 150V RUN1, RUN2 Voltages............................... -0.3V to 150V BOOST1, BOOST2..................................... -0.3V to 150V Switch Voltage (SW1, SW2)......................... -5V to 150V (BOOST1-SW1), (BOOST2-SW2).................-0.3V to 11V EXTVCC Voltage.......................................... -0.3V to 65V DRVCC Voltage.............................................-0.3V to 11V (NDRV-DRVCC) Voltage (Note 9)................... -0.3V to 6V PLLIN/SPREAD, FREQ Voltages.................... -0.3V to 6V TRACK/SS1, TRACK/SS2 Voltages............... -0.3V to 6V ITH1, ITH2, VFB1, VFB2, MODE Voltages........ -0.3V to 6V OVLO, REGSD, DRVSET Voltages................. -0.3V to 6V SENSE1+, SENSE2+, SENSE1-, SENSE2- Voltages...................................... -0.3V to 65V BG1, BG2, TG1, TG2.......................................... (Note 10) Operating Junction Temperature Range (Notes 2, 8) LTC7810E, LTC7810I........................... -40C to 125C LTC7810H........................................... -40C to 150C Storage Temperature Range............... -65C to 150C LXE PACKAGE 48-LEAD (7mm x 7mm) PLASTIC eLQFP TJMAX = 150C, JA = 20C/W EXPOSED PAD (PIN 49) IS SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7810ELXE#PBF LTC7810 48-Lead (7mm x 7mm) Plastic eLQFP -40C to 125C LTC7810ILXE#PBF LTC7810 48-Lead (7mm x 7mm) Plastic eLQFP -40C to 125C LTC7810HLXE#PBF LTC7810 48-Lead (7mm x 7mm) Plastic eLQFP -40C to 150C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. A For more information www.analog.com 3 LTC7810 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C, VIN = 12V, RUN1,2 = 5V, EXTVCC = 0V, DRVSET = INTVCC unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN (Note 11) TYP MAX UNITS 4.5 140 V 1 60 V Input Supply (VIN) VIN Input Supply Operating Range VOUT1,2 Regulated Output Voltage Set Point IVIN VIN Current in Regulation IQ Figure 14 Circuit, 48V to 12V and 3.3V, No Load 16 A Figure 14 Circuit, 12V to 3.3V, No Load, RUN2 = 0V 32 A No-Load DC Supply Current (Note 5) Shutdown VIN Current RUN1,2 = 0V 1.5 5 A Sleep Mode VIN Current (Note 3) VSENSE1- 3.2V, VEXTVCC = 12V VSENSE1- 3.2V, VEXTVCC = 0V VSENSE1- < 3.2V 4 25 40 8 50 75 A A A Sleep Mode SENSE1- Current (Note 3) VSENSE1- 3.2V 16 30 A Sleep Mode EXTVCC Current (Note 3) VEXTVCC = 12V 23 45 A Low IQ Dropout (One Channel On) VFB = 0.97V, VIN = VSENSE- 8V, No Load Combined VIN and VSENSE- DC Supply Current 78 130 A Low IQ Dropout (Both Channels On) VFB1,2 = 0.97V, VIN = VSENSE1,2- 8V, No Load Combined VIN and VSENSE- DC Supply Current 110 160 A Pulse-Skipping or Forced Continuous Mode One Channel On Both Channels On 1.7 2.4 RUN Pin ON Threshold VRUN1, VRUN2 Rising l 1.17 RUN Pin Hysteresis OVLO Pin OFF Threshold 1.22 mA mA 1.27 120 VOVLO Rising l 1.17 OVLO Pin Hysteresis 1.22 V mV 1.27 65 V mV Controller Operation VFB1,2 gm1,2 VSENSE(MAX) Regulated Feedback Voltage (Note 4) VIN = 4.5V to 150V, ITH1 = 0.6V to 1.2V -40C to 85C, All Grades Feedback Current (Note 4) Feedback Overvoltage Threshold Relative to Regulated VFB1,2 Transconductance Amplifier gm (Note 4) ITH1,2 = 1.2V, Sink/Source = 5A Maximum Current Sense Threshold VFB1,2 = 0.9V, VSENSE1,2- = 3.3V VFB1,2 = 0.9V, VSENSE1,2- = 3.3V Current Sense Threshold Matching Between Channels ISENSE1,2+ ISENSE1 - SENSE1,2+ Pin Current SENSE1- Pin Current 0.985 0.990 7 1.0 1.0 1.015 1.010 V V -5 50 nA 10 13 % 2 l mmho 67 75 83 mV -5 0 5 mV 1 A VSENSE1,2+ = 3V VSENSE1- < 3V 3.2V VSENSE1- < INTVCC - 0.5V VSENSE1- > INTVCC + 0.5V VSENSE1- 8V, in Low IQ Dropout 6 60 540 25 A A A A 4 480 4 A A A ISENSE2- SENSE2- Pin Current VSENSE2- < INTVCC - 0.5V VSENSE2- > INTVCC + 0.5V VSENSE2- 8V, in Low IQ Dropout ITRACK/SS1,2 Soft-Start Charge Current VTRACK/SS1,2 = 0V 4 l 8 10 12 A Rev. A For more information www.analog.com LTC7810 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C, VIN = 12V, RUN1,2 = 5V, EXTVCC = 0V, DRVSET = INTVCC unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TG or BG On-Resistance DRVSET OPEN Pull-up Pull-down 2.0 1.0 TG or BG Transition Time Rise Time Fall Time DRVSET OPEN (Note 6) CLOAD = 3300pF CLOAD = 3300pF 40 20 ns ns TG Off to BG On Delay Synchronous Switch-On Delay Time DRVSET OPEN 35 ns BG Off to TG On Delay Top Switch-On Delay Time DRVSET OPEN 35 ns TG Minimum On-Time (Note 7) DRVSET OPEN 90 ns Maximum Duty Cycle Output in Dropout, VSENSE- < 8V Output in Dropout, VSENSE- 8V 99 100 % % 105 A 8.5 V Gate Drivers tON(MIN) BOOST Charge Pump Available Output Current Output in Dropout, VBOOST = 16V, VSW = 12V, FREQ = 0V BOOST-SW Charge Pump Voltage Output in Dropout, VSENSE- 8V Low Dropout (LDO) Linear Regulators DRVCC Regulation Point for EXTVCC and NDRV DRVSET = INTVCC LDOs DRVSET = 0V DRVSET OPEN VCCXO DRVCC Regulation Point for Internal VIN LDO DRVSET = INTVCC DRVSET = 0V DRVSET OPEN EXTVCC LDO Switchover Voltage EXTVCC Rising DRVSET = INTVCC DRVSET = 0V DRVSET OPEN 5.7 7.6 9.6 Undervoltage Lockout 6.2 8.3 10.4 5.7 7.6 9.6 4.55 7.3 8.3 EXTVCC Switchover Hysteresis UVLO 6.0 8.0 10.0 4.7 7.5 8.5 V V V V V V 4.8 7.8 8.8 250 V V V mV DRVCC Rising DRVSET = INTVCC DRVSET = 0V DRVSET OPEN l l l 3.9 5.3 7.2 4.1 5.5 7.5 4.3 5.7 7.8 V V V DRVCC Falling DRVSET = INTVCC DRVSET = 0V DRVSET OPEN l l l 3.8 5.0 6.4 4.0 5.2 6.7 4.1 5.4 7.0 V V V REGSD Threshold Voltage VREGSD Rising 1.2 V REGSD Charge Current VREGSD = 1V, REGSD Rising 10 A REGSD Discharge Current VREGSD = 1V, REGSD Falling 10 A 4.5 V INTVCC Regulation Point Spread Spectrum Oscillator and Phase-Locked Loop fOSC Low Fixed Frequency VFREQ = 0V, PLLIN/SPREAD = 0V 160 200 230 kHz High Fixed Frequency VFREQ = INTVCC, PLLIN/SPREAD = 0V 230 300 340 kHz Programmable Frequency RFREQ = 25k, PLLIN/SPREAD = 0V RFREQ = 65k, PLLIN/SPREAD = 0V RFREQ = 105k, PLLIN/SPREAD = 0V 375 105 430 780 485 kHz kHz kHz Rev. A For more information www.analog.com 5 LTC7810 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25C, VIN = 12V, RUN1,2 = 5V, EXTVCC = 0V, DRVSET = INTVCC unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN fSYNC Synchronizable Frequency Range PLLIN/SPREAD = External Clock PLLIN Input High Level PLLIN Input Low Level 75 l l 2.5 MAX UNITS 720 kHz 0.5 V V Spread Spectrum Frequency Range (Relative to fOSC) PLLIN/SPREAD = INTVCC, RFREQ = 105k Minimum Frequency Maximum Frequency -15 +15 % % Spread Spectrum Modulation Frequency PLLIN/SPREAD = INTVCC 4.5 kHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7810 is tested under pulsed load conditions such that TJ TA. The LTC7810E is guaranteed to meet specifications from 0C to 85C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7810I is guaranteed over the -40C to 125C operating junction temperature range and the LTC7810H is guaranteed over the -40C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in C) is calculated from the ambient temperature (TA, in C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD * JA), where JA (in C/W) is the package thermal impedance. Note 3: SENSE1- bias current is reflected to the input supply by the formula IVIN = ISENSE1- * VOUT1/(VIN * ), where is the efficiency. EXTVCC bias current is similarly reflected to the input supply when biased by an output greater than the EXTVCC LDO Switchover Voltage (VCCOX). Note 4: The LTC7810 is tested in a feedback loop that servos VITH1,2 to a specified voltage and measures the resultant VFB1,2. The specification at 85C is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125C for the LTC7810E/LTC7810I, 150C for the LTC7810H. 6 l TYP Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See the Applications Information section. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current > 40% of IMAX (See Minimum On-Time Considerations in the Applications Information section). Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 9: Do not apply a voltage or current source to the NDRV pin, other than tying NDRV to DRVCC when not used. If used it must be connected to capacitive loads only (see DRVCC Regulators in the Applications Information section), otherwise permanent damage may occur. Note 10: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur. Note 11: The minimum input supply operating range is dependent on the DRVCC UVLO thresholds as determined by the DRVSET pin setting. Rev. A For more information www.analog.com LTC7810 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency and Power Loss vs Load Current BURST EFFICIENCY FCM EFFICIENCY 10 1 50 PULSE- SKIPPING 0.1 LOSS 40 30 BURST LOSS 10 0 0.001 0.01 VIN = 48V VOUT = 12V FIGURE 14 CIRCUIT 0.01 0.1 1 LOAD CURRENT (A) 10 85 80 75 70 65 60 55 0.001 EFFICIENCY (%) 60 FCM LOSS 98 90 POWER LOSS (W) 70 20 100 95 PULSE-SKIPPING EFFICIENCY 80 Efficiency vs Input Voltage 100 50 0.001 VIN = 24V VIN = 48V VIN = 100V VIN = 140V 0.01 0.1 1 LOAD CURRENT (A) 10 Load Step Burst Mode Operation 92 88 INDUCTOR CURRENT 1A/DIV INDUCTOR CURRENT 1A/DIV 7810 G05 Inductor Current at Light Load RUN1,2 2V/DIV 65 90 115 INPUT VOLTAGE (V) 140 7810 G06 200s/DIV VIN = 24V VOUT = 12V 100mA to 3A LOAD STEP FIGURE 14 CIRCUIT, PLLIN/SPREAD = GND Soft Start-Up Regulated Feedback Voltage vs Temperature 1.010 FIGURE 14 CIRCUIT VOUT1 2V/DIV 7810 G07 40 200s/DIV VIN = 24V VOUT = 12V 100mA to 3A LOAD STEP FIGURE 14 CIRCUIT, PLLIN/SPREAD = GND VOUT2 5V/DIV PULSE SKIPPING MODE 15 Load Step Forced Continuous Mode VOUT 100mV/DIV 7810 G04 BURST MODE OPERATION 1A/DIV ILOAD = 100mA 7810 G03 VOUT 100mV/DIV 200s/DIV VIN = 24V VOUT = 12V 100mA to 3A LOAD STEP FIGURE 14 CIRCUIT, PLLIN/SPREAD = GND FORCED CONTINUOUS MODE ILOAD = 4A 94 Load Step Pulse-Skipping Mode INDUCTOR CURRENT 1A/DIV 10s/DIV 96 7810 G02 7810 G01 VOUT 100mV/DIV FIGURE 14 CIRCUIT VOUT = 12V 90 FIGURE 14 CIRCUIT VOUT = 12V 2ms/DIV 7810 G08 VIN = 24V VOUT = 12V ILOAD = 100mA FIGURE 14 CIRCUIT, PLLIN/SPREAD = GND REGULATED FEEDBACK VOLTAGE (V) 90 EFFICIENCY (%) Efficiency vs Load Current 100 EFFICIENCY (%) 100 1.005 1.000 0.995 0.990 -55 -25 5 35 65 95 TEMPERATURE (C) 125 155 7810 G09 Rev. A For more information www.analog.com 7 LTC7810 TYPICAL PERFORMANCE CHARACTERISTICS 0 -30 -20 -40 -50 -60 -70 -30 -40 -50 -60 -70 -80 -80 -90 -90 -100 200 400 600 800 1000 FREQUENCY (kHz) 1200 FIGURE 15 CIRCUIT fSW = 600kHz VOUT = 3.3V PLLIN/SPREAD = INTVCC RBW = 5.1kHz -10 AMPLITUDE (dBm) -20 AMPLITUDE (dBm) 0 FIGURE 15 CIRCUIT fSW = 600kHz VOUT = 3.3V PLLIN/SPREAD = GND RBW = 5.1kHz -10 Output Voltage Frequency Spectrum (Spread Spectrum Enabled) 400 600 800 1000 FREQUENCY (kHz) 1200 7810 G10 40 VBOOST - VSW = 4V VBOOST - VSW = 7V VBOOST - VSW = 7V, LOW IQ DROPOUT 9.5 9.0 8.5 8.0 7.5 7.0 100 200 300 400 500 600 700 800 900 FREQUENCY (kHz) 0 10 400 300 200 100 0 60 60 40 10 20 30 40 50 60 VSENSE COMMON MODE VOLTAGE (V) 70 Normal Dropout, VBOOST - VSW = 4V Normal Dropout, VBOOST - VSW = 7V Low IQ Dropout, VBOOST - VSW = 4V Low IQ Dropout, VBOOST - VSW = 7V 0 10 20 30 40 50 INPUT VOLTAGE (V) 60 40 20 0 -20 -40 0 0.2 0.4 0.6 0.8 1.0 ITH VOLTAGE (V) 60 70 7810 G15 Foldback Current Limit 1.2 7810 G16 8 80 0 70 PULSE-SKIPPING FORCED CONTINUOUS BURST MODE (MODE=0V) BURST MODE (MODE=1V) 80 155 100 20 MAXIMUM CURRENT SENSE THRESHOLD (mV) SENSE CURRENT (A) MAXIMUM CURRENT SENSE THRESHOLD (mV) CHANNEL 1 CHANNEL 2 100 125 OUTPUT IN DROPOUT 140 VIN = VSW = VSENSE- FREQ = GND 120 Maximum Current Sense Threshold vs ITH Voltage 500 0 20 30 40 50 INPUT VOLTAGE (V) 5 35 65 95 TEMPERATURE (C) 7810 G14 SENSE Pins Total Input Current vs VSENSE Voltage 600 -25 BOOST Charge Pump Output Current in Dropout vs Input Voltage NORMAL DROPOUT LOW IQ DROPOUT 7810 G13 700 200 7810 G12 CHARGE PUMP CURRENT (A) VBOOST - VSW (V) CHARGE PUMP CURRENT (A) 60 0 300 160 OUTPUT IN DROPOUT 10.5 VIN = VSW = VSENSE- FREQ = GND 10.0 80 0 400 0 -55 1400 11.0 100 20 500 BOOST Charge Pump Output Voltage in Dropout vs Input Voltage OUTPUT IN DROPOUT VIN = VSW = VSENSE- = 12V 120 RFREQ = 30k RFREQ = 70k FREQ = 0V FREQ = INTVCC 600 7810 G11 BOOST Charge Pump Output Current vs Frequency 140 700 100 -100 200 1400 Oscillator Frequency vs Temperature FREQUENCY (kHz) Output Voltage Frequency Spectrum (Spread Spectrum Disabled) 1.4 7810 G17 100 90 80 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VFB VOLTAGE (V) 7810 G18 Rev. A For more information www.analog.com LTC7810 TYPICAL PERFORMANCE CHARACTERISTICS EXTVCC Switchover Thresholds vs Temperature DRVCC Load Regulation NDRV LDO, EXTVCC = 0V 8.9 VIN LDO, EXTVCC = 0V SWITCHOVER THRESHOLD (V) EXTVCC = 8.5V 5.0 4.5 EXTVCC = 5V 4.0 0 FALLING 7.7 DRVSET = 0V 6.5 10 RISING 7.1 FALLING 5.9 5.3 DRVSET = INTVCC 4.7 20 40 60 80 DRVCC LOAD CURRENT (mA) 100 -25 5 35 65 95 TEMPERATURE (C) SHUTDOWN CURRENT (A) 6.0 3.0 2.0 DRVSET = 0V 8 7 EXTVCC or NDRV LDO VIN LDO DRVSET = INTVCC 5 -55 -25 5 35 65 95 TEMPERATURE (C) 155 7810 G20 2.5 4.0 9 6 125 7810 G19 5.0 DRVSET OPEN RISING FALLING 3.5 -55 Shutdown Current vs Temperature 1.0 125 155 7810 G21 Shutdown Current vs VIN Voltage Quiescent Current vs Temperature 80 VIN = 12V 70 BURST MODE OPERATION 2.0 1.5 1.0 0.5 60 50 40 30 20 10 0 -55 -25 5 35 65 95 TEMPERATURE (C) 125 0 155 0 30 7810 G22 RUN and OVLO Thresholds vs Temperature 1.35 1.30 8.0 RUN OR OVLO RISING RUN FALLING OVLO FALLING 7.5 7.0 1.25 1.20 1.15 1.10 FALLING 5 35 65 95 TEMPERATURE (C) 0 -55 150 6.0 RISING 5.5 5.0 FALLING 4.5 RISING 125 155 3.0 -55 5 35 65 95 TEMPERATURE (C) 125 155 7810 G24 TRACK/SS Pull-Up Current vs Temperature 10.3 10.2 DRVSET OPEN DRVSET = 0V 10.1 10.0 9.9 9.8 FALLING DRVSET = INTVCC -25 -25 7810 G23 6.5 3.5 -25 120 RISING 4.0 1.05 1.00 -55 60 90 VIN VOLTAGE (V) DRVCC Undervoltage Lockout Thresholds vs Temperature UVLO THRESHOLD (V) RUN OR OVLO PIN VOLTAGE (V) DRVSET OPEN 4.1 7.0 SHUTDOWN CURRENT (A) RISING 8.3 TRACK/SS CURRENT (A) DRVCC VOLTAGE 6.0 5.5 11 DRVCC VOLTAGE (V) VIN = 12V DRVSET = INTVCC DRVCC Voltage vs Temperature 9.5 QUIESCENT CURRENT (A) 6.5 5 35 65 95 TEMPERATURE (C) 125 7810 G25 155 7810 G26 9.7 -55 -25 5 35 65 95 TEMPERATURE (C) 125 155 7810 G27 Rev. A For more information www.analog.com 9 LTC7810 PIN FUNCTIONS DRVSET (Pin 2): DRVCC Regulation Program Pin. This pin sets the regulation point for the DRVCC low dropout (LDO) linear regulators. Tying this pin to GND sets DRVCC to 8V, tying it to INTVCC sets DRVCC to 6V, and floating this pin sets DRVCC to 10V. The DRVCC UVLO and EXTVCC switchover thresholds change correspondingly with the DRVCC regulation point, as listed in the Electrical Characteristics table. INTVCC (Pin 3): Output of the Internal 4.5V Low Dropout Regulator. Internal low voltage analog and digital circuits are powered by this supply. A low ESR 0.1F ceramic bypass capacitor should be connected between INTVCC and GND, as close as possible to the IC. PLLIN/SPREAD (Pin 4): External Synchronization Input to Phase Detector and Spread Spectrum Enable. When an external clock is applied to this pin, the phase-locked loop will force the rising TG1 signal to be synchronized with the rising edge of the external clock. When not synchronizing to an external clock, tie this input to INTVCC to enable spread spectrum dithering of the oscillator or to ground to disable spread spectrum. SGND (Pins 5, Exposed Pad Pin 49): Small-signal ground common to both controllers, must be routed separately from high current grounds to the common (-) terminals of the CIN capacitors. The exposed pad must be soldered to PCB ground for rated thermal performance. FREQ (Pin 6): Frequency Control Pin for the Internal VCO. Connecting the pin to GND forces the VCO to a fixed low frequency of 200kHz. Connecting the pin to INTVCC forces the VCO to a fixed high frequency of 300kHz. Other frequencies between 50kHz and 750kHz can be programmed using a resistor between FREQ and GND. The resistor and an internal 20A source current create a voltage used by the internal oscillator to set the frequency. REGSD (Pin 7): Regulator Shutdown Timer. This pin limits the time allowed for switching while the internal VIN or NDRV linear regulators are operating, due to EXTVCC being below its switchover voltage. A capacitor from REGSD to ground limits the time to tREGSD = 1.2* CREGSD /10A. When the REGSD voltage exceeds 1.2V, the linear regulator shuts down for 29 * tREGSD, giving a "regulator-on" 10 duty cycle of 3.3%. This pin sources 10A of current when EXTVCC is below the switchover voltage and the LTC7810 is not in sleep, and sinks 10A when EXTVCC is above the switchover voltage or when the LTC7810 is in sleep. Ground this pin to disable the regulator shutdown timer. MODE (Pin 8): Mode Select and Burst Clamp Adjust Input. This input determines how the LTC7810 operates at light loads. Pulling this pin to ground selects Burst Mode operation with a burst clamp level of 25% of VSENSE(MAX). Tying this pin to a voltage between 0.5V and 1V selects Burst Mode and adjusts the burst clamp level between 10% and 60%. Tying this pin to INTVCC forces continuous inductor current operation. Tying this pin to a voltage greater than 1.4V and less than INTVCC - 1.3V selects pulse-skipping operation. Do not float this pin. OVLO (Pin 9): Overvoltage Lockout Input. Forcing this pin above 1.22V disables switching of the controllers. The DRVCC and INTVCC regulation is maintained during an OVLO event. Exceeding the OVLO threshold triggers a soft-start reset. Tie this pin to ground if the OVLO function is not used. NDRV (Pin 10): Drive Output for External Pass Device of the NDRV LDO Regulator for DRVCC. Connect this pin to the gate of an external NMOS pass device. An internal charge pump allows NDRV to be driven above VIN for low dropout performance. Tie this pin to DRVCC if the NDRV regulator is not used. EXTVCC (Pin 11): External Power Input to an Internal LDO Connected to DRVCC. This LDO supplies DRVCC power, bypassing both the internal VIN LDO and the external NDRV LDO whenever EXTVCC is higher than its switchover threshold. See DRVCC Regulators in the Applications Information section. Do not exceed 65V on this pin. Connect this pin to ground if the EXTVCC LDO is not used. SENSE1-, SENSE2- (Pins 1, 12): The (-) Input to the Differential Current Comparators. When SENSE1, 2- is greater than INTVCC, the SENSE- pin supplies current to the current comparator. When SENSE1- is greater than 3.2V, it supplies the majority of the sleep mode quiescent current instead of VIN, further reducing the input-referred quiescent current. Rev. A For more information www.analog.com LTC7810 PIN FUNCTIONS SENSE1+, SENSE2+ (Pins 48, 13): The (+) Input to the Differential Current Comparators. The ITH pin voltage and controlled offsets between the SENSE- and SENSE+ pins in conjunction with RSENSE set the current trip threshold. VFB1, VFB2 (Pins 47, 14): Receives the remotely sensed feedback voltage for each buck controller from an external resistive divider across the output. Tie VFB2 to INTVCC for a two-phase single output application, in which both channels share VFB1, ITH1, and TRACK/SS1. ITH1, ITH2 (Pins 46,15): Error Amplifier Outputs and Switching Regulator Compensation Points. Each associated channel's current comparator trip point increases with this control voltage. TRACK/SS1, TRACK/SS2 (Pins 45, 16): External Tracking and Soft-Start Input. The LTC7810 regulates the VFB1,2 voltage to the lesser of 1V or the voltage on the TRACK/SS1,2 pin. An internal 10A pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to the final regulated output voltage. The ramp time is equal to 1ms for every 10nF of capacitance. Alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC7810 output to track the other supply during startup. NC (Pins 17, 18, 22, 23, 27, 28, 30, 31, 33, 34, 36, 38, 39, 43, 44): No Internal Connection. Float these pins or connect to ground. TG1, TG2 (Pins 42, 19): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to DRVCC - VD superimposed on the switch node voltage SW, where VD is the forward voltage drop of the external bootstrap diode. SW1, SW2 (Pins 41, 20): Switch Node Connections to Inductors. BOOST1, BOOST2 (Pins 40, 21): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the BOOST and SW pins and external bootstrap diodes are tied between the BOOST and DRVCC pins. Voltage swing at the BOOST pins is from DRVCC to (VIN + DRVCC). BG1, BG2 (Pins 37, 24): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from PGND to DRVCC. PGND (Pin 25): Driver Power Ground. Connects to the sources of bottom (synchronous) N-channel MOSFETs and the (-) terminal(s) of CIN. DRVCC (Pin 26): Output of the Internal or External Low Dropout Regulator. The gate drivers are powered from this voltage source. The DRVCC voltage regulation point is set by the DRVSET pin. DRVCC must be decoupled to ground with a 2.2F to 10F ceramic or other low ESR capacitor. Do not use the DRVCC pin for any other purpose. RUN1, RUN2 (Pins 32, 29): Run Control Inputs. Forcing this pin below 1.1V disables switching of the corresponding controller. Forcing both RUN pins below 0.7V shuts down the entire LTC7810, reducing quiescent current to approximately 1.5A. These pins can be tied to VIN for always-on operation. Do not float these pins. VIN (Pin 35): Main Supply Pin. A bypass capacitor should be tied between this pin and SGND. Rev. A For more information www.analog.com 11 12 VIN 20A For more information www.analog.com DRVCC EN 6V 8V 10V NDRV LDO CHARGE PUMP NDRV VIN EXTVCC DRVSET PLLIN/SPREAD FREQ MODE OVLO EN INTVCC LDO INTVCC 4.7V 7.5V 8.5V VIN LDO SPREAD SPECTRUM 1.22V CLK2 REGSD REGFLT REGSD TIMER CLK1 EXTVCC LDO EN SYNC DET 10A PFD VCO TEMPERATURE MONITOR UVLO 1.4V ICMP Q ITH CLAMP 1.1V SLOPE COMP 1.4V BCLAMP 0.425V R S SLEEP CHARGE PUMP 10A EA 3mV 1V SWITCH LOGIC ALLOFF BOT ALLOFF SW1,2 TOP ON DROPOUT DETECT 8V SENSE1,2- DUPLICATE FOR SECOND CONTROLLER CHANNEL 1.22V RUN1,2 IR BOT TOP PGND BG1,2 TRACK/SS1,2 ITH1,2 VFB1,2 SENSE1,2- SENSE1,2+ DRVCC SW1,2 TG1,2 BOOST1,2 RF1 RF2 L VIN1,2 CSS CB DB DRVCC CC2 CC1 RSENSE CIN RC 7810 BD COUT VOUT1,2 LTC7810 FUNCTIONAL DIAGRAM Rev. A LTC7810 OPERATION (Refer to the Functional Diagram) Main Control Loop The LTC7810 is a dual synchronous step-down controller utilizing a constant frequency, peak current mode control architecture. The two controller channels operate 180 out of phase which reduces the required input capacitance and power supply induced noise. During normal operation, the external top MOSFET is turned on when the clock for that channel sets the SR latch, causing the inductor current to increase. The top MOSFET is turned off when the main current comparator, ICMP, trips and resets the SR latch. After the top MOSFET is turned off each cycle, the bottom MOSFET is turned on which causes the inductor current to decrease until either the current starts to reverse, as indicated by the reverse current comparator IR, or the beginning of the next clock cycle. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, EA. The error amplifier compares the output voltage feedback signal at the VFB pin (which is generated with an external resistor divider connected across the output voltage, VOUT, to ground) to the internal 1V reference voltage. When the load current increases, it causes a slight decrease in VFB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current matches the new load current. Power and Bias Supplies (VIN, NDRV, EXTVCC, DRVCC, REGSD) The DRVCC pin supplies power for the MOSFET drivers and can be set to 6V, 8V, or 10V depending on the state of the DRVSET pin. Three LDOs (low dropout linear regulators) are available to provide power to DRVCC. The internal VIN LDO powers DRVCC through a P-channel pass device connected from VIN to DRVCC. At high input voltage, this LDO from VIN dissipates significant power; therefore, to prevent high on-chip power dissipation in high input voltage applications, the LTC7810's NDRV pin can drive the gate of an external N-channel MOSFET linear regulator from VIN. This NDRV LDO includes an internal charge pump that allows NDRV to be driven above VIN for low dropout performance. The internal VIN LDO has a slightly lower regulation point than the NDRV LDO to ensure that the external MOSFET is supplying the current to DRVCC. In high voltage applications, the power dissipation in the VIN and NDRV LDOs is significant and in many cases cannot be supplied indefinitely. Therefore, the LTC7810 also includes an additional EXTVCC LDO that can generate DRVCC more efficiently from a lower voltage supply. When EXTVCC is taken above its switchover voltage, the EXTVCC LDO turns on and powers DRVCC from the EXTVCC pin. This allows the DRVCC power to be derived from a high efficiency external source such as one of the LTC7810 switching regulator outputs. In general, the EXTVCC pin should be connected to an output voltage (VOUT1 or VOUT2) that is greater than the DRVCC regulation point. If both VOUT1 and VOUT2 are greater than DRVCC, connect EXTVCC to the lesser of the two for higher efficiency and lower power dissipation. If EXTVCC is below its switchover voltage (for example, if EXTVCC is tied to an output that is shorted to ground), the LTC7810 implements a failsafe regulator timeout to limit the power dissipation in both the internal VIN LDO and the external NDRV LDO. When the DRVCC bias is supplied by the VIN or NDRV LDOs and the part is not in sleep mode, a 10A current source pull-up charges an external capacitor connected to the REGSD pin. If the voltage on the REGSD exceeds 1.2V, then a regulator timeout occurs and switching of the top and bottom power MOSFETs is disabled, which dramatically reduces the power dissipation. After a long cool-down delay (approximately 29 times the REGSD charge time), a restart is initiated. This results in an "on" duty cycle of approximately 3.3% for the VIN and NDRV LDOs, which reduces the steady-state power dissipation in these LDOs by a factor of 30. When EXTVCC is above its switchover voltage or the part is in sleep mode, the REGSD pin is discharged by a 10A current source. In low input voltage applications, the regulator shutdown timer may not be needed and can be disabled by tying the REGSD pin to ground. See DRVCC Regulators in the Applications Information section for more information. Rev. A For more information www.analog.com 13 LTC7810 OPERATION Boost Supply and Dropout (BOOST and SW pins) Each top MOSFET driver is biased from a floating Boost Supply, consisting of the bootstrap capacitor, CB, and external diode DB, which normally recharges from DRVCC during each cycle whenever SW goes low. When the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top MOSFET continuously. If the output voltage is below 8V, the top MOSFET is forced off for about one-twelfth of the clock period every tenth cycle to allow CB to recharge, resulting in an effective 99% maximum duty cycle. If the output voltage on the SENSE- pins is above 8V, the LTC7810 enables an internal charge pump that allows the top MOSFET to be turned on continuously at 100% duty cycle. Furthermore, if Burst Mode is also selected (MODE 1V) and the differential SENSE pin voltage (SENSE+ - SENSE-) is less than 30% of VSENSE(MAX), the LTC7810 enters a Low IQ Dropout mode in which the majority of internal circuitry is disabled, reducing the supply current to 45A (one channel in dropout, one channel shutdown) or 67A (both channels in dropout). In low IQ dropout mode, the internal charge pump is pulsed to maintain an average gate-source voltage on the top MOSFET of 8.5V. Start-Up and Shutdown (RUN, TRACK/SS, OVLO Pins) The two channels of the LTC7810 can be independently shut down using the RUN1 and RUN2 pins. Pulling a RUN pin below 1.1V shuts down the main control loop for that channel. Pulling both pins below 0.7V disables both controllers and most internal circuits, including the DRVCC and INTVCC LDOs. In this shutdown state, the LTC7810 draws only 1.5A of quiescent current. The RUN pins may be externally pulled up or driven directly by logic. Each pin can tolerate up to 150V (absolute maximum), so it can be conveniently tied to VIN in always-on applications where one or both controllers are enabled continuously and never shut down. Additionally, a resistive divider from VIN to the RUN pins can be used to set a precise input undervoltage lockout so that the power supply will not operate below a user-adjustable level. Furthermore, switching is similarly inhibited if the 14 voltage on the OVLO pin exceeds 1.22V. This pin can be configured as an input overvoltage lockout to prevent power supply operation during an overvoltage condition on the input supply. When switching is disabled by the RUN or OVLO pins, the LTC7810 can safely sustain input voltages up to the absolute maximum rating of 150V. These events trigger a soft-start reset, which results in a graceful recovery from an input supply transient. Do not float the RUN1, RUN2, or OVLO pins. The start-up of each controller's output voltage VOUT is controlled by the voltage on the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/SS2 for channel 2). When the voltage on the TRACK/SS pin is less than the 1V internal reference, the LTC7810 regulates the VFB voltage to the TRACK/SS pin voltage instead of the 1V reference. This allows the TRACK/SS pin to be used as a soft-start which smoothly ramps the output voltage on startup, thereby limiting the input supply inrush current. An external capacitor from the TRACK/SS pin to GND is charged by an internal 10A pull-up current, creating a voltage ramp on the TRACK/SS pin. As the TRACK/SS voltage rises linearly from 0V to 1V (and beyond), the output voltage VOUT rises smoothly from zero to its final value. Alternatively the TRACK/SS pins can be used to make the startup of VOUT track that of another supply. Typically, this requires connecting to the TRACK/SS pin an external resistor divider from the other supply to ground (see Applications Information section). Light Load Operation: Burst Mode Operation, Pulse Skipping or Forced Continuous Mode (MODE Pin) The LTC7810 can be set to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the MODE pin to GND or a voltage between 0.5V and 1V. To select forced continuous operation, tie the MODE pin to INTVCC. To select pulse-skipping mode, tie the MODE pin to a DC voltage greater than 1.1V and less than INTVCC - 1.3V. This can be done with a resistive divider between INTVCC and GND, with both resistors being 100k. Rev. A For more information www.analog.com LTC7810 OPERATION When a controller is enabled for Burst Mode operation, the minimum peak current in the inductor (burst clamp) is adjustable and can be programmed by the voltage on the MODE pin. Tying the MODE pin to GND sets the default burst clamp to approximately 25% of the maximum sense voltage even when the voltage on the ITH pin indicates a lower value. A voltage between 0.5V and 1V on the MODE pin programs the burst clamp linearly between 10% and 60% of the maximum sense voltage. This facilitates a trade-off between light load efficiency and output voltage ripple. Higher burst clamp levels result in higher light load efficiency, but also in higher light load output voltage ripple. In Burst Mode operation, if the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes high (enabling sleep mode) and both external MOSFETs are turned off. The ITH pin is then disconnected from the output of the EA and parked at 0.45V. In sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC7810 draws. If both channels are in sleep mode or if one channel is in sleep mode and the other channel is shut down, the LTC7810 draws only 40A of quiescent current. When VOUT on channel 1 is 3.2V or higher, the majority of this quiescent current is supplied by the SENSE1- pin, which further reduces the input-referred quiescent current by the ratio of VIN /VOUT multiplied by the efficiency. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA's output begins to rise. When the output voltage drops enough, the ITH pin is reconnected to the output of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (IR) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates discontinuously. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and less interference with audio circuitry. In forced continuous mode, the output ripple is independent of load current. When the MODE pin is connected for pulse-skipping mode, the LTC7810 operates in PWM pulse-skipping mode at light loads. In this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the current comparator, ICMP, may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Unlike forced continuous mode and pulse-skipping mode, Burst Mode cannot be synchronized to an external clock. Therefore, if Burst Mode is selected and the PLLIN/SPREAD pin is clocked to use the phase-locked loop, the LTC7810 switches from Burst Mode to forced continuous mode. Rev. A For more information www.analog.com 15 LTC7810 OPERATION Frequency Selection, Spread Spectrum, and PhaseLocked Loop (FREQ and PLLIN/SPREAD Pins) The free running switching frequency of the LTC7810 controllers is selected using the FREQ pin. Tying FREQ to GND selects 200kHz while tying FREQ to INTVCC selects 300kHz. Placing a resistor between FREQ and GND allows the frequency to be programmed between 50kHz and 750kHz. Switching regulators can be particularly troublesome for applications where electromagnetic interference (EMI) is a concern. To improve EMI, the LTC7810 can operate in spread spectrum mode, which is enabled by tying the PLLIN/SPREAD pin to INTVCC. This feature varies the switching frequency at a 4.5kHz rate with a triangular frequency modulation of 15% of the frequency set by the FREQ pin. For example, if the LTC7810's frequency is programmed to switch at 300kHz, enabling spread spectrum will modulate the frequency between 255kHz and 345kHz at a 4.5kHz rate. 16 A phase-locked loop (PLL) is available on the LTC7810 to synchronize the internal oscillator to an external clock source connected to the PLLIN/SPREAD pin. The LTC7810's phase detector (PFD) and low pass filter adjust the voltage of the VCO input to align the turn-on of controller 1's external top MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2's external top MOSFET is 180 out-of-phase to the rising edge of the external clock source. The VCO input voltage is prebiased to the free running frequency set by the FREQ pin before the external clock is applied. If prebiased near the external clock frequency, the PLL only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock to the rising edge of TG1. The ability to prebias the loop filter allows the PLL to lock-in rapidly without deviating far from the desired frequency. The LTC7810's PLL is guaranteed to lock to an external clock source whose frequency is between 75kHz and 720kHz. The PLLIN/ SPREAD pin is TTL compatible with thresholds of 1.6V (rising) and 1.1V (falling) and is guaranteed to operate with a clock signal swing of 0.5V to 2.5V. Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION The Typical Application on the first page is a basic LTC7810 application circuit. External component selection is largely driven by the load requirement and begins with the selection of the current sense components, operating frequency, and light load operating mode. The power stage components, consisting of the inductor, input and output capacitors, and power MOSFETs can then be chosen. Next, feedback resistors are selected to set the desired output voltage. Then, the remaining external components are selected, such as for VIN undervoltage/overvoltage lockout, soft-start, DRVCC bias, and loop compensation. Current Sense Selection The LTC7810 can be configured to use either DCR (inductor resistance) sensing or low value resistor sensing. The choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. DCR sensing has become popular because it saves expensive current sensing resistors and is more power efficient, particularly in high current applications. However, current sensing resistors provide the most accurate current limits for the controller. Other external component selection is driven by the load requirement, and begins with the selection of RSENSE (if RSENSE is used) and inductor value. The SENSE+ and SENSE- pins are the inputs to the current comparators. The common mode voltage range on these pins is 0V to 65V (absolute maximum), enabling the LTC7810 to regulate output voltages up to a nominal 60V (allowing margin for tolerances and transients). The SENSE+ pin is high impedance, drawing less than 1A. This high impedance allows the current comparators to be used in inductor DCR sensing. The impedance of the SENSE- pin changes depending on the common mode voltage. When SENSE- is less than INTVCC - 0.5V, it is relatively high impedance, drawing 4A. When SENSE- is above INTVCC + 0.5V, a higher current ( 480A) flows into the pin. Between INTVCC - 0.5V and INTVCC + 0.5V, the current transitions from the smaller current to the higher current. Channel 1's SENSE1- has an additional 60A current when its voltage is above 3.2V to bias internal circuitry from VOUT1, thereby reducing the effective input supply current. Filter components mutual to the sense lines should be placed close to the LTC7810, and the sense lines should run close together to a Kelvin connection underneath the current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. If DCR sensing is used (Figure 2b), resistor R1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. TO SENSE FILTER NEXT TO THE CONTROLLER COUT CURRENT FLOW INDUCTOR OR RSENSE 7810 F01 Figure 1. Sense Lines Placement with Inductor or Sense Resistor Low Value Resistor Current Sensing A typical sensing circuit using a discrete resistor is shown in Figure 2a. RSENSE is chosen based on the required output current. Each controller's current comparator has a threshold VSENSE(MAX) of 75mV. The current comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current, IMAX, equal to the peak value less half the peak-to-peak ripple current, IL. To calculate the sense resistor value, use the equation: R SENSE = VSENSE(MAX) IMAX + IL 2 (1) Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC7810 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure 2b. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less than 1m for today's low value, high current inductors. In a high current application requiring such an inductor, Rev. A For more information www.analog.com 17 LTC7810 APPLICATIONS INFORMATION VIN1,2 BOOST TG LTC7810 RSENSE SW VOUT1,2 Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: R SENSE(EQUIV) = BG SENSE1,2+ GND 7810 F02a (2a) Using a Resistor to Sense Current VIN1,2 BOOST LTC7810 INDUCTOR TG L SW DCR VOUT1,2 SENSE1,2 RD = R1 C1* R2 - GND *PLACE C1 NEAR SENSE PINS (R1||R2) * C1 = L/DCR RSENSE(EQ) = DCR(R2/(R1+R2)) 7810 F02b (2b) Using the Inductor DCR to Sense Current R SENSE(EQUIV) DCRMAX at TL(MAX) (2) power loss through a sense resistor would cost several points of efficiency compared to inductor DCR sensing. If the external (R1||R2)*C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2 /(R1 + R2). R2 scales the voltage across the sense terminals for applications where the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the DCR of the inductor must be known. It can be measured using a good RLC meter, but the DCR tolerance is not always the same and varies with temperature; consult the manufacturers' data sheets for detailed information. (3) C1 is usually selected to be in the range of 0.1F to 0.47F. This forces R1|| R2 to around 2k, reducing error that might have been caused by the SENSE+ pin's 1A current. The equivalent resistance R1||R2 is scaled to the room temperature inductance and maximum DCR: R1|| R2 = Figure 2. Current Sensing Methods 18 IL 2 Next, determine the DCR of the inductor. When provided, use the manufacturer's maximum value, usually given at 20C. Increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/C. A conservative value for TL(MAX) is 100C. To scale the maximum inductor DCR to the desired sense resistor value (RD), use the divider ratio: BG SENSE1,2+ IMAX + To ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for VSENSE(MAX) in the Electrical Characteristics table. CAP PLACED NEAR SENSE PINS SENSE1,2- VSENSE(MAX) L (DCR at 20C) * C1 (4) The sense resistor values are: R1= R1|| R2 RD ; R2 = R1* RD 1- RD (5) The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSS R1= (VIN(MAX) - VOUT ) * VOUT R1 (6) Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION Setting the Operating Frequency For most LTC7810 applications, a good balance between size and efficiency is achieved with a switching frequency between 150kHz and 350kHz. Operating at higher switching frequencies up to 750kHz is readily possible, but switching losses generally limit the input voltage to lower levels. The switching frequency is set using the FREQ and PLLIN/SPREAD pins as shown in Table 1. Table 1. FREQ PIN PLLIN/SPREAD PIN FREQUENCY 0V 0V 200kHz INTVCC 0V 300kHz Resistor to GND 0V 50kHz to 750kHz Any of the Above External Clock 75kHz to 720kHz Phase-Locked to External Clock Any of the Above INTVCC Spread Spectrum fOSC modulated 15% Tying the FREQ pin to ground selects 200kHz while tying FREQ to INTVCC selects 300kHz. Since the FREQ pin sources 20A, placing a resistor between FREQ and ground allows the frequency to be programmed anywhere between 50kHz and 750kHz. Choose a FREQ pin resistor from Figure 3 or the following equation: fOSC 9 + 13.5k 800 700 600 500 400 300 200 Selection of the operating frequency is a trade-off between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing gate charge and transition losses, but requires larger inductance values and/or capacitance to maintain low output ripple voltage. RFREQ = 900 FREQUENCY (kHz) or sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. (7) 100 0 15 25 35 45 55 65 75 85 95 105 115 125 FREQ PIN RESISTOR (k) 7810 F03 Figure 3. Relationship Between Oscillator Frequency and Resistor Value at the FREQ Pin To improve EMI, spread spectrum mode can optionally be selected by tying the PLLIN/SPREAD pin to INTVCC. When spread spectrum is enabled, the switching frequency varies with a 4.5kHz triangular modulation to 15% of the frequency selected by the FREQ pin. Spread spectrum may be used in any operating mode selected by the MODE pin (Burst Mode, pulse-skipping, or forced continuous mode). A phase-locked loop (PLL) is also available on the LTC7810 to synchronize the internal oscillator to an external clock source that is connected to the PLLIN/SPREAD pin. Once synchronized, TG1 is aligned to the rising edge of the synchronizing signal. See the Phase-Locked Loop and Frequency Synchronization section for details. Selecting the Light-Load Operating Mode The LTC7810 can be set to enter high efficiency Burst Mode operation, constant frequency pulse-skipping mode or forced continuous conduction mode at light load currents. To select Burst Mode operation with default burst clamp (25% of VSENSE(MAX), tie the MODE pin to ground. To linearly adjust the burst clamp between 10% and 60%, tie the mode pin to a voltage between 0.5V (10% burst clamp) and 1V (60% burst clamp). See the Burst Clamp Programming section for more information. To select forced continuous operation, tie the MODE pin to INTVCC. To select pulse-skipping mode, tie the MODE pin to a divider comprised of two 100k resistors from INTVCC to Rev. A For more information www.analog.com 19 LTC7810 APPLICATIONS INFORMATION ground. When synchronized to an external clock through the PLLIN/SPREAD pin, if Burst Mode or forced continuous operation is selected, the LTC7810 operates in forced continuous mode. If pulse-skipping is selected, the LTC7810 remains in pulse-skipping. Table 2 summarizes the use of the MODE pin to select light load operating mode. Table 2. MODE PIN LIGHT-LOAD OPERATING MODE MODE WHEN SYNCHRONIZED 0V Burst Mode 25% Burst Clamp Forced Continuous Mode 0.5V to 1V 2.25V (100k Divider from INTVCC) INTVCC Burst Mode Forced Continuous Mode 10% to 60% Burst Clamp Pulse-Skipping Mode Pulse-Skipping Mode Forced Continuous Mode Forced Continuous Mode In general, the requirements of each application will dictate the appropriate choice for light-load operating mode. In Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the regulator operates in discontinuous operation. In addition, when the load current is very light, the inductor current will begin bursting at frequencies lower than the switching frequency, and enter a low current sleep mode when not switching. As a result, Burst Mode operation has the highest possible efficiency at light load. In forced continuous mode, the inductor current is allowed to reverse at light loads and switches at the same frequency regardless of load. In this mode, the efficiency at light loads is considerably lower than in Burst Mode operation. However, continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. In forced continuous mode, the output ripple is independent of load current. In pulse-skipping mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. At very light loads, the PWM comparator may remain tripped for several cycles and force the top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, 20 like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Consequently, pulse-skipping mode represents a compromise between light load efficiency, output ripple and EMI. In some applications, it may be desirable to change light load operating mode based on the conditions present in the system. For example, if a system is inactive, one might select high efficiency Burst Mode operation by keeping the MODE pin set to 0V. When the system wakes, one might send an external clock to PLLIN/SPREAD, or tie MODE to INTVCC to switch to low noise forced continuous mode. Such on-the-fly mode changes can allow an individual application to benefit from the advantages of each lightload operating mode. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET switching and gate charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current, IL, decreases with higher inductance or higher frequency and increases with higher VIN: IL = V VOUT 1- OUT VIN (f)(L) 1 (8) Accepting larger values of IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IL = 0.3(IMAX). The maximum IL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION the burst clamp, which can be programmed between 10% and 60% of the current limit determined by RSENSE. (For more information see the Burst Clamp Programming section.) Lower inductor values (higher IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency regulators generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET Selection Two external power MOSFETs must be selected for each controller in the LTC7810: one N-channel MOSFET for the top (main) switch and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the DRVCC voltage. This voltage can be set to 6V, 8V, or 10V depending on configuration of the DRVSET pin. Therefore, both logic-level and standard-level threshold MOSFETs can be used in most applications depending on the programmed DRVCC voltage. Pay close attention to the BVDSS specification for the MOSFETs as well. Selection criteria for the power MOSFETs include the on resistance RDS(ON), Miller capacitance CMILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers' data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in VDS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified VDS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: V Main Switch Duty Cycle = OUT VIN Synchronous Switch Duty Cycle = VIN - VOUT (9) VIN The MOSFET power dissipations at maximum output current are given by: 2 V PMAIN = OUT IOUT(MAX) (1+ )RDS(ON) + VIN ( ) IOUT(MAX) (VIN )2 (RDR )(CMILLER ) * 2 (10) 1 1 + (f) VDRVCC - VTHMIN VTHMIN 2 V - VOUT IOUT(MAX) (1+ )RDS(ON) PSYNC = IN VIN ( ) where is the temperature dependency of RDS(ON) and RDR (approximately 2) is the effective driver resistance at the MOSFET's miller threshold voltage. VTHMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the main N channel equations include an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty cycle is low For more information www.analog.com Rev. A 21 LTC7810 APPLICATIONS INFORMATION or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but = 0.005/C can be used as an approximation for low voltage MOSFETs. CIN and COUT Selection The selection of CIN is simplified by the two-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor). It can be shown that the worst-case capacitor RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product needs to be used in the formula shown in Equation 11 to determine the maximum RMS capacitor current requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS ripple current from its maximum value. The out-of-phase technique typically reduces the input capacitor's RMS ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (VOUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS IMAX VIN [(VOUT )(VIN - VOUT )] 1/2 (11) This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers' ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC7810, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. 22 The benefit of the LTC7810 two-phase operation can be calculated by using Equation 11 for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor's ESR. This is why the input capacitor's requirement calculated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a two-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The drains of the top MOSFETs should be placed within 1cm of each other and share a common CIN(s). Separating the drains and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1F to 1F) bypass capacitor between the chip VIN pin and ground, placed close to the LTC7810, is also suggested. An optional 2.2 to 10 resistor placed between CIN and the VIN pin provides further isolation from a noisy input supply. The selection of COUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (VOUT) is approximated by: 1 VOUT I L ESR + 8 * f * COUT (12) where f is the operating frequency, COUT is the output capacitance and IL is the ripple current in the inductor. The output ripple is highest at maximum input voltage since IL increases with input voltage. Setting the Output Voltage The LTC7810 output voltages are each set by an external feedback resistor divider carefully placed across the output, as shown in Figure 4 The regulated output voltage is determined by: R VOUT = 1V 1+ B RA (13) Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION VIN VOUT 1/2 LTC7810 RB R3 RUN CFF R4 VFB LTC7810 OVLO RA R5 7810 F05 7810 F04 Figure 4. Setting the Output Voltage Figure 5. Adjustable UV and OV Lockout To improve the frequency response, a feedforward capacitor, CFF , may be used. Great care should be taken to route the VFB lines away from noise sources, such as the inductor or the SW lines. OVLO event, resulting in a graceful recovery from an input supply transient. The OVLO pin is high impedance and must be kept below its absolute maximum rating of 6V. A Zener diode clamp should be placed on the OVLO pin if its 6V rating becomes a limitation. The OVLO pin must be grounded if it is not used. For applications with multiple output voltage levels, select channel 1 to be the lowest output voltage that is greater than 3.2V. When the SENSE1- pin (connected to VOUT1) is above 3.2V, it (instead of VIN) biases some internal circuitry, thereby increasing light load Burst Mode efficiency. Similarly, connect EXTVCC to the lowest output voltage that is greater than the selected DRVCC regulation point. EXTVCC is then used to supply the high current gate drivers as well as to relieve additional quiescent current from VIN, further reducing the VIN pin current to 4A in sleep. RUN Pins and Overvoltage/Undervoltage Lockout The LTC7810 is enabled using the RUN1 and RUN2 pins. The RUN pins have a rising threshold of 1.22V with 120mV of hysteresis. Pulling a RUN pin below 1.1V shuts down the main control loop and resets the soft-start for that channel. Pulling both RUN pins below 0.7V disables the controllers and most internal circuits, including the DRVCC and INTVCC LDOs. In this state, the LTC7810 draws only 1.5A of quiescent current. The RUN pins are high impedance must be externally pulled up/down or driven directly by logic. Each RUN pin can tolerate up to 150V (absolute maximum), so it can be conveniently tied to VIN in always-on applications where the controller is enabled continuously and never shut down. Do not float the RUN pins. The OVLO pin operates in a similar but inverted fashion to the RUN pins. Both channels of the LTC7810 are disabled when the OVLO pin rises above its threshold of 1.22V with 65mV of hysteresis. Soft-start is reset following an The RUN and OVLO pins can be configured as undervoltage (UVLO) and overvoltage (OVLO) lockouts on the VIN supply with a resistor divider from VIN to ground. A simple resistor divider can be used as shown in Figure 5 to meet specific VIN voltage requirements. The current that flows through the R3-R4-R5 divider will directly add to the shutdown, sleep, and active current of the LTC7810, and care should be taken to minimize the impact of this current on the overall efficiency of the application circuit. Resistor values in the M range may be required to keep the impact on quiescent shutdown and sleep currents low. To pick resistor values, the sum total of R3 + R3 + R5 (RTOTAL) should be chosen first based on the allowable DC current that can be drawn from VIN. The individual values of R3, R4 and R5 can be calculated from the following equations: R5 = R TOTAL * R4 = R TOTAL * 1.22V Rising VIN OVLO Threshold 1.22V Rising VIN UVLO Threshold - R5 (14) R3 = R TOTAL - R5 - R4 For applications that do not require a precise OVLO, the OVLO pin can be tied directly to ground. The RUN pin in this type of application can be used as an external UVLO using the previous equations with R5 = 0. Rev. A For more information www.analog.com 23 LTC7810 APPLICATIONS INFORMATION Similarly, for applications that do not require a precise UVLO, the RUN pin can be tied to VIN. In this configuration, the UVLO threshold is limited to the internal DRVCC UVLO thresholds as shown in the Electrical Characteristics table. The resistor values for the OVLO can be computed using the previous equations with R3 = 0. Soft-start is enabled by simply connecting a capacitor from the TRACK/SS pin to ground, as shown in Figure 6. An internal 10A current source charges the capacitor, providing a linear ramping voltage at the TRACK/SS pin. The LTC7810 will regulate its feedback voltage (and hence VOUT) according to the voltage on the TRACK/SS pin, allowing VOUT to rise smoothly from 0V to its final regulated value. For a desired soft-start time, tSS, select a soft-start capacitor CSS = tSS * 10F/sec. Alternatively, the TRACK/SS1 and TRACK/SS2 pins can be used to track two (or more) supplies during start-up, as shown qualitatively in Figure 7a and Figure 7b. To do this, a resistor divider should be connected from the master supply (VX) to the TRACK/SS pin of the slave supply (VOUT), as shown in Figure 8. During start-up VOUT will track VX according to the ratio set by the resistor divider: VX VOUT = RA R TRACKA * R TRACKA + R TRACKB GND 7810 F06 Figure 6. Using the TRACK/SS Pin to Program Soft-Start VX(MASTER) VOUT(SLAVE) TIME 7810 F07a (7a) Coincident Tracking VX(MASTER) VOUT(SLAVE) TIME 7810 F07b (7b) Ratiometric Tracking Figure 7. Two Different Modes of Output Voltage Tracking VOUT (15) R A + RB TRACK/SS OUTPUT (VOUT) The start-up of each VOUT is controlled by the voltage on the TRACK/SS pin (TRACK/SS1 for channel 1, TRACK/SS2 for channel 2). When the voltage on the TRACK/SS pin is less than the internal 1V reference, the LTC7810 regulates the VFB pin voltage to the voltage on the TRACK/SS pin instead of the internal reference. The TRACK/SS pin can be used to program an external soft-start function or to allow VOUT to track another supply during start-up. CSS OUTPUT (VOUT) Tracking and Soft-Start (TRACK/SS1, TRACK/SS2 Pins) 1/2 LTC7810 RB VFB RA For coincident tracking (VOUT = VX during start-up), VX RA = RTRACKA 1/2 LTC7810 RTRACKB RB = RTRACKB TRACK/SS RTRACKA 7810 F08 Figure 8. Using the TRACK/SS Pin for Tracking 24 Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION VIN TG1 VIN CIN LTC7810 BG1 PGND SENSE1+ RUN1 ON SHUTDOWN L1 SW1 VIN RSENSE1 RUN2 SENSE1- SENSE2- VFB2 INTVCC VOUT RSENSE2 CINT RF1 COUT SENSE2+ VFB1 CITH TG2 ITH2 RITH 1nF 1nF L2 SW2 TRACK/SS2 CSS VIN RF2 ITH1 TRACK/SS1 SGND BG2 7810 F09 Figure 9. Single Output Two-Phase Operation Single Output Two-Phase Operation For high power applications, the two channels can be operated in a two-phase single output configuration. The two channels switch 180 out-of-phase, which reduces the required output capacitance in addition to the required input capacitance and power supply induced noise. To configure the LTC7810 for two-phase operation, tie VFB2 to INTVCC and RUN2 to RUN1. To prevent high frequency noise from coupling into the unused ITH2 and TRACK/ SS2 pins, either tie them to ground or, for lower burst mode quiescent current, place 1nF capacitors from these pins to ground. The RUN1, VFB1, ITH1, TRACK/SS1 pins are then used to control both channels, but each channel uses its own ICMP and IR comparators to monitor their respective inductor currents. Figure 9 shows the connections for single output two-phase operation. DRVCC Regulators The LTC7810 features three separate low dropout linear regulators (LDO) that can supply power at the DRVCC pin. The internal VIN LDO uses an internal P-channel pass device between the VIN and DRVCC pins. The internal EXTVCC LDO uses an internal P-channel pass device between the EXTVCC and DRVCC pins. The NDRV LDO utilizes the NDRV pin to drive the gate of an external N channel MOSFET acting as a linear regulator with its drain connected to VIN. The NDRV LDO provides an alternative method to supply power to DRVCC from the input supply without dissipating the power inside the LTC7810 IC. It has an internal charge pump that allows NDRV to be driven above the VIN supply, allowing for low dropout performance. The VIN LDO has a slightly lower regulation point than the NDRV LDO, such that all DRVCC current flows through the external N-channel MOSFET (and not through the internal P-channel pass device) when DRVCC reaches regulation. Do not float the NDRV pin. If the NDRV LDO is not being used, short NDRV to DRVCC. When laying out the PC board, care should be taken to route NDRV away from any switching nodes, such as SW, TG, and BOOST. Coupling to the NDRV node could cause its voltage to collapse and the NDRV LDO to lose regulation. If this occurs, the internal VIN LDO would take over and maintain DRVCC voltage at a slightly lower regulation point. However, internal heating of the IC would become a concern. High frequency noise from the VIN supply could also couple into the NDRV node through the gate-to-drain capacitance of the MOSFET and adversely affect NDRV regulation. The following are methods that could mitigate this potential Rev. A For more information www.analog.com 25 LTC7810 APPLICATIONS INFORMATION VIN VIN LTC7810 NDRV R1* C2* C1* DRVCC GND *R1, C1 AND C2 ARE OPTIONAL 7810 F10 Figure 10. Configuring the NDRV LDO issue (refer to Figure 10): 1) Add local decoupling capacitors right next to the drain of the external NDRV N-channel MOSFET in the PCB layout; 2) Insert a resistor (~100) in series with the gate of the NDRV MOSFET; 3) Insert a small capacitor (~1nF) between the gate and source of the NDRV MOSFET. When testing the application circuit, be sure the NDRV voltage does not collapse over the entire input voltage and output current operating range of the buck regulators. The DRVCC regulation point is set to 6V, 8V, or 10V based on the state of the DRVSET pin. Tie DRVSET to INTVCC to select 6V, to GND to select 8V, or float it to select 10V. Select the regulation point based on the MOSFETs that are used in the application. The regulation point should be set high enough to be above the "knee" in the MOSFET ID vs VGS curve. Setting the regulation point too low results in excess power loss in the MOSFETs due to I2R losses. Setting the regulation point too high results in excess power loss due to the additional gate charge required to switch the MOSFETs. The optimum regulation point can be selected by comparing the input supply current at a specific operating point. The DRVCC UVLO thresholds and EXTVCC switchover thresholds adjust correspondingly to the selected regulation point and are summarized in Table 3. Table 3. DRVSET PIN NDRV AND INTERNAL EXTVCC EXTVCC LDO VIN LDO DRVCC UVLO SWITCHOVER REGULATION REGULATION RISING RISING POINT POINT THRESHOLDS THRESHOLDS INTVCC 6V 5.8V 4.2V 4.7V GND 8V 7.7V 5.5V 7.5V FLOATING 10V 9.6V 7.5V 8.5V 26 High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7810 to be exceeded. The DRVCC current, which is dominated by the gate charge current, may be supplied by the VIN LDO, NDRV LDO or the EXTVCC LDO. When the voltage on the EXTVCC pin is less than its switchover threshold (4.7V, 7.5V, or 8.5V as determined by the DRVSET pin described above), the VIN and NDRV LDOs are enabled. Power dissipation in this case is highest and is equal to VIN * IDRVCC. If the NDRV LDO is not being used, this power is dissipated inside the IC. The gate charge current is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, if DRVCC is set to 6V, the DRVCC current is limited to less than 38mA from a 72V supply when not using the EXTVCC supply at a 70C ambient temperature: TJ = 70C + (38mA)(72V)(20C/W) = 125C (16) To prevent the maximum junction temperature from being exceeded, the VIN supply current must be checked while operating in forced continuous mode (MODE = INTVCC) at maximum VIN. When the voltage applied to EXTVCC rises above its switchover threshold, the VIN LDO and NDRV LDOs are turned off and the EXTVCC LDO is enabled. The EXTVCC LDO remains on as long as the voltage applied to EXTVCC remains above the switchover threshold minus the comparator hysteresis. The EXTVCC LDO attempts to regulate the DRVCC voltage to the voltage as programmed by the DRVSET pin, so while EXTVCC is less than this voltage, the LDO is in dropout and the DRVCC voltage is approximately equal to EXTVCC. When EXTVCC is greater than the programmed voltage, up to an absolute maximum of 65V, DRVCC is regulated to the programmed voltage. Significant efficiency and thermal gains can be realized by powering DRVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle) /(Switcher Efficiency). This is accomplished by tying the EXTVCC pin directly to an output voltage that is greater than the DRVCC regulation Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION point. If both VOUT1 and VOUT2 are greater than the DRVCC regulation point, tie EXTVCC to the lesser of the two for lowest power dissipation. The EXTVCC pin's absolute maximum voltage of 65V enables it to be connected to an output in nearly any application. EXTVCC may also be connected to any other supply in the system that is higher than the DRVCC regulation point and capable of providing the MOSFET gate drive current. For the previous example, tying the EXTVCC pin to a 12V supply reduces the junction temperature from 125C to: TJ = 70C + (38mA)(12V)(20C/W) = 79C (17) In applications where both outputs are less than the DRVCC regulation point, and no other supply available in the system, additional circuitry is required to derive DRVCC power from the output. Using the EXTVCC LDO allows the MOSFET driver and control power to be derived from one of the LTC7810's switching regulator outputs during normal operation and from the VIN LDO or NDRV LDO when the output is out of regulation (e.g., start-up, short-circuit). For a condition that keeps EXTVCC below its switchover threshold for a long period of time, such as a persistent short-circuit, the LTC7810 provides a regulator shutdown timeout to limit excessive power dissipation from the VIN supply. When DRVCC is supplied by the VIN or NDRV LDOs and the part is not in sleep mode, a 10A current source out of the REGSD pin charges an external capacitor. When the voltage on the REGSD pin reaches 1.2V, a regulator timeout fault occurs and switching stops. After a long cool-down delay (approximately 29 times the length of the initial timeout) during which the REGSD pin is cycled between 0.2V and 1.2V, a restart is initiated. When the LTC7810 is in Burst Mode and goes to sleep, or if EXTVCC rises above its switchover voltage, no significant power is being dissipated in the VIN or NDRV LDOs, and the REGSD pin is therefore discharged with a 10A current. Figure 11 shows the REGSD connection. Be sure to select the REGSD timeout to be longer than it takes for the output voltage to reach the EXTVCC switchover threshold during soft-start. This is accomplished by selecting the value of CREGSD to be greater than or equal to the value of the soft-start capacitor for the channel that EXTVCC is tied LTC7810 REGSD CREGSD GND 7810 F11 Figure 11. Using the REGSD Pin to. For low voltage applications where power dissipation from VIN is not significant, the regulator shutdown timer can be disabled by grounding the REGSD pin. The following list summarizes the four possible connections for EXTVCC: 1. EXTVCC grounded. This will cause DRVCC to be powered from the internal VIN or NDRV LDO resulting in an efficiency penalty at high input voltages. If EXTVCC is grounded, the REGSD feature must be defeated by grounding the REGSD pin. 2. EXTVCC connected directly to one of the LTC7810's outputs. This is the normal connection for an application with an output greater than the DRVCC regulation point and provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available, it may be used to power EXTVCC providing it is compatible with the MOSFET gate drive requirements. This supply may be higher or lower than VIN; however, if the NDRV LDO is also used and VIN is lower than DRVCC, keep in mind that the external NMOS has a body diode from DRVCC to VIN, and may require a diode in series with its drain to avoid back-biasing VIN from DRVCC. 4. EXTVCC connected to an output-derived boost or charge pump. For regulators where both of the LTC7810 outputs are low voltage, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than the DRVCC regulation point. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though external diode DB from DRVCC when Rev. A For more information www.analog.com 27 LTC7810 APPLICATIONS INFORMATION the SW pin is low. When one of the topside MOSFETs is to be turned on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply: VBOOST = VIN + VDRVCC. The value of the boost capacitor, CB, needs to be 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of the external diode must be greater than VIN(MAX). The external diode DB can be a Schottky diode or silicon diode, but in either case it should have low-leakage and fast recovery. Pay close attention to the reverse leakage current specification for this diode, especially at high temperatures where it generally increases substantially. The topside MOSFET drivers include internal charge pumps that deliver current to the bootstrap capacitor when the top MOSFET is on continuously, such as when the output is in dropout (100% duty cycle). The diode selected for the boost topside driver should have a reverse leakage less than the available output current the charge pump can supply. Curves displaying the available charge pump current under different operating conditions can be found in the Typical Performance Characteristics section. A leaky diode DB can not only prevent the top MOSFET from fully turning on but it can also create a current path from the BOOST pin to DRVCC. This can cause DRVCC to rise if the diode leakage exceeds the current consumption on DRVCC. This is particularly a concern in Burst Mode operation where the load on DRVCC can be very small. There is an internal voltage clamp on DRVCC that prevents the DRVCC voltage from running away, but this clamp should be regarded as a failsafe only. The external Schottky or silicon diode should be carefully chosen such that DRVCC never gets charged up higher than its normal regulation voltage. Burst Clamp Programming V - 0.4V BURST CLAMP = MODE * 100% 1V (18) where VMODE is the voltage on the MODE pin and burst clamp is the percentage of VSENSE(MAX). The burst clamp level facilitates a trade-off between light load efficiency and light load output voltage ripple. Higher burst clamp levels increase the output voltage ripple due to higher peak inductor currents, but also increase the sleep time between burst pulses which increases efficiency. The MODE pin is high impedance and VMODE can be set by a resistor divider from the INTVCC pin (Figure 12a). As a lower quiescent current alternative, the MODE pin can be connected to either VFB feedback divider by use of a third divider resistor (R3) as shown in Figure 12b to program the burst clamp between 10% and 60% (VMODE = 0.5V to 1V). In the configuration of Figure 12b, when INTVCC LTC7810 R2 MODE 7810 F12a R1 (12a) Using INTVCC to Program the Burst Clamp VOUT R2 VFB LTC7810 R3 MODE 7810 F12b R1 (12b) Using VFB to Program the Burst Clamp Burst Mode operation is enabled if the voltage on the MODE pin is 0V or in the range between 0.5V to 1V. The burst clamp, which sets the minimum peak inductor current, can be programmed by the MODE pin voltage. If 28 the MODE pin is grounded, the burst clamp is set to 25% of the maximum sense voltage (VSENSE(MAX)). A MODE pin voltage between 0.5V and 1V varies the burst clamp linearly between 10% and 60% of VSENSE(MAX) through the following equation: Figure 12. Programming the Adjustable Burst Clamp Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION the output voltage is in regulation, the output voltage and MODE pin voltage are: R2 VOUT = 1V 1+ R1+ R3 (19) R1 VMODE = 1V R1+ R3 returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Fault Conditions: Overtemperature Protection Fault Conditions: Current Limit and Current Foldback The LTC7810 includes current foldback to help limit load current when the output is shorted to ground. If the output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 40% of its maximum selected value. Under short-circuit conditions with very low duty cycles, the LTC7810 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be dissipating most of the power but less than in normal operation. The short-circuit ripple current is determined by the minimum on-time, tON(MIN), of the LTC7810 (90ns), the input voltage and inductor value: V IL(SC) = tON(MIN) IN L (20) The resulting average short-circuit current is: 1 ISC = 40% * I LIM(MAX) - I L(SC) 2 (21) Fault Conditions: Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the controller is operating. A comparator monitors the output for overvoltage conditions. The comparator detects faults greater than 10% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The bottom MOSFET remains on continuously for as long as the overvoltage condition persists; if VOUT At higher temperatures, or in cases where the internal power dissipation causes excessive self-heating on chip, the overtemperature shutdown circuitry will shut down the LTC7810. When the junction temperature exceeds approximately 180C, the overtemperature circuitry disables the DRVCC LDO, causing the DRVCC supply to collapse and effectively shut down the entire LTC7810 chip. When the junction temperature drops back to the approximately 160C, the DRVCC LDO turns back on. Long-term overstress (TJ > 125C) should be avoided as it can degrade the performance or shorten the life of the part. Phase-Locked Loop and Frequency Synchronization The LTC7810 has an internal phase-locked loop (PLL) comprised of a phase frequency detector, a low pass filter, and a voltage-controlled oscillator (VCO). This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the PLLIN/ SPREAD pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. If the external clock frequency is greater than the internal oscillator's frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the VCO input. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the VCO input. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage at the VCO input is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector For more information www.analog.com Rev. A 29 LTC7810 APPLICATIONS INFORMATION output is high impedance and the internal filter capacitor, CLP, holds the voltage at the VCO input. Note that the LTC7810 can only be synchronized to an external clock whose frequency is within range of the LTC7810's internal VCO, which is nominally 50kHz to 750kHz. This is guaranteed to be between 75kHz and 720kHz. Typically, the external clock (on the PLLIN/ SPREAD pin) input high threshold is 1.6V, while the input low threshold is 1.1V. The LTC7810 is guaranteed to synchronize to an external clock that swings up to at least 2.5V and down to 0.5V or less. Rapid phase-locking can be achieved by using the FREQ pin to set a free-running frequency near the desired synchronization frequency. The VCO's input voltage is prebiased at a frequency corresponding to the frequency set by the FREQ pin. Once prebiased, the PLL only needs to adjust the frequency slightly to achieve phase lock and synchronization. Although it is not required that the free running frequency be near the external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the PLL locks. When synchronized to an external clock, the LTC7810 operates in forced continuous mode if the MODE pin is set to Burst Mode operation or forced continuous operation. If the MODE pin is set to pulse-skipping operation, the LTC7810 maintains pulse-skipping operation when synchronized. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the LTC7810 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: V tON(MIN) < OUT VIN (f) (22) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. 30 The minimum on-time for the LTC7810 is approximately 90ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases up to about 130ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC7810 circuits: 1) IC VIN current, 2) DRVCC regulator current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. VIN current typically results in a small (<0.1%) loss. 2. DRVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge, dQ, moves from DRVCC to ground. The resulting dQ/dt is a current out of DRVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. Supplying DRVCC from an output-derived source power through EXTVCC will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 20V to 5V Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION application, 10mA of DRVCC current results in approximately 2.5mA of VIN current. This reduces the mid-current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resistor and input and output capacitor ESR. In continuous mode the average output current flows through L and RSENSE, but is chopped between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L, RSENSE and ESR to obtain I2R losses. For example, if each RDS(ON) = 30m, RL = 50m, RSENSE = 10m and RESR = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. This results in losses ranging from 3% to 13% as the output current increases from 1A to 5A for a 5V output, or a 4% to 20% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. Transition losses apply only to the top MOSFET(s), and become significant only when operating at high input voltages (typically 20V or greater). Transition losses can be estimated from: Transition Loss = 1.7 * VIN2 * IOUT(MAX) * CRSS * f (23) Other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these system level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20F to 40F of capacitance having a maximum of 20m to 50m of ESR. Other losses including conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ILOAD(ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior, but it also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the first page circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be Rev. A For more information www.analog.com 31 LTC7810 APPLICATIONS INFORMATION used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. inductor ripple current can be calculated from the following equation: The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. L= A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise-time should be controlled so that the load rise-time is limited to approximately 25 * CLOAD. Thus a 10F capacitor would require a 250s rise time, limiting the charging current to about 200mA. Design Example As a design example, assume VIN = 48V (nominal), VIN = 140V (max), VOUT = 12V, IOUT(MAX) = 6A, and f = 150kHz. The schematic representing this design example is shown as channel 2 in Figure 14 in the Typical Applications section. 1. Set the operating frequency. Since the input can be high voltage, a low switching frequency is selected to minimize transition losses on the top MOSFET. The operating frequency is not one of the internal preset values of 200kHz or 300kHz, so a resistor from the FREQ pin to GND is required, with a value of: RFREQ = 150kHz 9 + 13.5k = 30.2k (24) 2. Determine the inductor value. Initially select a value based on an inductor ripple current of 30%. The 32 VOUT VOUT 1- = 33H (f)(IL ) VIN(NOM) (25) The highest value of ripple current occurs at the maximum input voltage, in this case, the ripple at VIN = 140V is 37%. 3. Verify that the minimum on-time of 90ns is not violated. The minimum on-time occurs at maximum VIN: tON(MIN) = VOUT VIN(MAX)(f) = 571ns (26) This is more than sufficient to satisfy the minimum on-time requirement. If the minimum on-time were violated, either the frequency could be decreased (with inductor value accordingly adjusted) or the OVLO pin could be used to limit the maximum input voltage where switching occurs. 4. Select the RSENSE resistor value. The peak inductor current is the maximum DC output current plus half of the inductor ripple current. Or (6A)(1 + 0.30/2) = 6.9A in this case. The RSENSE resistor value can then be calculated based on the minimum value for the maximum current sense threshold (67mV): R SENSE 67mV 6.9A 10m (27) 5. Select the feedback resistors. If very light load efficiency is required, high value feedback resistors may be used to minimize the current due to the feedback divider. However, in most applications a feedback divider current in the range of 10A to 100A or more is acceptable. For a 50A feedback divider current, RA = 1V/50A = 20k. RB can then be calculated as: RB = RA (12V - 1V) = 220k (28) 6. Select the MOSFETs. The best way to evaluate MOSFET performance in a particular application is to build and test the circuit on the bench which is facilitated by an LTC7810 demo board. However, an educated guess about the application is helpful to initially select Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION MOSFETs. Since this is a high input voltage application, transition losses will likely dominate the power loss in the top MOSFET. Therefore, choose a MOSFET with low gate charge to minimize this loss term, such as an Infineon BSC520N15NS3G which has low gate charge, a VDS rating of 150V, RDS(ON) of 52m, and a maximum drain current of 21A. Due to the high transition losses that occur with a 140V input voltage, two MOSFETs may needed in parallel to more evenly balance the dissipated power and to lower the RDS(ON). The bottom MOSFET does not experience transition losses, and its power loss is generally dominated by I2R losses. For this reason, the bottom MOSFET is typically chosen to be of lower RDS(ON) and subsequently higher gate charge than the top MOSFET. For this example, an Infineon BSC093N15NS5 is chosen with an RDS(ON) of just 9m. The DRVSET pin for these MOSFETs should be configured for either 8V or 10V to avoid the "knee" in the MOSFET ID vs VGS curve. Losses due to the gate charge required to turn on the MOSFETs may be greater with DRVCC set to 10V, but I2R losses may decrease; therefore, both configurations of the DRVSET pin should be attempted in the lab to determine the most efficient operating point. 7. Select the input and output capacitors. CIN is chosen for an RMS current rating of at least 4A (IOUT/2, with margin) at temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02 for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR *IL = 0.02 *1.8A = 36mVP-P (29) On the 12V output, this is equal to 0.30% of peak to peak voltage ripple. 8. Determine the bias supply components. Since the regulated output is greater than the DRVCC regulation point, tie EXTVCC to VOUT to supply the gate drive current from the output. For a 10ms soft start, select a 0.1F capacitor for the TRACK/SS pin. Select a 0.33F capacitor for the REGSD pin for a 40ms REGSD timeout, which is longer than the soft-start time to ensure that the output has an opportunity to start up before the regulator shutdown timer expires. As a first pass estimate for the bias components, select CDRVCC = 4.7F, CINTVCC = 0.1F, boost supply capacitor CB = 0.1F and low leakage boost supply diode CMPD3003A from Central Semiconductor. 9. Determine and set application-specific parameters. Set the MODE pin based on the trade-off of light load efficiency and constant frequency operation. Set the PLLIN/SPREAD pin based on whether a fixed, spread spectrum, or phase-locked frequency is desired. The RUN and OVLO pins can be used to control the input voltage window within which the regulator operates. Use ITH compensation components from the typical applications as a first guess, check the transient response for stability, and modify as necessary. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. Figure 13 illustrates the current waveforms present in the various branches of the two-phase synchronous buck regulators operating in the continuous mode. Check the following in your layout: 1. Are the top N-channel MOSFETs MTOP1 and MTOP2 located within 1cm of each other with a common drain connection at CIN? Do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CDRVCC must return to the combined COUT (-) terminals. The path formed by the top N-channel MOSFET, bottom N-channel MOSFET and the CIN capacitor should have short leads and PC trace lengths. The output capacitor (-) terminals should be connected as close as possible to the (-) terminals of the input capacitor by placing the capacitors next to each other and away from the loop described above. Rev. A For more information www.analog.com 33 LTC7810 APPLICATIONS INFORMATION 3. Does the LTC7810's VFB pin's resistive divider connect to the (+) terminal of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 4. Are the SENSE- and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE+ and SENSE- should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor. 5. Is the DRVCC and decoupling capacitor connected close to the IC, between the DRVCC and the ground pin? This capacitor carries the MOSFET drivers' current peaks. SW1 6. Keep the switching nodes (SW1, SW2), top gate (TG1, TG2), and boost nodes (BOOST1, BOOST2) away from sensitive small-signal nodes, especially from the opposite channel's voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC7810 and occupy minimum PC trace area. 7. Use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the DRVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the GND pin of the IC. L1 RSENSE1 VOUT1 COUT1 RL1 VIN RIN CIN SW2 L2 RSENSE2 VOUT2 COUT2 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. RL2 7810 F13 Figure 13. Branch Current Waveforms 34 Rev. A For more information www.analog.com LTC7810 APPLICATIONS INFORMATION PC Board Layout Debugging Start with one controller at a time. It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold - typically 25% of the maximum designed current level in Burst Mode operation. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after each controller is checked for its individual performance should both controllers be turned on at the same time. A particularly difficult region of operation is when one channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. Reduce VIN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST, SW, TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, the top MOSFET, and the bottom MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor--don't worry, the regulator will still maintain control of the output voltage. Rev. A For more information www.analog.com 35 LTC7810 TYPICAL APPLICATIONS DRVCC VIN 8V TO 140V* 0.47F x4 100F D1 RUN1 VIN RUN2 BOOST1 TG1 MTOP1 L1 6.8H DRVCC 4.7F D2 BOOST2 TG2 MTOP2 0.1F 0.1F SW1 L2 33H SW2 LTC7810 MBOT1 BG1 10 VOUT1 3.3V/10A 22F MBOT2 10 SENSE1+ SENSE2+ SENSE1- SENSE2- EXTVCC NDRV 1nF 6m COUT1 330F 6.3V BG2 PGND 1nF 10pF 2.3M VFB1 ITH1 TRACK/SS1 1M 1.69k 4.7nF 30.2k 0.1F 22pF OVLO DRVCC 10pF 2.2M VFB2 ITH2 TRACK/SS2 FREQ PLLIN/SPREAD INTVCC 0.1F 10m SGND VOUT2 12V*/6A COUT2 150F 16V 10F 200k DRVSET 2.2k 0.1F REGSD 22pF MODE 0.33F 2.2nF 7810 F14a fSW = 150kHz, SPREAD SPECTRUM * VOUT2, FOLLOWS VIN WHEN VIN IS LESS THAN THE REGULATION POINT MTOP1,2, MBOT2: INFINEON BSC520N15NS3G MBOT1: INFINEON BSC190N15NS3G D1,2: CENTRAL SEMI CMHD3595 L1: COILCRAFT SER2915L-682KL L2: WURTH 7443633300 COUT1: KEMET T520V337M006ATE025 COUT2: KEMET T521D157M016ATE050 (14a) No-Load Input Current vs Input Voltage Efficiency vs Load Current 90 140 VOUT = 3.3V 85 EFFICIENCY (%) 80 75 70 65 60 55 VIN = 24V VIN = 48V VIN = 100V VIN = 140V 50 45 40 0.001 0.01 0.1 1 LOAD CURRENT (A) 10 7810 F14b (14b) NO-LOAD INPUT CURRENT (uA) 95 Short Circuit Response BOTH CHANNELS ON CHANNEL 1 ONLY, REGSD=GND CHANNEL 2 ONLY 120 VOUT2 5V/DIV 100 80 INDUCTOR CURRENT 3A/DIV 60 40 200s/DIV 20 0 0 20 40 60 80 100 VIN INPUT VOLTAGE (V) 120 7810 F14d 140 7810 F14c (14c) (14d) Figure 14. High Efficiency Dual 3.3V/12V Step-Down Regulator with Spread Spectrum 36 Rev. A For more information www.analog.com LTC7810 TYPICAL APPLICATIONS LIMITED TO 32V MAX VIN UNREGULATED 12V OR 24V SUPPLY SURGE TO 140V DRVCC 0.47F x4 100F L2 4.7H VIN RUN1 RUN2 EXTVCC BOOST1 TG1 0.1F MBOT1 SENSE2+ SENSE1+ SENSE2- SENSE1- 1nF 1nF 6m 10pF 10pF VFB1 OVLO ITH1 TRACK/SS1 1M 31.5k BG1 PGND 10m 0.1F 100k L1 1H SW1 LTC7810 BG2 100 3.3F MTOP1 0.1F SW2 3.1M 10F VOUT2 32V* 6A D1 BOOST2 TG2 MBOT2 1M DRVCC D2 MTOP2 COUT2 82F 50V FREQ 10k 82.5k 47pF 1.8nF 0.1F INTVCC REGSD VOUT1 3.3V/10A 460k ITH2 TRACK/SS2 NDRV DRVCC DRVSET PLLIN/SPREAD SGND COUT1 680F 6.3V 33F VFB2 200k DRVCC 1.33k 0.1F MODE 680pF 4.7F 22pF 7810 F15a fSW = 600kHz MTOP1: VISHAY SILICONIX SI7848DP MBOT1: VISHAY SILICONIX SIR418DP MTOP2, MBOT2: INFINEON BSC093N15NS5 D1,2: CENTRAL SEMI CMPD3003 L1: COILCRAFT XAL6030-102ME L2: COILCRAFT XAL6060-472ME COUT1: KEMET T520X687M006ATE025 COUT2: SUN ELECTRONIC 50HVH82M *VOUT2 FOLLOWS VIN WHEN VIN < 32V OVLO LIMITS SWITCHING TIME WHEN VIN > 40V (15a) Switching Time Limit vs Input Voltage Surge Surge Transient Response Surge Transient Response 9 VIN = 12V BEFORE SURGE VIN = 24V BEFORE SURGE 8 VIN 10V/DIV VIN 30V/DIV VIN TRANSIENT SWITCHING TIME LIMIT (SEC) 12V TO 140V VIN TRANSIENT VOUT2 10V/DIV VOUT2 LIMITED TO 32V VOUT2 30V/DIV VOUT2 LIMITED TO 32V 80ms/DIV (15b) 7810 F15b 100s/DIV 7810 F15c 7 6 5 4 3 2 1 0 40 60 80 100 120 VIN SURGE VOLTAGE (V) (15c) 140 7810 F15d (15d) Figure 15. Small Size High Efficiency Switching Surge Stopper and 3.3V/10A Regulator Rev. A For more information www.analog.com 37 LTC7810 TYPICAL APPLICATIONS DRVCC1 VIN 18V TO 60V (48V NOMINAL) CIN2 4.7F x6 CIN1 47F DRVCC1 BOOST1 TG1 RUN1 RUN2 DRVCC NDRV VIN D1 VIN SW1 LTC7810 4.7F MTOP1 x2 L1 6.8H 0.1F MBOT1 x2 BG1 PGND 10 SENSE1+ INTVCC1 1nF VFB2 MODE DRVSET INTVCC 1nF 0.1F SENSE2+ VFB1 CLK1 SS ITH 100pF 3.74k 10nF INTVCC1 V+ 0.1F 442k OUT1 LTC6908-2 GND OUT2 SET MOD CLK1 42.2k 3m SENSE1- EXTVCC SENSE2- PLLIN/SPREAD TRACK/SS1 ITH1 FREQ REGSD ITH2 TRACK/SS2 OVLO SGND DRVCC1 VIN D2 BOOST2 TG2 0.1F SW2 3m 10 110k COUT1 22F x6 COUT2 330F x2 10k MTOP2 x2 L2 6.8H MBOT2 x2 BG2 VOUT 12V/ 75A DRVCC2 VIN CLK2 CIN4 4.7F x6 CIN3 47F DRVCC2 VIN RUN1 RUN2 DRVCC NDRV BOOST1 TG1 LTC7810 MTOP3 x2 L3 6.8H 0.1F SW1 4.7F VIN D3 MBOT3 x2 BG1 PGND 10 SENSE1+ INTVCC2 VFB2 MODE DRVSET INTVCC 0.1F SENSE2+ VFB1 CLK2 TRACK/SS1 ITH 0.1F 100pF 42.2k 3m 1nF 3m ITH1 FREQ REGSD ITH2 TRACK/SS2 OVLO SGND 10 110k COUT3 22F x6 COUT4 330F x2 DRVCC2 D4 PLLIN/SPREAD SS 1nF SENSE1- EXTVCC SENSE2- BOOST2 TG2 SW2 BG2 7810 F16 VIN 10k MTOP4 x2 L4 0.1F 6.8H MBOT4 x2 fSW = 225kHz MTOP1,2,3,4: INFINEON BSC340N08NS3 MBOT1,2,3,4: INFINEON BSC042NE7NS3 D1,2,3,4: CENTRAL SEMI CMDP3003 L1,2,3,4: COILCRAFT SER2918H-682KL CIN1,CIN3: SUN 100CE47LX CIN2,CIN4: TDK CGA6M3X7S2A475M200AB COUT1,COUT3: MURATA GRM32ER71E226ME15L COUT2,COUT4: SUN 25HVH330M Figure 16. High Efficiency Four Phase Single Output 12V/75A (900W) Step-Down Regulator 38 Rev. A For more information www.analog.com LTC7810 TYPICAL APPLICATIONS DRVCC VIN 120V NOMINAL 8V TO 140V* D1 10F 100F RUN1 VIN RUN2 BOOST1 TG1 MTOP1 L1 10H SW1 BOOST2 TG2 BG2 SENSE1+ SENSE2+ SENSE1- SENSE2- 50 1nF 1nF EXTVCC 1M NDRV 22pF VFB1 ITH1 TRACK/SS1 0.1F 12k 90.9k 33pF L2 22H MBOT2 PGND 5m COUT1 330F 16V MTOP2 SW2 LTC7810 BG1 10 22F 4.7F D2 0.1F 0.1F MBOT1 VOUT1 12V* 10A DRVCC 0.1F DRVCC 10pF 230k VFB2 ITH2 TRACK/SS2 INTVCC FREQ PLLIN/SPREAD OVLO SGND 1.5nF 8m DRVSET REGSD 6.2k 0.1F COUT2 56F 50V VOUT2 24V* 6A 10F 10k 33pF 6.8nF 0.33F MODE 7810 F17a fSW = 300kHz * VOUT1, VOUT2 FOLLOW VIN WHEN VIN IS LESS THAN THE REGULATION POINT MTOP1,2: INFINEON BSC520N15NS3G MBOT1,2: INFINEON BSC360N15NS3G D1,2: CENTRAL SEMI CMPD3003 L1: VISHAY IHLP6767GZER100M11 L2: VISHAY IHLP6767GZER220M11 COUT1: KEMET T521X337MO16ATE025 COUT2: SUN ELECTRONIC 50HVH56M (17a) Efficiency and Power Loss vs Load Current VOUT = 12V 95 EFFICIENCY 100 10 80 75 1 70 POWER LOSS 65 60 VIN = 48V VIN = 96V VIN = 140V 55 0.01 0.1 1 LOAD CURRENT (A) 10 EFFICIENCY 0.1 85 10 80 75 1 70 POWER LOSS 65 60 VIN = 48V VIN = 96V VIN = 140V 55 0.01 50 0.001 0.01 0.1 1 LOAD CURRENT (A) 7810 F17b (17b) 95 100 10 POWER LOSS (W) 85 VOUT = 24V Efficiency vs Input Voltage 100 1k 90 POWER LOSS (W) EFFICIENCY (%) 90 50 0.001 100 0.1 0.01 90 EFFICIENCY (%) 95 1k EFFICIENCY (%) 100 Efficiency and Power Loss vs Load Current 85 80 75 VOUT = 12V, ILOAD = 100mA VOUT = 12V, ILOAD = 5A VOUT = 24V, ILOAD = 100mA VOUT = 24V, ILOAD = 3A 70 65 15 40 65 90 115 INPUT VOLTAGE (V) 7810 F17d 7810 F17c (17c) 140 (17d) Figure 17. High Efficiency High Voltage Dual 24V/12V Step-Down Regulator Rev. A For more information www.analog.com 39 LTC7810 PACKAGE DESCRIPTION LXE Package 48-Lead Plastic Exposed Pad LQFP (7mm x 7mm) (Reference LTC DWG #05-08-1832 Rev E) Exposed Pad Variation BB 9.00 BSC 7.00 BSC 3.60 0.10 48 37 SEE NOTE: 3 1 48 37 36 36 1 9.00 BSC 7.00 BSC 3.60 0.10 A A 12 25 25 12 C0.30 - 0.50 13 24 13 BOTTOM OF PACKAGE--EXPOSED PAD (SHADED AREA) 24 11 - 13 R0.08 - 0.20 1.60 1.35 - 1.45 MAX GAUGE PLANE 0.25 0 - 7 LXE48 LQFP 0318 REV E 11 - 13 0.09 - 0.20 1.00 REF 0.50 BSC 0.17 - 0.27 0.05 - 0.15 SIDE VIEW 0.45 - 0.75 SECTION A - A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION 4. DRAWING IS NOT TO SCALE 7.15 - 7.25 5.50 REF 1 48 37 36 0.50 BSC 5.50 REF 7.15 - 7.25 0.20 - 0.30 3.60 0.05 12 13 PACKAGE OUTLINE 24 25 COMPONENT PIN "A1" XXYY LTCXXXX 3.60 0.05 1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 40 TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION Rev. A For more information www.analog.com LTC7810 REVISION HISTORY REV DATE DESCRIPTION A 04/19 Corrected Figure 9 and Figure 16 schematics PAGE NUMBER 25, 37 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 41 LTC7810 TYPICAL APPLICATION DRVCC VIN 8V TO 140V 100F 10F VIN BOOST1 TG1 RUN2 NDRV DRVCC MTOP1 x2 L1 10H 0.1F SW1 DRVCC 4.7F VIN D1 RUN1 MBOT1 x2 BG1 LTC7810 PGND SENSE1+ VFB2 MODE INTVCC 1nF 0.1F ITH1 0.33F 0.1F 110k SENSE2+ VFB1 47pF 10nF 3m 1nF DRVSET 3.83k 3m SENSE1- EXTVCC SENSE2- REGSD TRACK/SS1 FREQ ITH2 TRACK/SS2 PLLIN/SPREAD OVLO SGND DRVCC D2 BOOST2 TG2 0.1F VIN MTOP2 x2 10pF VOUT 12V*/30A COUT 330F x2 10F x4 10k L2 10H SW2 MBOT2 x2 BG2 7810 F18 fSW = 200kHz *VOUT FOLLOWS VIN WHEN VIN < 12V MTOP1, MTOP2: INFINEON BSC190N15NS3 MBOT1, MBOT2: INFINEON BSC190N15NS3 COUT: KEMET T521X337M016ATE025 D1, D2: DIODES INC DFLS1150 L1, L2: COILCRAFT XAL1510-103 Figure 18. High Efficiency 360W Two Phase Single Output 12V Step-Down Regulator RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC7801/ LTC3895 150V Low IQ, Synchronous Step-Down DC/DC Controller with 100% Duty Cycle 4V VIN 140V, 150V Absolute Maximum, PLL Fixed Frequency 50kHz to 900kHz, 0.8V VOUT 60V, Adjustable 5V to 10V Gate Drive, IQ = 40A, 4mm x 5mm QFN-24, TSSOP-24, TSSOP-38(31) LTC7103 105V, 2.3A Low EMI Synchronous Step-Down Regulator 4.4V VIN 105V, 1V VOUT VIN, IQ = 2A Fixed Frequency 200kHz to 2MHz, 5mm x 6mm QFN LTC3638 High Efficiency, 140V 250mA Step-Down Regulator Integrated Power MOSFETs, 4V VIN 140V, 0.8V VOUT VIN, IQ = 12A, MSOP-16(12) LTC3896 150V Low IQ, Synchronous Inverting DC/DC Controller with Ground-Referenced Control/Interface Pins 4V VIN 140V, 150V Absolute Maximum, PLL Fixed Frequency 50kHz to 900kHz, -0.8V VOUT -60V, Adjustable 5V to 10V Gate Drive, IQ = 40A LTC3892/ LTC3892-1 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller with 99% Duty Cycle 4V VIN 60V, PLL Fixed Frequency 50kHz to 900kHz, 0.8V VOUT 0.99VIN, Adjustable 5V to 10V Gate Drive, IQ = 29A LTC3639 High Efficiency, 150V 100mA Synchronous Step-Down Integrated Power MOSFETs, 4V VIN 150V, 0.8V VOUT VIN, IQ = 12A, Regulator MSOP-16(12) LT8631 100V, 1A Synchronous Micropower Step-Down Regulator Integrated Power MOSFETs, 3V VIN 100V, 0.8V VOUT 60V, IQ = 7A, TSSOP-20 LTC7138 High Efficiency, 140V 400mA Step-Down Regulator Integrated Power MOSFETs, 4V VIN 140V, 0.8V VOUT VIN, IQ = 12A, MSOP-16(12) LTC3899 60V Triple Output, Buck/Buck/Boost Synchronous Controller with 30A Burst Mode IQ 4.5V (Down to 2.2V After Start-Up) VIN 60V, Buck VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V LTC7860 High Efficiency Switching Surge Stopper 3.5V VIN 60V, Expandable to 200V+, Adjustable VOUT Clamp and Current Limit, Power Inductor Improves EMI, MSOP-12 42 Rev. A 04/19 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2018-2019