100336 Low Power 4-Stage Counter/Shift Register General Description The 100336 operates as either a modulo-16 up/down counter or as a 4-bit bidirectional shift register. Three Select (Sn) inputs determine the mode of operation, as shown in the Function Select table. Two Count Enable (CEP, CET) inputs are provided for ease of cascading in multistage counters. One Count Enable (CET) input also doubles as a Serial Data (D0) input for shift-up operation. For shift-down operation, D3 is the Serial Data input. In counting operations the Terminal Count (TC) output goes LOW when the counter reaches 15 in the count/up mode or 0 (zero) in the count/down mode. In the shift modes, the TC output repeats the Q3 output. The dual nature of this TC/Q3 output and the D0/ CET input means that one interconnection from one stage to the next higher stage serves as the link for multistage counting or shift-up operation. The individual Preset (Pn) inputs are used to enter data in parallel or to preset the coun- ter in programmable counter applications. A HIGH signal on the Master Reset (MR) input overrides all other inputs and asynchronously clears the flip-flops. In addition, a synchronous clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have 50 kX pull-down resistors. Features Y Y Y Y Y Y 40% power reduction of the 100136 2000V ESD protection Pin/function compatible with 100136 Voltage compensated operating range e b 4.2V to b 5.7V Available to industrial grade temperature range Available to MIL-STD-883 Logic Symbol Pin Names CP CEP D0/CET TL/F/10584 - 1 S0 -S2 MR P0 -P3 D3 TC Q0 -Q3 Q0 -Q3 Description Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs Connection Diagrams 24-Pin DIP/SOIC 28-Pin PCC 24-Pin Quad Cerpak TL/F/10584 - 3 TL/F/10584-2 C1995 National Semiconductor Corporation TL/F/10584 TL/F/10584 - 4 RRD-B30M105/Printed in U. S. A. 100336 Low Power 4-Stage Counter/Shift Register July 1992 Logic Diagram TL/F/10584 - 5 2 Function Select Table S2 S1 S0 Function L L L L H H H H L L H H L L H H L H L H L H L H Parallel Load Complement Shift Left Shift Right Count Down Clear Count Up Hold Truth Table Q0 e LSB Inputs MR S2 S1 L L L L L Outputs S0 CEP D0/CET D3 CP L L X X X L P3 P2 L H X X X L Q3 Q2 L H L X X X L D3 Q3 L L H H X X X L Q2 Q1 L H L L L L X L L L H H L L L L H X L H X X X X Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 L H L H X X X L L L L L L H H L L L X L L L H H H H L L H X L H X X X X Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 L H H H X X X X Q3 Q2 Q1 H H H H H H H H H L L L L H H H H H L L H H L L L H H L H L H L L H L H X X X X X X X X X X X X X L H X X X X X X X X X X X X X X X X X X X X X L L L L L L L L L L L L L L L L L L L L L L L L L L L j e i i Le LOW Voltage Level Xe Don't Care TC Mode P1 P0 L Preset (Parallel Load) Q1 Q0 L Invert Q2 Q1 D3 Shift to LSB Q0 D0 Q3* Shift to MSB j Count Down j H Count Down with CEP not active Count Down with CET not active H Clear k Count Up k H Count Up with CEP not active Count Up with CET not active Q0 H Hold L L L L L L L L L L L L L L H H H H Asynchronous Master Reset After the clock, TC is Q2 HHHH HIGH Voltage Level Q0 *Before the clock, TC is Q3 L if Q0 -Q3 e HHHH H if Q0 -Q3 Q1 (Q0- 3) plus 1 LLLL He Q2 (Q0- 3) minus 1 L if Q0 -Q3 e LLLL H if Q0 -Q3 k e Q3 L e LOW-to-HIGH Transition 3 Absolute Maximum Ratings Recommended Operating Conditions Above which the useful life may be impaired. (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 65 C to a 150 C Storage Temperature (TSTG) Maximum Junction Temperature (TJ) Ceramic Plastic VEE Pin Potential to Ground Pin Input Voltage (DC) Output Current (DC Output HIGH) ESD (Note 2) Case Temperature (TC) Commercial Industrial Military 0 C to a 85 C b 40 C to a 85 C b 55 C to a 125 C Supply Voltage (VEE) a 175 C a 150 C b 5.7V to b 4.2V b 7.0V to a 0.5V VEE to a 0.5V b 50 mA t 2000V Note 1: Absolute maximum ratings are those values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e 0 C to a 85 C (Note 3) Symbol Parameter Min Typ Max Units VOH Output HIGH Voltage b 1025 b 955 b 870 mV VOL Output LOW Voltage b 1830 b 1705 b 1620 mV VOHC Output HIGH Voltage b 1035 VOLC Output LOW Voltage b 1610 mV VIH Input HIGH Voltage b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current mV 0.50 mA 240 b 165 b 80 mA Conditions VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V VIN e VIH(Min) or VIL (Max) Loading with 50X to b2.0V VIN e VIL (Min) VIN e VIH (Max) Inputs Open Note 3: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 4 Commercial Version (Continued) DIP AC Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e 0 C Min Max TC e a 25 C TC e a 85 C Min Min Max Conditions MHz Figures 2 and 3 fshift Shift Frequency 300 tPLH tPHL Propagation Delay CP to Qn, Qn 1.00 2.00 1.00 2.00 1.00 2.00 ns Figures 1 and 3 (Note 1) tPLH tPHL Propagation Delay CP to TC (Shift) 2.10 3.50 2.10 3.50 2.10 3.70 ns Figures 1, 7, 8 (Note 1) tPLH tPHL Propagation Delay CP to TC (Count) 2.40 4.40 2.40 4.40 2.60 4.70 ns Figures 1 and 9 (Note 1) tPLH tPHL Propagation Delay MR to Qn, Qn 1.40 2.50 1.40 2.50 1.50 2.60 ns Figures 1 and 4 (Note 1) tPLH tPHL Propagation Delay MR to TC (Count) 2.80 5.10 2.90 5.20 3.10 5.50 ns Figures 1, 12 (Note 1) tPHL Propagation Delay MR to TC (Shift) 2.40 4.00 2.40 4.00 2.50 4.10 ns Figures 1, 10, 11 (Note 1) tPLH tPHL Propagation Delay D0/CET to TC 1.80 3.10 1.80 3.10 1.90 3.30 ns tPLH tPHL Propagation Delay Sn to TC 1.90 4.10 1.90 4.10 2.10 4.40 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1 and 3 tS Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) 1.00 1.50 1.30 1.40 3.40 2.60 1.00 1.50 1.30 1.40 3.40 2.60 1.00 1.50 1.30 1.40 3.40 2.60 ns Figures 6 and 4 Hold Time D3 Pn D0/CET CEP Sn 0.40 0.30 0.30 0.20 0.10 0.40 0.30 0.30 0.20 0.10 0.40 0.30 0.30 0.20 0.10 ns Figure 6 2.00 2.00 2.00 ns Figures 3 and 4 tH tpw(H) Pulse Width HIGH CP, MR 300 Units Max 300 Note 1: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 5 Figures 1 and 5 (Note 1) Commercial Version (Continued) SOIC, PCC and Cerpak AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e 0 C Min Max TC e a 25 C Min Max Units Conditions MHz Figures 2 and 3 Max fshift Shift Frequency 350 tPLH tPHL Propagation Delay CP to Qn, Qn 1.00 1.80 1.00 1.80 1.00 1.80 ns Figures 1 and 2 (Note 2) tPLH tPHL Propagation Delay CP to TC (Shift) 2.10 3.30 2.10 3.30 2.10 3.50 ns Figures 1, 7, 8 (Note 2) tPLH tPHL Propagation Delay CP to TC (Count) 2.40 4.20 2.40 4.20 2.60 4.50 ns Figures 1 and 9 (Note 2) tPLH tPHL Propagation Delay MR to Qn, Qn 1.40 2.30 1.40 2.30 1.50 2.40 ns Figures 1 and 4 (Note 2) tPLH tPHL Propagation Delay MR to TC (Count) 2.80 4.90 2.90 5.00 3.10 5.30 ns Figures 1 and 12 (Note 2) tPHL Propagation Delay MR to TC (Shift) 2.40 3.80 2.40 3.80 2.50 3.90 ns Figures 1, 10, 11 (Note 2) tPLH tPHL Propagation Delay D0/CET to TC 1.80 2.90 1.80 2.90 1.90 3.10 ns tPLH tPHL Propagation Delay Sn to TC 1.90 3.90 1.90 3.90 2.10 4.20 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.35 1.10 0.35 1.10 0.35 1.10 ns Figures 1 and 3 tS Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) 0.90 1.40 1.20 1.30 3.30 2.50 0.90 1.40 1.20 1.30 3.30 2.50 0.90 1.40 1.20 1.30 3.30 2.50 ns Figures 4 and 6 Hold Time D3 Pn D0/CET CEP Sn 0.30 0.20 0.20 0.10 0.00 0.30 0.20 0.20 0.10 0.00 0.30 0.20 0.20 0.10 0.00 ns Figure 6 2.00 2.00 2.00 ns Figures 3 and 4 tH 350 TC e a 85 C Min 350 Figures 1 and 5 (Note 2) tpw(H) Pulse Width HIGH CP, MR tOSHL Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path 200 200 200 ps PCC Only (Note 1) Maximum Skew Common Edge Output-to-Output Variation Clock to Output Path 200 200 200 ps PCC Only (Note 1) Maximum Skew Opposite Edge Output-to-Output Variation Clock to Output Path 230 230 230 ps PCC Only (Note 1) Maximum Skew Pin (Signal) Transition Variation Clock to Output Path 245 245 245 ps PCC Only (Note 1) tOSLH tOST tps Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tps guaranteed by design Note 2: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 6 Industrial Version PCC DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b40 C to a 85 C (Note 1) Symbol Parameter TC e b40 C Min TC e 0 C to a 85 C Max Min Max Units VOH Output HIGH Voltage b 1085 b 870 b 1025 b 870 mV VOL Output LOW Voltage b 1830 b 1575 b 1830 b 1620 mV VOHC Output HIGH Voltage b 1095 VOLC Output LOW Voltage b 1610 mV VIH Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current IEE Power Supply Current b 1035 b 1565 mV Conditions VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V VIN e VIH(Min) or VIL (Max) Loading with 50X to b2.0V b 1170 b 870 b 1165 b 870 mV Guaranteed HIGH Signal for All Inputs b 1830 b 1480 b 1830 b 1475 mV Guaranteed LOW Signal for All Inputs mA VIN e VIL (Min) 240 mA VIN e VIH (Max) b 80 mA Inputs Open 0.50 0.50 240 b 165 b 75 b 165 Note 1: The specified limits represent the ``worst case'' value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under ``worst case'' conditions. 7 Industrial Version (Continued) PCC AC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b40 C TC e a 25 C TC e a 85 C Min Min Min Max Max Conditions MHz Figures 2 and 3 fshift Shift Frequency 325 tPLH tPHL Propagation Delay CP to Qn, Qn 1.00 1.80 1.00 1.80 1.00 1.80 ns Figures 1 and 3 (Note 1) tPLH tPHL Propagation Delay CP to TC (Shift) 2.00 3.30 2.10 3.30 2.10 3.50 ns Figures 1, 7, 8 (Note 1) tPLH tPHL Propagation Delay CP to TC (Count) 2.40 4.20 2.40 4.20 2.60 4.50 ns Figures 1 and 9 (Note 1) tPLH tPHL Propagation Delay MR to Qn, Qn 1.40 2.30 1.40 2.30 1.50 2.40 ns Figures 1 and 4 (Note 1) tPLH tPHL Propagation Delay MR to TC (Count) 2.80 4.90 2.90 5.00 3.10 5.30 ns Figures 1 and 12 (Note 1) tPHL Propagation Delay MR to TC (Shift) 2.40 3.80 2.40 3.80 2.50 3.90 ns Figures 1, 10, 11 (Note 1) tPLH tPHL Propagation Delay D0/CET to TC 1.70 2.90 1.80 2.90 1.90 3.10 ns tPLH tPHL Propagation Delay Sn to TC 1.80 3.90 1.90 3.90 2.10 4.20 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.20 1.90 0.35 1.10 0.35 1.10 ns Figures 1 and 3 ts Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) 1.40 1.70 1.80 1.80 3.30 2.60 0.90 1.40 1.20 1.30 3.30 2.50 0.90 1.40 1.20 1.30 3.30 2.50 ns Figure 6 Hold Time D3 Pn D0/CET CEP Sn 0.90 1.00 0.70 0.60 0.00 0.30 0.20 0.20 0.10 0.00 0.30 0.20 0.20 0.10 0.00 ns Figure 6 2.20 2.00 2.00 ns Figures 3 and 4 th tpw(H) Pulse Width HIGH CP, MR 350 Units Max 350 Note 1: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 8 Figures 1 and 5 (Note 1) Military Version DC Electrical Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND, TC e b55 C to a 125 C Symbol VOH VOL VOHC VOLC Parameter Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Input HIGH Voltage VIL Input LOW Voltage IIL Input LOW Current IIH Input HIGH Current Max Units TC b 1025 b 870 mV 0 C to a 125 C b 1085 b 870 mV b 55 C b 1830 b 1620 mV 0 C to a 125 C b 1830 b 1555 mV b 55 C Conditions Notes VIN e VIH (Max) or VIL (Min) Loading with 50X to b2.0V 1, 2, 3 VIN e VIH (Min) or VIL (Max) Loading with 50X to b2.0V 1, 2, 3 0 C to b 1035 mV b 1085 mV b 55 C b 1610 mV 0 C to a 125 C b 1555 mV b 55 C Guaranteed HIGH Signal for All Inputs 1, 2, 3, 4 1, 2, 3, 4 Output LOW Voltage VIH IEE Min a 125 C b 1165 b 870 mV b 55 C to a 125 C b 1830 b 1475 mV b 55 C to a 125 C Guaranteed LOW Signal for All Inputs mA b 55 C to a 125 C VEE e b4.2V VIN e VIL (Min) 1, 2, 3 VEE e b5.7V VIN e VIH(Max) 1, 2, 3 Inputs Open VEE e b4.2V to b4.8V VEE e b4.2V to b5.7V 1, 2, 3 0.50 240 mA 340 mA Power Supply Current 0 C to a 125 C b 55 C b 55 C b 185 b 195 b 70 b 70 mA to a 125 C Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold temperatures. Note 2: Screen tested 100% on each device at b 55 C, a 25 C, and a 125 C, Subgroups 1, 2, 3, 7, and 8. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b 55 C, a 25 C, a 125 C, Subgroups A1, 2, 3, 7, and 8. Note 4: Guaranteed by applying specified input conditon and testing VOH/VOL. 9 Military Version (Continued) AC Characteristics VEE e b4.2V to b5.7V, VCC e VCCA e GND Symbol Parameter TC e b55 C TC e a 25 C TC e a 125 Min Min Min Max Max Conditions Notes MHz Figures 2 and 3 fshift Shift Frequency 325 tPLH tPHL Propagation Delay CP to Qn, Qn 0.40 tPLH tPHL Propagation Delay CP to TC (Shift) 1.30 3.90 1.70 3.80 1.70 4.20 ns Figures 1, 7, 8 tPLH tPHL Propagation Delay CP to TC (Count) 1.20 4.60 1.50 4.60 1.60 5.20 ns Figures 1 and 9 tPLH tPHL Propagation Delay MR to Qn, Qn 0.60 2.90 0.80 2.80 0.90 3.20 ns Figures 1 and 4 tPLH tPHL Propagation Delay MR to TC (Count) 2.30 5.20 2.70 5.20 2.90 5.90 ns Figures 1, 12 tPHL Propagation Delay MR to TC (Shift) 2.10 4.30 2.20 4.10 2.40 4.70 ns Figures 1, 10, 11 1, 2, 3, 5 tPLH tPHL Propagation Delay D0/CET to TC 0.70 3.20 1.00 3.20 1.30 4.10 ns tPLH tPHL Propagation Delay Sn to TC 1.30 4.10 1.50 4.20 1.70 4.90 ns tTLH tTHL Transition Time 20% to 80%, 80% to 20% 0.20 1.90 0.20 1.80 0.20 2.00 ts Setup Time D3 Pn D0/CET CEP Sn MR (Release Time) 1.40 1.70 1.80 1.80 3.30 2.60 1.40 1.70 1.80 1.80 3.30 2.60 1.40 1.70 1.80 1.80 3.30 2.60 Hold Time D3 Pn D0/CET CEP Sn 0.90 1.00 0.70 0.60 0.00 0.90 1.00 0.70 0.60 0.00 0.90 1.00 0.70 0.60 0.00 1.60 2.00 1.60 2.00 1.60 2.00 th tpw(H) Pulse Width HIGH 325 Units Max 2.30 325 0.50 2.20 0.40 2.50 ns 4 Figures 1 and 3 1, 2, 3, 5 1, 2, 3, 5 1, 2, 3, 5 CP MR Figures 1 and 5 1, 2, 3, 5 ns Figures 1 and 3 4 ns Figure 6 4 ns Figure 6 4 ns Figures 3 and 4 4 Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b 55 C), then testing immediately after power-up. This provides ``cold start'' specs which can be considered a worst case condition at cold tempertures. Note 2: Screen tested 100% on each device at a 25 C temperature only, Subgroups A9. Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a 25 C, Subgroups A9, and at a 125 C and b 55 C temperatures, Subgroups A10 and A11. Note 4: Not tested at a 25 C, a 125 C, and b 55 C temperature (design characterization data). Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching. 10 Test Circuitry Notes: VCC, VCCA e a 2V, VEE e b 2.5V L1, L2 and L3 e equal length 50X impedance lines RT e 50X terminator internal to scope Decoupling 0.1 mF from GND to VCC and VEE All unused outputs are loaded with 50X to GND CL e Fixture and stray capacitance s 3 pF Pin numbers shown are for flatpak; for DIP see logic symbol TL/F/10584 - 6 FIGURE 1. AC Test Circuit TL/F/10584 - 7 FIGURE 2. Shift Frequency Test Circuit (Shift Left) Notes: For shift right mode, a 1.05V is applied at S0. The feedback path from output to input should be as short as possible. 11 Switching Waveforms TL/F/10584 - 8 FIGURE 3. Propagation Delay (Clock) and Transition Times TL/F/10584 - 9 FIGURE 4. Propagation Delay (Reset) 12 Switching Waveforms (Continued) TL/F/10584 - 10 FIGURE 5. Propagation Delay (Serial Data, Selects) TL/F/10584 - 11 Notes: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. FIGURE 6. Setup and Hold Time TL/F/10584 - 15 Note: Shift Right Mode; S0 e H, S1 e H, S2 e L. FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode) 13 Switching Waveforms (Continued) Note: Shift Left Mode; S0 e L, S1 e H, S2 e L. TL/F/10584 - 16 FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode) TL/F/10584 - 17 Note: *Decimal representation of binary outputs. Count Up: S0 e L, S1 e H, S2 e H; Count Down: S0 e L, S1 e L, S2 e H. Measurement taken at 50% point of waveform. FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes) TL/F/10584 - 18 Note: Shift Right Mode; S0 e H, S1 e H, S2 e L. FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode) 14 Switching Waveforms (Continued) TL/F/10584 - 19 Note: Shift Left Mode; S0 e L, S1 e H, S2 e L. FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode) TL/F/10584 - 20 Note: *Decimal representation of binary outputs. Count Up Mode: S0 e L, S1 e H, S2 e H. TL/F/10584 - 21 Note: *Decimal representation of binary outputs. Count Down Mode: S0 e L, S1 e L, S2 e H. FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes) 15 Applications 3-Stage Divider, Preset Count Down Mode Note: If S0 e S1 e S2 e LOW, then TC e LOW TL/F/10584 - 12 Slow Expansion Scheme TL/F/10584 - 13 Fast Expansion Scheme TL/F/10584 - 14 Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 100336 D Device Number (Basic) C QB Special Variation QB e Military grade device with environmental and burn-in processing Package Code D e Ceramic DIP F e Quad Cerpak P e Plastic DIP Q e Plastic Leaded Chip Carrier (PCC) S e Small Outline (SOIC) Temperature Range C e Commercial (0 C to a 85 C) I e Industrial (b40 C to a 85 C) (PCC only) M e Military (b55 C to a 125 C) 16 17 Physical Dimensions inches (millimeters) 24-Lead Ceramic Dual-In-Line Package (0.400x Wide) (D) NS Package Number J24E 24-Lead Molded Package (0.300x Wide) (S) NS Package Number M24B 18 Physical Dimensions inches (millimeters) (Continued) 24-Lead Plastic Dual-In-Line Package (P) NS Package Number N24E NS Package Number V28A 28-Lead Plastic Chip Carrier (Q) 19 --- OVERFLOW DATA THIS PAGE --- 100336 Low Power 4-Stage Counter/Shift Register Physical Dimensions inches (millimeters) (Continued) Lit. Y 114913 24-Lead Quad Cerpak (F) NS Package Number W24B LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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