TL/F/10584
100336 Low Power 4-Stage Counter/Shift Register
July 1992
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down coun-
ter or as a 4-bit bidirectional shift register. Three Select (Sn)
inputs determine the mode of operation, as shown in the
Function Select table. Two Count Enable (CEP, CET) inputs
are provided for ease of cascading in multistage counters.
One Count Enable (CET) input also doubles as a Serial Data
(D0) input for shift-up operation. For shift-down operation,
D3is the Serial Data input. In counting operations the Termi-
nal Count (TC) output goes LOW when the counter reaches
15 in the count/up mode or 0 (zero) in the count/down
mode. In the shift modes, the TC output repeats the Q3
output. The dual nature of this TC/Q3output and the D0/
CET input means that one interconnection from one stage
to the next higher stage serves as the link for multistage
counting or shift-up operation. The individual Preset (Pn) in-
puts are used to enter data in parallel or to preset the coun-
ter in programmable counter applications. A HIGH signal on
the Master Reset (MR) input overrides all other inputs and
asynchronously clears the flip-flops. In addition, a synchro-
nous clear is provided, as well as a complement function
which synchronously inverts the contents of the flip-flops.
All inputs have 50 kXpull-down resistors.
Features
Y40% power reduction of the 100136
Y2000V ESD protection
YPin/function compatible with 100136
YVoltage compensated operating range e
b4.2V to b5.7V
YAvailable to industrial grade temperature range
YAvailable to MIL-STD-883
Logic Symbol
TL/F/10584–1
Pin Names Description
CP Clock Pulse Input
CEP Count Enable Parallel Input (Active LOW)
D0/CET Serial Data Input/Count Enable
Trickle Input (Active LOW)
S0–S2Select Inputs
MR Master Reset Input
P0–P3Preset Inputs
D3Serial Data Input
TC Terminal Count Output
Q0–Q3Data Outputs
Q0–Q3Complementary Data Outputs
Connection Diagrams
24-Pin DIP/SOIC
TL/F/10584–2
28-Pin PCC
TL/F/10584–4
24-Pin Quad Cerpak
TL/F/10584–3
C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Logic Diagram
TL/F/10584–5
2
Function Select Table
S2S1S0Function
L L L Parallel Load
L L H Complement
L H L Shift Left
L H H Shift Right
H L L Count Down
H L H Clear
H H L Count Up
H H H Hold
Truth Table
Q0eLSB
Inputs Outputs
MR S2S1S0CEP D0/CET D3CP Q3Q2Q1Q0TC Mode
LLLL X X XLP
3
P
2
P
1
P
0L Preset (Parallel Load)
LLLHX X XLQ
3
Q
2
Q
1
Q
0L Invert
LLHL X X XLD
3
Q
3
Q
2
Q
1
D
3
Shift to LSB
LLHHX X XLQ
2
Q
1
Q
0
D
0
Q
3
*Shift to MSB
LHLL L L XL(Q0–3) minus 1 jCount Down
LHLL H L X XQ
3
Q
2
Q
1
Q
0jCount Down with CEP not active
LHLL X H X XQ
3
Q
2
Q
1
Q
0H Count Down with CET not active
LHLH X X XLL L L L H Clear
LHHL L L XL(Q0–3) plus 1 kCount Up
LHHL H L X XQ
3
Q
2
Q
1
Q
0kCount Up with CEP not active
LHHL X H X XQ
3
Q
2
Q
1
Q
0H Count Up with CET not active
LHHH X X X XQ
3
Q
2
Q
1
Q
0H Hold
HLLL X X X X LLLL L
HLLH X X X X LLLL L
HLHL X X X X LLLL L
HLHH X X X X LLLL LAsynchronous
HHLL X L X X LLLL LMaster Reset
HHLL X H X X LLLL H
HHLH X X X X LLLL H
HHHL X X X X LLLL H
HHHH X X X X LLLL H
j
e
LifQ
0
–Q3eLLLL *Before the clock, TC is Q3
HifQ
0
–Q3iLLLL After the clock, TC is Q2
keLifQ
0
–Q3eHHHH
HifQ
0
–Q3iHHHH
HeHIGH Voltage Level
LeLOW Voltage Level
XeDon’t Care
LeLOW-to-HIGH Transition
3
Absolute Maximum Ratings
Above which the useful life may be impaired. (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature (TSTG)b65§Ctoa
150§C
Maximum Junction Temperature (TJ)
Ceramic a175§C
Plastic a150§C
VEE Pin Potential to Ground Pin b7.0V to a0.5V
Input Voltage (DC) VEE to a0.5V
Output Current (DC Output HIGH) b50 mA
ESD (Note 2) t2000V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Recommended Operating
Conditions
Case Temperature (TC)
Commercial 0§Ctoa
85§C
Industrial b40§Ctoa
85§C
Military b55§Ctoa
125§C
Supply Voltage (VEE)b5.7V to b4.2V
Commercial Version
DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCe0§Ctoa
85§C (Note 3)
Symbol Parameter Min Typ Max Units Conditions
VOH Output HIGH Voltage b1025 b955 b870 mV VIN eVIH (Max) Loading with
VOL Output LOW Voltage b1830 b1705 b1620 mV or VIL (Min) 50Xto b2.0V
VOHC Output HIGH Voltage b1035 mV VIN eVIH(Min) Loading with
VOLC Output LOW Voltage b1610 mV or VIL (Max) 50Xto b2.0V
VIH Input HIGH Voltage b1165 b870 mV Guaranteed HIGH Signal
for All Inputs
VIL Input LOW Voltage b1830 b1475 mV Guaranteed LOW Signal
for All Inputs
IIL Input LOW Current 0.50 mAV
IN eVIL (Min)
IIH Input HIGH Current 240 mAV
IN eVIH (Max)
IEE Power Supply Current b165 b80 Inputs Open
Note 3: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.
4
Commercial Version (Continued)
DIP AC Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCe0§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
fshift Shift Frequency 300 300 300 MHz
Figures 2
and
3
tPLH Propagation Delay 1.00 2.00 1.00 2.00 1.00 2.00 ns
Figures 1
and
3
tPHL CP to Qn,Q
n(Note 1)
tPLH Propagation Delay 2.10 3.50 2.10 3.50 2.10 3.70 ns
Figures 1, 7, 8
tPHL CP to TC (Shift) (Note 1)
tPLH Propagation Delay 2.40 4.40 2.40 4.40 2.60 4.70 ns
Figures 1
and
9
tPHL CP to TC (Count) (Note 1)
tPLH Propagation Delay 1.40 2.50 1.40 2.50 1.50 2.60 ns
Figures 1
and
4
tPHL MR to Qn,Q
n(Note 1)
tPLH Propagation Delay 2.80 5.10 2.90 5.20 3.10 5.50 ns
Figures 1, 12
tPHL MR to TC (Count) (Note 1)
tPHL Propagation Delay 2.40 4.00 2.40 4.00 2.50 4.10 ns
Figures 1, 10, 11
MR to TC (Shift) (Note 1)
tPLH Propagation Delay 1.80 3.10 1.80 3.10 1.90 3.30 ns
tPHL D0/CET to TC
Figures 1
and
5
tPLH Propagation Delay 1.90 4.10 1.90 4.10 2.10 4.40 ns
(Note 1)
tPHL Snto TC
tTLH Transition Time 0.35 1.20 0.35 1.20 0.35 1.20 ns
Figures 1
and
3
tTHL 20% to 80%, 80% to 20%
tSSetup Time
D31.00 1.00 1.00
Pn1.50 1.50 1.50
D0/CET 1.30 1.30 1.30 ns
Figures 6
and
4
CEP 1.40 1.40 1.40
Sn3.40 3.40 3.40
MR (Release Time) 2.60 2.60 2.60
tHHold Time
D30.40 0.40 0.40
Pn0.30 0.30 0.30 ns
Figure 6
D0/CET 0.30 0.30 0.30
CEP 0.20 0.20 0.20
Sn0.10 0.10 0.10
tpw(H) Pulse Width HIGH 2.00 2.00 2.00 ns
Figures 3
and
4
CP, MR
Note 1: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
5
Commercial Version (Continued)
SOIC, PCC and Cerpak AC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCe0§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
fshift Shift Frequency 350 350 350 MHz
Figures 2
and
3
tPLH Propagation Delay 1.00 1.80 1.00 1.80 1.00 1.80 ns
Figures 1
and
2
tPHL CP to Qn,Q
n(Note 2)
tPLH Propagation Delay 2.10 3.30 2.10 3.30 2.10 3.50 ns
Figures 1, 7, 8
tPHL CP to TC (Shift) (Note 2)
tPLH Propagation Delay 2.40 4.20 2.40 4.20 2.60 4.50 ns
Figures 1
and
9
tPHL CP to TC (Count) (Note 2)
tPLH Propagation Delay 1.40 2.30 1.40 2.30 1.50 2.40 ns
Figures 1
and
4
tPHL MR to Qn,Q
n(Note 2)
tPLH Propagation Delay 2.80 4.90 2.90 5.00 3.10 5.30 ns
Figures 1
and
12
tPHL MR to TC (Count) (Note 2)
tPHL Propagation Delay 2.40 3.80 2.40 3.80 2.50 3.90 ns
Figures 1, 10, 11
MR to TC (Shift) (Note 2)
tPLH Propagation Delay 1.80 2.90 1.80 2.90 1.90 3.10 ns
tPHL D0/CET to TC
Figures 1
and
5
tPLH Propagation Delay 1.90 3.90 1.90 3.90 2.10 4.20 ns
(Note 2)
tPHL Snto TC
tTLH Transition Time 0.35 1.10 0.35 1.10 0.35 1.10 ns
Figures 1
and
3
tTHL 20% to 80%, 80% to 20%
tSSetup Time
D30.90 0.90 0.90
Pn1.40 1.40 1.40
D0/CET 1.20 1.20 1.20 ns
Figures 4
and
6
CEP 1.30 1.30 1.30
Sn3.30 3.30 3.30
MR (Release Time) 2.50 2.50 2.50
tHHold Time
D30.30 0.30 0.30
Pn0.20 0.20 0.20 ns
Figure 6
D0/CET 0.20 0.20 0.20
CEP 0.10 0.10 0.10
Sn0.00 0.00 0.00
tpw(H) Pulse Width HIGH 2.00 2.00 2.00 ns
Figures 3
and
4
CP, MR
tOSHL Maximum Skew Common Edge PCC Only
Output-to-Output Variation 200 200 200 ps (Note 1)
Clock to Output Path
tOSLH Maximum Skew Common Edge PCC Only
Output-to-Output Variation 200 200 200 ps (Note 1)
Clock to Output Path
tOST Maximum Skew Opposite Edge PCC Only
Output-to-Output Variation 230 230 230 ps (Note 1)
Clock to Output Path
tps Maximum Skew PCC Only
Pin (Signal) Transition Variation 245 245 245 ps (Note 1)
Clock to Output Path
Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL), or LOW to HIGH (tOSLH), or in opposite directions both
HL and LH (tOST). Parameters tOST and tps guaranteed by design
Note 2: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
6
Industrial Version
PCC DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCeb
40§Ctoa
85§C (Note 1)
Symbol Parameter TCeb
40§CT
C
e
0
§
Ctoa
85§CUnits Conditions
Min Max Min Max
VOH Output HIGH Voltage b1085 b870 b1025 b870 mV VIN eVIH (Max) Loading with
VOL Output LOW Voltage b1830 b1575 b1830 b1620 mV or VIL (Min) 50Xto b2.0V
VOHC Output HIGH Voltage b1095 b1035 mV VIN eVIH(Min) Loading with
VOLC Output LOW Voltage b1565 b1610 mV or VIL (Max) 50Xto b2.0V
VIH Input HIGH Voltage b1170 b870 b1165 b870 mV Guaranteed HIGH Signal
for All Inputs
VIL Input LOW Voltage b1830 b1480 b1830 b1475 mV Guaranteed LOW Signal
for All Inputs
IIL Input LOW Current 0.50 0.50 mAV
IN eVIL (Min)
IIH Input HIGH Current 240 240 mAV
IN eVIH (Max)
IEE Power Supply Current b165 b75 b165 b80 mA Inputs Open
Note 1: The specified limits represent the ‘‘worst case’’ value for the parameter. Since these values normally occur at the temperature extremes, additional noise
immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to
guarantee operation under ‘‘worst case’’ conditions.
7
Industrial Version (Continued)
PCC AC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCeb
40§CT
C
ea
25§CT
C
ea
85§CUnits Conditions
Min Max Min Max Min Max
fshift Shift Frequency 325 350 350 MHz
Figures 2
and
3
tPLH Propagation Delay 1.00 1.80 1.00 1.80 1.00 1.80 ns
Figures 1
and
3
tPHL CP to Qn,Q
n(Note 1)
tPLH Propagation Delay 2.00 3.30 2.10 3.30 2.10 3.50 ns
Figures 1, 7, 8
tPHL CP to TC (Shift) (Note 1)
tPLH Propagation Delay 2.40 4.20 2.40 4.20 2.60 4.50 ns
Figures 1
and
9
tPHL CP to TC (Count) (Note 1)
tPLH Propagation Delay 1.40 2.30 1.40 2.30 1.50 2.40 ns
Figures 1
and
4
tPHL MR to Qn,Q
n(Note 1)
tPLH Propagation Delay 2.80 4.90 2.90 5.00 3.10 5.30 ns
Figures 1 and 12
tPHL MR to TC (Count) (Note 1)
tPHL Propagation Delay 2.40 3.80 2.40 3.80 2.50 3.90 ns
Figures 1, 10, 11
MR to TC (Shift) (Note 1)
tPLH Propagation Delay 1.70 2.90 1.80 2.90 1.90 3.10 ns
tPHL D0/CET to TC
Figures 1
and
5
tPLH Propagation Delay 1.80 3.90 1.90 3.90 2.10 4.20 ns
(Note 1)
tPHL Snto TC
tTLH Transition Time 0.20 1.90 0.35 1.10 0.35 1.10 ns
Figures 1
and
3
tTHL 20% to 80%, 80% to 20%
tsSetup Time
D31.40 0.90 0.90
Pn1.70 1.40 1.40
D0/CET 1.80 1.20 1.20 ns
Figure 6
CEP 1.80 1.30 1.30
Sn3.30 3.30 3.30
MR (Release Time) 2.60 2.50 2.50
thHold Time
D30.90 0.30 0.30
Pn1.00 0.20 0.20 ns
Figure 6
D0/CET 0.70 0.20 0.20
CEP 0.60 0.10 0.10
Sn0.00 0.00 0.00
tpw(H) Pulse Width HIGH 2.20 2.00 2.00 ns
Figures 3
and
4
CP, MR
Note 1: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
8
Military Version
DC Electrical Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND, TCeb
55§Ctoa
125§C
Symbol Parameter Min Max Units TCConditions Notes
VOH Output HIGH Voltage b1025 b870 mV 0§Cto
a
125§CVIN eVIH (Max) Loading with
b1085 b870 mV b55§Cor VIL (Min) 50Xto b2.0V 1, 2, 3
VOL Output LOW Voltage b1830 b1620 mV 0§Cto
a
125§C
b1830 b1555 mV b55§C
VOHC Output HIGH Voltage b1035 mV 0§Cto
a
125§CVIN eVIH (Min) Loading with
b1085 mV b55§Cor VIL (Max) 50Xto b2.0V 1, 2, 3
VOLC Output LOW Voltage b1610 mV 0§Cto
a
125§C
b1555 mV b55§C
VIH Input HIGH Voltage b1165 b870 mV b55§C to Guaranteed HIGH Signal 1, 2, 3, 4
a125§C for All Inputs
VIL Input LOW Voltage b1830 b1475 mV b55§C to Guaranteed LOW Signal 1, 2, 3, 4
a125§C for All Inputs
IIL Input LOW Current 0.50 mAb55§Cto V
EE eb
4.2V 1, 2, 3
a125§CV
IN eVIL (Min)
IIH Input HIGH Current 240 mA0§Cto V
EE eb
5.7V
a125§CVIN eVIH(Max)
1, 2, 3
340 mAb55§C
IEE Power Supply Current b55§C Inputs Open
b185 b70 mA to VEE eb
4.2V to b4.8V 1, 2, 3
b195 b70 a125§CV
EE eb
4.2V to b5.7V
Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing
immediately without allowing for the junction temperature to stablize due to heat dissipation after power-up. This provides ‘‘cold start’’ specs which can be
considered a worst case condition at cold temperatures.
Note 2: Screen tested 100% on each device at b55§C, a25§C, and a125§C, Subgroups 1, 2, 3, 7, and 8.
Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at b55§C, a25§C, a125§C, Subgroups A1, 2, 3, 7, and 8.
Note 4: Guaranteed by applying specified input conditon and testing VOH/VOL.
9
Military Version (Continued)
AC Characteristics
VEE eb
4.2V to b5.7V, VCC eVCCA eGND
Symbol Parameter TCeb
55§CT
C
ea
25§CT
C
ea
125§Units Conditions Notes
Min Max Min Max Min Max
fshift Shift Frequency 325 325 325 MHz
Figures 2
and
3
4
tPLH Propagation Delay 0.40 2.30 0.50 2.20 0.40 2.50 ns
Figures 1
and
3
tPHL CP to Qn,Q
n1, 2, 3, 5
tPLH Propagation Delay 1.30 3.90 1.70 3.80 1.70 4.20 ns
Figures 1, 7, 8
tPHL CP to TC (Shift)
tPLH Propagation Delay 1.20 4.60 1.50 4.60 1.60 5.20 ns
Figures 1
and
9
1, 2, 3, 5
tPHL CP to TC (Count)
tPLH Propagation Delay 0.60 2.90 0.80 2.80 0.90 3.20 ns
Figures 1
and
4
tPHL MR to Qn,Q
n1, 2, 3, 5
tPLH Propagation Delay 2.30 5.20 2.70 5.20 2.90 5.90 ns
Figures 1, 12
tPHL MR to TC (Count)
tPHL Propagation Delay 2.10 4.30 2.20 4.10 2.40 4.70 ns
Figures 1, 10, 11
1, 2, 3, 5
MR to TC (Shift)
tPLH Propagation Delay 0.70 3.20 1.00 3.20 1.30 4.10 ns
tPHL D0/CET to TC
Figures 1
and
5
1, 2, 3, 5
tPLH Propagation Delay 1.30 4.10 1.50 4.20 1.70 4.90 ns
tPHL Snto TC
tTLH Transition Time 0.20 1.90 0.20 1.80 0.20 2.00 ns
Figures 1
and
3
4
tTHL 20% to 80%, 80% to 20%
tsSetup Time
D31.40 1.40 1.40
Pn1.70 1.70 1.70
D0/CET 1.80 1.80 1.80 ns
Figure 6
4
CEP 1.80 1.80 1.80
Sn3.30 3.30 3.30
MR (Release Time) 2.60 2.60 2.60
thHold Time
D30.90 0.90 0.90
Pn1.00 1.00 1.00 ns
Figure 6
4
D0/CET 0.70 0.70 0.70
CEP 0.60 0.60 0.60
Sn0.00 0.00 0.00
tpw(H) Pulse Width HIGH CP 1.60 1.60 1.60 ns
Figures 3
and
4
4
MR 2.00 2.00 2.00
Note 1: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals b55§C), then testing
immediately after power-up. This provides ‘‘cold start’’ specs which can be considered a worst case condition at cold tempertures.
Note 2: Screen tested 100% on each device at a25§C temperature only, Subgroups A9.
Note 3: Sample tested (Method 5005, Table I) on each manufactured lot at a25§C, Subgroups A9, and at a125§C and b55§C temperatures, Subgroups A10 and
A11.
Note 4: Not tested at a25§C, a125§C, and b55§C temperature (design characterization data).
Note 5: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
10
Test Circuitry
Notes:
VCC,V
CCA ea
2V, VEE eb
2.5V
L1, L2 and L3 eequal length 50Ximpedance lines
RTe50Xterminator internal to scope
Decoupling 0.1 mF from GND to VCC and VEE
All unused outputs are loaded with 50Xto GND
CLeFixture and stray capacitance s3pF
Pin numbers shown are for flatpak;
for DIP see logic symbol
TL/F/10584–6
FIGURE 1. AC Test Circuit
TL/F/10584–7
FIGURE 2. Shift Frequency Test Circuit (Shift Left)
Notes:
For shift right mode, a1.05V is applied at S0.
The feedback path from output to input should be as short as possible.
11
Switching Waveforms
TL/F/10584–8
FIGURE 3. Propagation Delay (Clock) and Transition Times
TL/F/10584–9
FIGURE 4. Propagation Delay (Reset)
12
Switching Waveforms (Continued)
TL/F/10584–10
FIGURE 5. Propagation Delay (Serial Data, Selects)
TL/F/10584–11
Notes:
tsis the minimum time before the transition of the clock that information must be present at the data input.
this the minimum time after the transition of the clock that information must remain unchanged at the data input.
FIGURE 6. Setup and Hold Time
TL/F/10584–15
Note: Shift Right Mode; S0eH, S1eH, S2eL.
FIGURE 7. Propagation Delay, Clock to Terminal Count (Shift Right Mode)
13
Switching Waveforms (Continued)
Note: Shift Left Mode; S0eL, S1eH, S2eL. TL/F/10584–16
FIGURE 8. Propagation Delay, Clock to Terminal Count (Shift Left Mode)
TL/F/10584–17
Note:
*Decimal representation of binary outputs.
Count Up: S0eL, S1eH, S2eH; Count Down: S0eL, S1eL, S2eH.
Measurement taken at 50% point of waveform.
FIGURE 9. Propagation Delay, Clock to Terminal Count (Count Up and Count Down Modes)
TL/F/10584–18
Note: Shift Right Mode; S0eH, S1eH, S2eL.
FIGURE 10. Propagation Delay, Master Reset to Terminal Count (Shift Right Mode)
14
Switching Waveforms (Continued)
TL/F/10584–19
Note: Shift Left Mode; S0eL, S1eH, S2eL.
FIGURE 11. Propagation Delay, Master Reset to Terminal Count (Shift Left Mode)
TL/F/10584–20
Note:
*Decimal representation of binary outputs. Count Up Mode: S0eL, S1eH, S2eH.
TL/F/10584–21
Note:
*Decimal representation of binary outputs. Count Down Mode: S0eL, S1eL, S2eH.
FIGURE 12. Propagation Delay, Master Reset to Terminal Count (Count Up and Count Down Modes)
15
Applications
3-Stage Divider, Preset Count Down Mode
Note: If S0eS1eS2eLOW, then TCeLOW TL/F/10584–12
Slow Expansion Scheme
TL/F/10584–13
Fast Expansion Scheme
TL/F/10584–14
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
100336 D C QB
Device Number (Basic) Special Variation
QB eMilitary grade device with
Package Code environmental and burn-in
DeCeramic DIP processing
FeQuad Cerpak
PePlastic DIP Temperature Range
QePlastic Leaded Chip Carrier (PCC) C eCommercial (0§Ctoa
85§C)
SeSmall Outline (SOIC) I eIndustrial (b40§Ctoa
85§C)
(PCC only)
MeMilitary (b55§Ctoa
125§C)
16
17
Physical Dimensions inches (millimeters)
24-Lead Ceramic Dual-In-Line Package (0.400×Wide) (D)
NS Package Number J24E
24-Lead Molded Package (0.300×Wide) (S)
NS Package Number M24B
18
Physical Dimensions inches (millimeters) (Continued)
24-Lead Plastic Dual-In-Line Package (P)
NS Package Number N24E
28-Lead Plastic Chip Carrier (Q)
NS Package Number V28A
---OVERFLOW DATA THISPAGE ---
19
100336 Low Power 4-Stage Counter/Shift Register
Physical Dimensions inches (millimeters) (Continued) Lit. Ý114913
24-Lead Quad Cerpak (F)
NS Package Number W24B
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
