PA080XS1 Version : 0.2 TECHNICAL MODEL SPECIFICATION NO. : PA080XS1 Customer's Confirmation Customer Date By PVI's Confirmation Confirmed By Prepared By FOR MORE INFORMATION: AZ DISPLAYS, INC. 75 COLUMBIA, ALISO VIEJO, CA, 92656 http://www.AZDISPLAYS.com Date : Mar.22,2005 This technical specification is subject to change without notice. Please return 1 copy with your signature on this page for approval. The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:1 PA080XS1 TECHNICAL SPECIFICATION CONTENTS NO. ITEM PAGE - Cover 1 - Contents 2 1 Application 3 2 Features 3 3 Mechanical Specifications 3 4 Mechanical Drawing of TFT-LCD module 4 5 Input / Output Terminals 5 6 Pixel Arrangement and input connector pin NO. 6 7 Absolute Maximum Ratings 6 8 Electrical Characteristics 7 9 Power Sequence 17 10 Optical Characteristics 17 11 Handling Cautions 21 12 Reliability Test 22 13 Block Diagram 23 14 Packing 24 - Revision History 25 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:2 PA080XS1 1. Application This technical specification applies to 8" color TFT-LCD module, PA080XS1. The applications of the panel are car TV, portable DVD, GPS, multimedia applications and others AV system. 2. Features . Pixel in stripe configuration . Slim and compact . High Brightness . Image ReversionUp/Down and Left/Right . Column inversion driving 3. Mechanical Specifications Parameter Screen Size Display Format Active Area Dot Pitch Pixel Configuration Outline Dimension Surface Treatment Weight Specifications 8(diagonal) 1440x468 161.28 (H)x117.94 (V) 0.112(H)x0.252(V) Stripe 172.4(W)x 131.99(H)x 6.64(D)(typ.) Anti-Glare TBD Unit Inch dot mm mm mm g The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:3 PA080XS1 4. Mechanical Drawing of TFT-LCD Module The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:4 PA080XS1 5. Input / Output Terminals LCD Module Connector FPC Down Connect , 32 Pins , Pitch : 0.5 mm Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol STH2 OEH POL MOD R/L VDD1 CPH3 CPH2 CPH1 VSS1 VDD2 VBVGVRVSS2 VB+ VG+ VR+ VSS2 STH1 VCOM OE1 OE2 OE3 U/D CKV STVD STVU VCC VEE VGH GND I/O I/O I I I I I I I I I I I I I I/O I I I I I I I/O I/O - Description Start pulse for source driver Output enable for source driver P0larity control for column inversion Simultaneous/sequential mode select Left / Right Control for source driver Supply voltage of logic circuit for source driver Sample and shift clock for source driver Sample and shift clock for source driver Sample and shift clock for source driver Ground of logic circuit for source driver Supply voltage of analog circuit for source driver Video input B for negative polarity Video input G for negative polarity Video input R for negative polarity Ground for analog circuit for source driver Video input B for positive polarity Video input G for positive polarity Video input R for positive polarity Ground for analog circuit for source driver Start pulse for source driver Voltage for common electrode Output enable for gate driver Output enable for gate driver Output enable for gate driver Up / Down Control for gate driver Shift clock for gate driver Vertical start pulse Vertical start pulse Power supply for gate driver circuit Negative power gate driver Positive power gate driver Ground for gate driver Note 5-1 U/D STVD Vcc Input GND Output STVU output input scanning direction up todown down to up Note 5-2 R/L STH1 Vcc input GND output STH2 output input scanning direction left to right right to left Remark Note 5-2 Note 5-2 Note 5-2 Note 5-1 Note 5-1 Note 5-3 Note 5-4 Note 5-5 The definitions of Note 5-1,5-2 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:5 PA080XS1 U/D(PIN 25)=High R/L(PIN 5)=High U/D(PIN 25)=LowR/L(PIN 5)=Low Note 5-3 : VCC TYP.+3.3V Note 5-4 : VEE TYP.-10V Note 5-5 : VGH TYP.+20V Note 5-6 : VDD2 TYP.+12V Note 5-7 : VDD1 TYP.+3.3V 6. Pixel Arrangement and input connector pin NO. Line 1 Gate driver Line 1440 R G B R G B R G B R G B Row 1 R G B R G B R G B R G B Row 2 R G B R G B R G B R G B Row 3 R G B R G B R G B R G B Row 4 R G B R G B R G B R G B Row 467 R G B R G B R G B R G B Row 468 Source driver Input FPC Pin 32 Pin 1 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:6 PA080XS1 7. Absolute Maximum Ratings The followings are maximum values , which if exceeded, may cause faulty operation or damage to the unit. Parameter Supply Voltage For Source Driver Supply Voltage For Gate Driver Analog Signal Input Level Symbol VDD2 MIN. +9.0 MAX. +13.5 Unit V VDD1 -0.3 +7.0 V VCC -0.3 +6.0 V VGH-VEE -0.3 +40.0 V H Level VGH -0.3 +25.0 V L Level VEE -16 +0.3 V VR+,VG+,VB+ +4 +11 V VR-,VG-,VB- 0 5.5 V Storage Temperature -30 +80 Operation Temperature -20 +70 Remark Note 7-1 Note 7-2 Notes 7-1 : Analog Input Voltage means VR,VG,VB. Notes 7-2 : Optical characteristics shown in Table 10-1 are measured under Ta=+25. 8. Electrical Characteristics 8-1) Recommended Driving condition for TFT-LCD panel Analog Logic H level Sym bol VDD2 VDD1 VGH L level VEE DC Parameter Supply Driver Voltage For Source Supply Voltage For Gate Driver Analog Signal input Level Digital input voltage Digital output voltage Vcom MIN. Typ. MAX. Unit +9 +4.5 +18 +10 +5.0 +20 +11 +5.5 +22 V V V -11 -10 -9 V Logic VCC +4.5 V VR+,VG+,VB+ +, AC (Analog video+) V+ ,DC 7.2 V- ,AC VR-,VG-,VB(Analog video-) V- ,DC 2.2 0.7 H level VIH -0.3 L level VIL 0.7 H level VOH L level VOL -0.3 VCOM 4.5 DC +5.0 +4.0 7.5 +4.02.5 5.0 Remark +5.5 V OP-P 7.8 V OP-P 2.8 V VDD1 V 0.3 V VDD1 V 0.3 V 5.5 V DC Component of VCOM Note 8-1 Note 8-1 : PVI strongly suggests that the VCOM DC level shall be adjustable , and the adjustable level range is 5.0V0.5V , every module's VCOM DC level shall be carefully adjusted to show a best image performance. The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:7 PA080XS1 8-2) Back Light driving (JST BHSR-02VS-1 ,Pin No.2) Pin No 1 2 Symbol VL1 VL2 Description Input terminal (Hi voltage side) Input terminal (Low voltage side) Remark Wire color: pink Wire color: white Note 8-2 Note 8-2 : Low voltage side of back light inverter connects with Ground of inverter circuits. Recommended driving condition for back light Parameter Symbol Min. Lamp voltage VL TBD Lamp current IL TBD Lamp frequency PL TBD Vs Starting voltage(25) (Reference Value) Vs Starting voltage(0) (Reference Value) Typ. TBD TBD TBD Max. TBD TBD TBD Unit Vrms mA KHz Vrms TBD Vrms TBD Ta= 25 Remark Note 8-3 Note 8-4 Note 8-5 Note 8-5 Note 8-3 : In order to satisfy the quality of B/L , no matter use what kind of inverter , the output lamp current must between Min. and Max. to avoid the abnormal display image caused by B/L. Note 8-4 : The waveform of lamp driving voltage should be as closed to a perfect sine wave as possible. Note 8-5 : This value is not output voltage of inverter. The voltage of inverter must larger than the starting voltage. The kick-off time must larger than 1 second. Ta= 25 Parameter Symbol Conditions TYP. MAX Unit Remark Supply current for Gate Driver (Hi level) IGH mA VGH +20V TBD TBD Supply current for Gate Driver (Low level) IEE mA VEE -10V TBD TBD IDD1 VDD1 +3.3V TBD TBD Supply current for Source Driver(Digital) mA IDD2 VDD2 +12V TBD TBD Supply current for Source Driver(Analog) mA VCC +3.3V TBD TBD Supply current for Gate Driver (Digital) ICC mA 8-3) Power Consumption LCD Panel Power Consumption TBD Back Light Lamp Power Consumption TBD TBD mW Note 8-6 W Note 8-7 Note 8-6 : The power consumption for back light is not included. Note 8-7 : Back light lamp power consumption is calculated by ILxVL. The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:8 PA080XS1 8-4) Timing Characteristics Of Input Signals Characteristics Symbol Rising time tr Falling time tf High and low level pulse width tCPH CPH pulse duty tCWH STH setup time tSUH STH hold time tHDH STH pulse width tSTH STH period tH OEH pulse width tOEH Sample and hold disable time tDIS1 OEV pulse width tOEV CKV pulse width tCKV Clean enable time tDIS2 Horizontal display start tSH Horizontal display timing range tDH STV setup time tSUV STV hold time tHDV STV pulse width tSTV Horizontal lines per field tV Vertical display start tSV Vertical display timing range tDV Min. 9.2 30 20 20 61.5 400 400 256 Typ. 9.6 50 1 63.5 1.40 7.43 18 31.75 9.0 0 480 262 3 234 Max. 10 10 10.0 70 65.5 1 268 - Unit ns ns MHz % ns ns tCPH s s s s s s tCPH/3 tCPH Ns Ns tH tH tH tH Remark CPH1~CPH3 CPH1~CPH3 STH1,STH2 STH1,STH2 STH1,STH2 STH1,STH2 OEH OEV CKV STVD,STVU STVD,STVU STVD,STVU The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:9 PA080XS1 10% tr 90% 90% tf 10% 8-5) Signal Timing Waveforms CPH3 (L) CPH2 (L) CPH1 STHL(R) 50% tCWH 50% tCPH tSUH tSTH tHDH g n i m i t k c o l c g n i l p m a S 1 8 . g i F The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:10 Fig. 8-2 Horizontal display timing range CPH1 Output (STHR/STHL) Input (STHL/STHR) tDH PA080XS1 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:11 CKV OE 1,2,3 STHL(R) OEH (HSY) 1H tH Fig. 8-3 (a) Horizontal timing PA080XS1 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:12 Fig. 8-3 (b) Detail horizontal timing CKV OE 1,2,3 STHL(R) OEH (HSY) tDIS2 tOEV tOEH tCKV tDIS1 1H tSTH Note : The falling edge of OEV should be synchronized with the falling edge of OEH PA080XS1 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:13 V- ,AC Blamk Black Vcom DC V- ,DC Negative Analog video Positive Analog video (HSY) V+ ,DC Black Blamk 1H V+ ,AC White White Fig 8-3(c) Vcom &Analog video timing PA080XS1 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:14 Fig. 8-4 Vertical shift clock timing CKV STVU(D) tSUV 1H tCKV tHDV PA080XS1 The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:15 PA080XS1 V(R,G,B-) Vcom V(R,G,B+) STVU/STVD (VSY) (HSY) Fig. 8-5 (a) Vertical timing tsv Display on panel first line Vertical timing The information contained herein is the exclusive property of Prime View International Co., Ltd. and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Prime View International Co., Ltd.PAGE:16 PA080XS1 VGH VDD,VCC VSS(0V) VEE OFF OFF ON T1 T3 Logic signal RGB-Video signal T2 T4 9. Power on Sequence The Power on Sequence only effect by VCC, VDD,VEE and VGH, the others do not care. 1) 10msT1