1 November 01, 2001
UL62H1708B
Preliminary
F131072 x 8 bit static CMO S RAM
F35 and 55 ns Access Time
FComm on data inputs and
data outputs
FThree-state outputs
FTyp. operating supply current
35 ns: 45mA
55 ns: 30mA
FStandby current <100µA at 125°C
FPower supply voltage 2.5 V
FOperating temperature r ange
-40 °C to 85 °C
-40 °C to 125 °C
FCECC 90000 Qua lity Standard
FESD protection > 2000 V
(MIL STD 883C M3015.7)
FLatch-up im mun ity >100 mA
FPackage: SOP32 (300/330 mil)
The UL62H1708B is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operat i ng modes:
- Read - Standby
- Write - Data Rete ntion
The memory array is based on a
6-Transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read or Write cycl e.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the da ta
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and cont rol signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by th e falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are requ ired.
Low Voltage Automotive Fast 128K x 8 SRAM
Pin Configuration
Top View
Sign al Name Signal Descript ion
A0 - A16 Address Inputs
DQ0 - DQ7 Data In/Out
E1 Chip Enable 1
E2 Chip Enable 2
GOutput Enable
WWrite Enable
VCC Power Supply Voltage
VSS Ground
n.c. not connected
Pin Descript ion
1n.c. VCC32
2A16 A1531
4A12 W
29
5A7 A1328
3A14 E230
6A6 A827
7A5 A926
8A4 A1125
12A0 DQ721
9A3 G
24
10
A2 A1023
11A1 E1
22
13DQ0 DQ620
14DQ1 DQ519
SOP
DQ4
DQ3
DQ2
VSS
18
17
15
16
Features Description
2 November 01, 200 1
UL62H1708B Preliminary
Operating Mode E1 E2 W GDQ0 - DQ7
Standby/not selected * L * * High-Z
H*** High-Z
Internal Read L H H H High-Z
Read L H H L Data Outputs Low-Z
Write L H L * Data In puts High-Z
Truth Table
Block Diagram
Maxim um Rati ngs Symb ol Min. Max. U nit
Power Supply Vol tage VCC -0.3 3.6 V
Input Voltage VI-0.3 VCC + 0.3 V
Outp ut Vo ltage VO-0.3 VCC + 0. 3 V
Power Dissipation PD-1W
Operating Temperature K-Type
A-Type Ta-40
-40 85
125 °C
Storage Temp erature Tstg -65 150 °C
Outp ut Short-Circuit Current
at VCC = 2.5 V and VO = 0 V** | IOS | 100 mA
Characteristics
**Not more than 1 output should be shorted at the same time. Duration of the short circuit should not ex ceed 30 s.
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are ba sed on a rise and fall time of 5 ns, measured bet ween 10 % and 90 % of VI,as well as
input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V,
with the ex ception of the tdis-times and ten-times , in which case s transition is measured ±200 mV f rom stead y-state voltage.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC VSS W GE1
Row Address
Inputs
Column Address
Inputs
Address
Change
Detector
Column Decode r Row Decode r
Se ns e Am plifi er/
Write Control Logic
Clock
Generator
Com mon Data I/O
Memory C ell
Array
1024 Rows x
128 x 8 Columns
A0
A1
A2
A3
A10
A5
A6
A7
A8
A9
A4
A11
A12
A13
A14
A15
A16
E2
*H or L
3 November 01, 2001
UL62H1708B
Preliminary
Recommended
Operatin g Condi tions Symbol Conditions Min. Max. Unit
Power Supply Voltage VCC 2.3 2.7 V
Input Low Volt age*VIL -0.2 0.6 V
Input High Voltage VIH 2.0 VCC + 0.2 V
Electrical Characteri stics Symbol Cond itions Min. Max. Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
ICC(OP)
ICC(SB)
ICC(SB)1
VCC
VIL
VIH
tcW
tcW
tcW
VCC
VE1= VE2
VCC
VE1= VE2
K-Type
A-Type
= 2.7 V
= 0.6 V
=2.0 V
= 35 ns
= 55 ns
= 70 ns
=2.7 V
= VCC - 0.2 V
= 2.7 V
= 2.0 V
90
70
60
100
10
20
mA
mA
mA
µA
mA
mA
Output High Voltage
Output Low Volt age
VOH
VOL
VCC
IOH
VCC
IOL
= 2.3 V
=-0.5 mA
=2.3 V
=0.5 mA
2.0
0.4
V
V
Input High Leakage Current
Input Low Leakage Curren t
IIH
IIL
VCC
VIH
VCC
VIL
= 2.7 V
= 2.7 V
= 2.7 V
= 0 V -2
A
µA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
=2.3 V
=2.0 V
=2.3 V
=0.4 V 0.5
-0.5 mA
mA
Output Leakage Current
High at Three-State Outputs
Low at Three-Stat e Output s
IOHZ
IOLZ
VCC
VOH
VCC
VOL
=2.7 V
=2.7 V
=2.7 V
=0 V -2
A
µA
* -2 V at Pulse Wid th 1 0 ns
4 November 01, 200 1
UL62H1708B Preliminary
Switching Characteristics
Read Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Read Cycle Time tRC tcR 35 55 ns
Address Access Time to Data Valid tAA ta(A) 35 55 ns
Chip Enable Access Time to Data Valid tACE ta(E) 35 55 ns
G LOW to Data Valid tOE ta(G) 15 25 ns
E1 HIGH or E2 LOW to Output in High-Z tHZCE tdis(E) 12 15 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
E1 LOW or E2 HIGH to Output in Low-Z tLZCE ten(E) 33ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
Output Hold Tim e from Address Change tOH tv(A) 33ns
E1 LOW o r E 2 H I G H to P o w e r -Up Time tPU 00ns
E1 HI GH or E2 LOW to Power-Down T i me tPD 35 55 ns
Switching Characteristics
Write Cycle
Symbol 35 55 Unit
Alt. IEC Min. Max. Min. Max.
Write Cycle Time t WC tcW 35 55 ns
Write Pulse Width tWP tw(W) 20 35 ns
Write Setup Tim e tWP tsu(W) 20 35 ns
Address Setup Tim e tAS tsu(A) 00ns
Address Valid to End of W ri te tAW tsu(A-WH) 20 40 ns
Chip Enable Setup Time tCW tsu(E) 25 40 ns
Pulse Width Chip Enable to End o f Write tCW tw(E) 25 40 ns
Da ta Setup Time tDS tsu(D) 15 25 ns
Data Hold Time tDH th(D) 00ns
Address Hold from End of Write tAH th(A) 00ns
W LOW to Output in High-Z tHZWE tdis(W) 15 20 ns
G HIGH to Output in High-Z tHZOE tdis(G) 12 15 ns
W HIGH to Ou tpu t i n L o w - Z tLZWE ten(W) 00ns
G LOW to Output in Low-Z t LZOE ten(G) 00ns
5 November 01, 2001
UL62H1708B
Preliminary
Data Retention
Characteristics Symbol Conditions Min. Typ. Max. Unit
Alt. IEC
Data Retention Supply Vol tage VCC(DR) 1.5 2.7 V
Data Retention Supply Current ICC(DR) VCC(DR) = 2 V
VE1 =VE2 = V CC(DR) - 0.2 V 30 µA
Data Retention Setup Time tCDR tsu(DR) See Dat a Retention
Waveforms (below ) 0ns
Operating Recovery Time tRtrec tcR ns
Data Retention Mode E 1 - cont ro lled
Data Retention
2.3 V
tsu(DR) trec
VCC
E1
VCC(DR) 1.5 V
0 V
2.0 V
2.0 V
Data Re te ntio n Mode E2 - cont r olled
VE2(DR) VCC(DR) - 0.2 V or VE2(DR) 0.2 V
VCC(DR) - 0.2 V VE1(DR) VCC(DR) + 0.2 V
0.8 V
0.8 V
2.3 V
0 V
VCC
VE1(DR) VCC(DR) - 0.2 V or VE1(DR) 0.2 V
VE2(DR) 0.2 V
trec
tDR
VCC(DR) 1.5 V
Data Retention E2
Data Retention Mode
6 November 01, 200 1
UL62H1708B Preliminary
Capacitance Conditions Symbol Min. Max. Unit
Input Capaci t ance VCC
VI
f
Ta
= 2.5 V
= VSS
= 1 MHz
= 25 °C
CI7pF
Output Capacitance Co7pF
IC Code Nu mbers
UL62H1708B SA35
Type
Package
S = SOP32 300 mil
S1 = SOP32 330 m il
Oper ating Temp eratu re Rang e
K = -40 to 85 °C
A = -40 to 125 °C
Access Time
35 = 35 ns
55 = 55 ns
The date of manufacture is given by the l as t 4 digits of the m ar k, the first 2 digit s indicating the year , and
the last 2 di gits t he calendar week.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Test Conf igur ation for Funct iona l Ch eck
VIH
VIL
VSS
VCC
2.5 V
481
255
VO
1) In measurement of tdis(E),tdis(W), t en(E), ten(W), ten(G) th e capacitance is 5 p F.
Input level according to the
rel ev a nt tes t me as urem en t
Simultaneous measure-
m ent of al l 8 output pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
E1
E2
W
G
All pins not under test must be connected with ground by capacitors.
30 pF1
7 November 01, 2001
UL62H1708B
Preliminary
Previous Data Valid Ou tp ut Data Val id
Ad dress Valid
Read Cycle 1: Ai-con trolled (during Read Cycle : E1 = G = VIL, W = E2 = VIH)
Read Cycle 2: G-, E1, E2-con t rol led (dur in g R ea d Cy cl e : W = VIH)
ta(A)
tcR
tv(A)
Ai
DQi
Output
tcR
High-Z
Ad dr e s se s Valid
Ai
E1
E2
G
DQi
Output
tdis(E)
tsu(A) ta(E)
tsu(A)
ten(E)
ten(E)
ten(G)
ta(G)
ta(E) tdis(E)
tdis(G)
Output Data Valid
tPD*
tPU*
ICC(OP)
ICC(SB)
* The same applies to E1
50 % 50 %
Write Cycl e1: W-controlled
th(D)
Ai
E1
E2
W
DQi
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A)
tsu(E)
tsu(D)
tdis(W) ten(W)
Ad dr e s se s Valid
High-Z
Input Input Data Valid
8 November 01, 200 1
UL62H1708B Preliminary
Write Cycle 2: E1-controlled
tsu(A)
th(D)
Ai
E1
E2
W
DQi
Input
G
DQi
Output
tcW
tw(E) th(A)
tsu(W)
tsu(E)
tsu(D)
tdis(W)
ten(E)
Addresse s Vali d
Input Data Valid
High-Z
tdis(G)
Write Cycle 3 (E2-co ntro lled)
High-Z
Input Dat a Valid
th(D)
tsu(W)
tw(E)
tsu(D)
tcW
Addresse s Vali d
tsu(A)
tsu(E) th(A)
ten(E) tdis(W)
Ai
E1
E2
W
DQi
Input
G
DQi
Output tdis(G)
L- to H- leve l undefined H- to L-le ve l
The informat ion describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden AG
Grenzstra ße 28 D-01109 Dresden P. O . B. 80 01 34 D-01101 Dresden Germany
Phone: +49 351 8822 306 Fax: +49 351 8822 337 Email: sales@zmd.de http://www.zmd.de
November 01, 2001
UL62H1708B
Preliminary
LIFE S U PP O R T POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or o ther application s intended to support or sustain life, or f or any othe r application in which
the failure of the ZMD product could create a situation wher e personal injury or death may occur.
Componen ts used in life-s upport devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The inform ation in this docum ent des cribes t he t ype of comp onent and sh all not be c onsidere d as ass ured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent Z MD’s warranty on any product bey ond that set forth in its standard terms and
condition s of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.