LM3940 www.ti.com SNVS114D - MAY 2004 - REVISED JULY 2007 LM3940 1A Low Dropout Regulator for 5V to 3.3V Conversion Check for Samples: LM3940 FEATURES * 1 * * * * * 2 Output voltage specified over temperature Excellent load regulation Guaranteed 1A output current Requires only one external component Built-in protection against excess temperature Short circuit protected APPLICATIONS * * Laptop/Desktop Computers Logic Systems DESCRIPTION The LM3940 is a 1A low dropout regulator designed to provide 3.3V from a 5V supply. The LM3940 is ideally suited for systems which contain both 5V and 3.3V logic, with prime power provided from a 5V bus. Because the LM3940 is a true low dropout regulator, it can hold its 3.3V output in regulation with input voltages as low as 4.5V. The T0-220 package of the LM3940 means that in most applications the full 1A of load current can be delivered without using an additional heatsink. The surface mount TO-263 package uses minimum board space, and gives excellent power dissipation capability when soldered to a copper plane on the PC board. Typical Application *Required if regulator is located more than 1 from the power supply filter capacitor or if battery power is used. **See Application Hints. Connection Diagram/Ordering Information Figure 1. 3-Lead TO-220 Package(Front View) Order Part Number LM3940IT-3.3 NSC Drawing Number TO3B Figure 2. 3-Lead TO-263 Package (Front View) Order Part Number LM3940IS-3.3 NSC Drawing Number TS3B 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2007, Texas Instruments Incorporated LM3940 SNVS114D - MAY 2004 - REVISED JULY 2007 www.ti.com Figure 3. 3-Lead SOT-223 (Front View) Order Part Number LM3940IMP-3.3 Package Marked L52B NSC Drawing Number MP04A Figure 4. 16-Lead Ceramic Dual-in-Line Package (Top View) Order Part Number LM3940J-3.3-QML 5962-9688401QEA NSC Drawing Number J16A Figure 5. 16-Lead Ceramic Surface-Mount Package (Top View) Order Part Number LM3940WG-3.3-QML 5962-9688401QXA NSC Drawing Number WG16A 8-Lead LLP A. Pin 2 and pin 7 are fused to center DAP. B. Pin 5 and 6 need to be tied together on PCB board. Figure 6. (Top View)(A)(B) Order Part Number LM3940LD-3.3 NSC Drawing Number LDC08A 2 Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 LM3940 www.ti.com SNVS114D - MAY 2004 - REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) -65C to +150C Storage Temperature Range Lead Temperature (Soldering, 5 seconds) 260C (2) Internally Limited Input Supply Voltage 7.5V Power Dissipation ESD Rating (1) (2) (3) (3) 2 kV Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. The value of JA (for devices in still air with no heatsink) is 60C/W for the TO-220 package, 80C/W for the TO-263 package, and 174C/W for the SOT-223 package. The effective value of JA can be reduced by using a heatsink (see Application Hints for specific information on heatsinking). The value of JA for the LLP package is specifically dependant on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. The JA rating for the LLP is with a JESD51-7 test board having 6 thermal vias under the exposed pad. ESD rating is based on the human body model: 100 pF discharged through 1.5 k. Operating Ratings (1) -40C to +125C Junction Temperature Range, TJ Input Supply Voltage, VIN(MIN) (1) VO + VDO Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 3 LM3940 SNVS114D - MAY 2004 - REVISED JULY 2007 www.ti.com Electrical Characteristics Limits in standard typeface are for TJ = 25C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = 5V, IL = 1A, COUT = 33 F. Symbol Parameter VO (1) (2) ZO IQ en VDO IL(SC) (1) (2) 4 Conditions Typical LM3940 (1) min max 3.20 3.13 3.40 3.47 Output Voltage 5 mA IL 1A 3.3 Line Regulation IL = 5 mA 4.5V VIN 5.5V 20 40 50 80 Units V mV Load Regulation 50 mA IL 1A 35 Output Impedance IL (DC) = 100 mA IL (AC) = 20 mA (rms) f = 120 Hz 35 4.5V VIN 5.5V IL = 5 mA 10 15 20 VIN = 5V IL = 1A 110 200 250 BW = 10 Hz-100 kHz IL = 5 mA 150 IL = 1A 0.5 0.8 1.0 V IL = 100 mA 110 150 200 mV RL = 0 1.7 Quiescent Current Output Noise Voltage Dropout Voltage m V (rms) (2) Short Circuit Current mA 1.2 A All limits guaranteed for TJ = 25C are 100% tested and are used to calculate Outgoing Quality Levels. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Dropout voltage is defined as the input-output differential voltage where the regulator output drops to a value that is 100 mV below the value that is measured at VIN = 5V. Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 LM3940 www.ti.com SNVS114D - MAY 2004 - REVISED JULY 2007 Thermal Performance Thermal Resistance, Junction-to-Case, JC Thermal Resistance, Junction-to-Ambient, JA 3-Lead TO-220 4 C/W 3-Lead TO-263 4 C/W 8-Lead LLP 6 C/W 3-Lead TO-220 60 C/W 3-Lead TO-263 80 C/W 35 C/W 8-Lead LLP (1) (1) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. The value of JA (for devices in still air with no heatsink) is 60C/W for the TO-220 package, 80C/W for the TO-263 package, and 174C/W for the SOT-223 package. The effective value of JA can be reduced by using a heatsink (see Application Hints for specific information on heatsinking). The value of JA for the LLP package is specifically dependant on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. The JA rating for the LLP is with a JESD51-7 test board having 6 thermal vias under the exposed pad. Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 5 LM3940 SNVS114D - MAY 2004 - REVISED JULY 2007 www.ti.com Typical Performance Characteristics 6 Dropout Voltage Dropout Voltage vs. Temperature Output Voltage vs. Temperature Quiescent Current vs. Temperature Quiescent Current vs. VIN Quiescent Current vs. Load Line Transient Response Load Transient Response Ripple Rejection Low Voltage Behavior Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 LM3940 www.ti.com SNVS114D - MAY 2004 - REVISED JULY 2007 Typical Performance Characteristics (continued) Output Impedance Peak Output Current Application Hints EXTERNAL CAPACITORS The output capacitor is critical to maintaining regulator stability, and must meet the required conditions for both ESR (Equivalent Series Resistance) and minimum amount of capacitance. MINIMUM CAPACITANCE: The minimum output capacitance required to maintain stability is 33 F (this value may be increased without limit). Larger values of output capacitance will give improved transient response. ESR LIMITS: The ESR of the output capacitor will cause loop instability if it is too high or too low. The acceptable range of ESR plotted versus load current is shown in Figure 7. It is essential that the output capacitor meet these requirements, or oscillations can result. Figure 7. ESR Limits It is important to note that for most capacitors, ESR is specified only at room temperature. However, the designer must ensure that the ESR will stay inside the limits shown over the entire operating temperature range for the design. For aluminum electrolytic capacitors, ESR will increase by about 30X as the temperature is reduced from 25C to -40C. This type of capacitor is not well-suited for low temperature operation. Solid tantalum capacitors have a more stable ESR over temperature, but are more expensive than aluminum electrolytics. A cost-effective approach sometimes used is to parallel an aluminum electrolytic with a solid Tantalum, with the total capacitance split about 75/25% with the Aluminum being the larger value. If two capacitors are paralleled, the effective ESR is the parallel of the two individual values. The "flatter" ESR of the Tantalum will keep the effective ESR from rising as quickly at low temperatures. HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible operating conditions, the junction temperature must be within the range specified under Absolute Maximum Ratings. Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 7 LM3940 SNVS114D - MAY 2004 - REVISED JULY 2007 www.ti.com To determine if a heatsink is required, the power dissipated by the regulator, PD, must be calculated. Figure 8 shows the voltages and currents which are present in the circuit, as well as the formula for calculating the power dissipated in the regulator: IIN = IL + IG PD = (VIN - VOUT) IL + (VIN) IG Figure 8. Power Dissipation Diagram The next parameter which must be calculated is the maximum allowable temperature rise, TR (max). This is calculated by using the formula: TR (max) = TJ (max) - TA (max) Where: TJ (max) is the maximum allowable junction temperature, which is 125C for commercial grade parts. TA (max) is the maximum ambient temperature which will be encountered in the application. Using the calculated values for TR(max) and PD, the maximum allowable value for the junction-to-ambient thermal resistance, (JA), can now be found: (JA) = TR (max)/PD IMPORTANT: If the maximum allowable value for (JA) is found to be 60C/W for the TO-220 package, 80C/W for the TO-263 package, or 174C/W for the SOT-223 package, no heatsink is needed since the package alone will dissipate enough heat to satisfy these requirements. If the calculated value for (JA)falls below these limits, a heatsink is required. HEATSINKING TO-220 PACKAGE PARTS The TO-220 can be attached to a typical heatsink, or secured to a copper plane on a PC board. If a copper plane is to be used, the values of (JA) will be the same as shown in the HEATSINKING TO-263 section for the TO-263. If a manufactured heatsink is to be selected, the value of heatsink-to-ambient thermal resistance, (H-A), must first be calculated: (H-A) = (JA) - (C-H) - (J-C) Where: (J-C) is defined as the thermal resistance from the junction to the surface of the case. A value of 4C/W can be assumed for (J-C) for this calculation. (C-H) is defined as the thermal resistance between the case and the surface of the heatsink. The value of (C-H) will vary from about 1.5C/W to about 2.5C/W (depending on method of attachment, insulator, etc.). If the exact value is unknown, 2C/W should be assumed for (C-H). When a value for (H-A) is found using the equation shown above, a heatsink must be selected that has a value that is less than or equal to this number. (H-A) is specified numerically by the heatsink manufacturer in the catalog, or shown in a curve that plots temperature rise vs. power dissipation for the heatsink. HEATSINKING TO-263 AND SOT-223 PACKAGE PARTS Both the TO-263 ("S") and SOT-223 ("MP") packages use a copper plane on the PCB and the PCB itself as a heatsink. To optimize the heat sinking ability of the plane and PCB, solder the tab of the package to the plane. Figure 9 shows for the TO-263 the measured values of (JA) for different copper area sizes using a typical PCB with 1 ounce copper and no solder mask over the copper area used for heatsinking. 8 Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 LM3940 www.ti.com SNVS114D - MAY 2004 - REVISED JULY 2007 Figure 9. (JA) vs. Copper (1 ounce) Area for the TO-263 Package As shown in Figure 9, increasing the copper area beyond 1 square inch produces very little improvement. It should also be observed that the minimum value of (JA) for the TO-263 package mounted to a PCB is 32C/W. As a design aid, Figure 10 shows the maximum allowable power dissipation compared to ambient temperature for the TO-263 device (assuming (JA) is 35C/W and the maximum junction temperature is 125C). Figure 10. Maximum Power Dissipation vs. TAMB for the TO-263 Package Figure 11 and Figure 12 show the information for the SOT-223 package. Figure 12 assumes a (JA) of 74C/W for 1 ounce copper and 51C/W for 2 ounce copper and a maximum junction temperature of 125C. Figure 11. (JA) vs. Copper (2 ounce) Area for the SOT-223 Package Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 9 LM3940 SNVS114D - MAY 2004 - REVISED JULY 2007 www.ti.com Figure 12. Maximum Power Dissipation vs. TAMB for the SOT-223 Package Please see AN1028 for power enhancement techniques to be used with the SOT-223 package. 10 Submit Documentation Feedback Copyright (c) 2004-2007, Texas Instruments Incorporated Product Folder Links: LM3940 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) LM3940IMP-3.3 ACTIVE SOT-223 DCY 4 1000 TBD CU SNPB Level-1-260C-UNLIM LM3940IMP-3.3/NOPB ACTIVE SOT-223 DCY 4 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3940IMPX-3.3 ACTIVE SOT-223 DCY 4 2000 TBD CU SNPB Level-1-260C-UNLIM LM3940IMPX-3.3/NOPB ACTIVE SOT-223 DCY 4 2000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3940IS-3.3 ACTIVE DDPAK/ TO-263 KTT 3 45 TBD CU SNPB Level-3-235C-168 HR LM3940IS-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 3 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR LM3940ISX-3.3 ACTIVE DDPAK/ TO-263 KTT 3 500 TBD CU SNPB Level-3-235C-168 HR LM3940ISX-3.3/NOPB ACTIVE DDPAK/ TO-263 KTT 3 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR LM3940IT-3.3 ACTIVE TO-220 NDE 3 45 TBD CU SNPB Level-1-NA-UNLIM LM3940IT-3.3/NOPB ACTIVE TO-220 NDE 3 45 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3940IMP-3.3 SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM3940IMP-3.3/NOPB SOT-223 DCY 4 1000 330.0 LM3940IMPX-3.3 SOT-223 DCY 4 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 16.4 7.0 7.5 2.2 12.0 16.0 LM3940IMPX-3.3/NOPB SOT-223 DCY 4 2000 Q3 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LM3940ISX-3.3 DDPAK/ TO-263 KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 LM3940ISX-3.3/NOPB DDPAK/ TO-263 KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3940IMP-3.3 SOT-223 DCY 4 1000 349.0 337.0 45.0 LM3940IMP-3.3/NOPB SOT-223 DCY 4 1000 349.0 337.0 45.0 LM3940IMPX-3.3 SOT-223 DCY 4 2000 354.0 340.0 35.0 LM3940IMPX-3.3/NOPB SOT-223 DCY 4 2000 354.0 340.0 35.0 LM3940ISX-3.3 DDPAK/TO-263 KTT 3 500 358.0 343.0 63.0 LM3940ISX-3.3/NOPB DDPAK/TO-263 KTT 3 500 358.0 343.0 63.0 Pack Materials-Page 2 MECHANICAL DATA NDE0003B www.ti.com MECHANICAL DATA MPDS094A - APRIL 2001 - REVISED JUNE 2002 DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE 6,70 (0.264) 6,30 (0.248) 3,10 (0.122) 2,90 (0.114) 4 0,10 (0.004) M 3,70 (0.146) 3,30 (0.130) 7,30 (0.287) 6,70 (0.264) Gauge Plane 1 2 0,84 (0.033) 0,66 (0.026) 2,30 (0.091) 4,60 (0.181) 1,80 (0.071) MAX 3 0-10 0,10 (0.004) M 0,25 (0.010) 0,75 (0.030) MIN 1,70 (0.067) 1,50 (0.059) 0,35 (0.014) 0,23 (0.009) Seating Plane 0,08 (0.003) 0,10 (0.0040) 0,02 (0.0008) 4202506/B 06/2002 NOTES: A. B. C. D. All linear dimensions are in millimeters (inches). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC TO-261 Variation AA. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA KTT0003B TS3B (Rev F) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. 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