LM3940
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SNVS114D –MAY 2004–REVISED JULY 2007
LM3940 1A Low Dropout Regulator for 5V to 3.3V Conversion
Check for Samples: LM3940
1FEATURES • Short circuit protected
2• Output voltage specified over temperature APPLICATIONS
• Excellent load regulation • Laptop/Desktop Computers
• Guaranteed 1A output current • Logic Systems
• Requires only one external component
• Built-in protection against excess temperature
DESCRIPTION
The LM3940 is a 1A low dropout regulator designed to provide 3.3V from a 5V supply.
The LM3940 is ideally suited for systems which contain both 5V and 3.3V logic, with prime power provided from
a 5V bus.
Because the LM3940 is a true low dropout regulator, it can hold its 3.3V output in regulation with input voltages
as low as 4.5V.
The T0-220 package of the LM3940 means that in most applications the full 1A of load current can be delivered
without using an additional heatsink.
The surface mount TO-263 package uses minimum board space, and gives excellent power dissipation capability
when soldered to a copper plane on the PC board.
Typical Application
*Required if regulator is located more than 1″from the power supply filter capacitor or if battery power is used.
**See Application Hints.
Connection Diagram/Ordering Information
Figure 1. 3-Lead TO-220 Package(Front View)
Order Part Number LM3940IT-3.3
NSC Drawing Number TO3B
Figure 2. 3-Lead TO-263 Package
(Front View)
Order Part Number LM3940IS-3.3
NSC Drawing Number TS3B
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM3940
SNVS114D –MAY 2004–REVISED JULY 2007
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Figure 3. 3-Lead SOT-223
(Front View)
Order Part Number LM3940IMP-3.3
Package Marked L52B
NSC Drawing Number MP04A
Figure 4. 16-Lead Ceramic Dual-in-Line Package
(Top View)
Order Part Number LM3940J-3.3-QML
5962-9688401QEA
NSC Drawing Number J16A
Figure 5. 16-Lead Ceramic Surface-Mount Package
(Top View)
Order Part Number LM3940WG-3.3-QML
5962-9688401QXA
NSC Drawing Number WG16A
8-Lead LLP
A. Pin 2 and pin 7 are fused to center DAP.
B. Pin 5 and 6 need to be tied together on PCB board.
Figure 6. (Top View)(A)(B)
Order Part Number LM3940LD-3.3
NSC Drawing Number LDC08A
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 5 seconds) 260°C
Power Dissipation (2) Internally Limited
Input Supply Voltage 7.5V
ESD Rating (3) 2 kV
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
(2) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal shutdown. The value of θJA (for devices in still air with no heatsink) is 60°C/W for the
TO-220 package, 80°C/W for the TO-263 package, and 174°C/W for the SOT-223 package. The effective value of θJA can be reduced
by using a heatsink (see Application Hints for specific information on heatsinking). The value of θJA for the LLP package is specifically
dependant on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power
dissipation for the LLP package, refer to Application Note AN-1187. The θJA rating for the LLP is with a JESD51-7 test board having 6
thermal vias under the exposed pad.
(3) ESD rating is based on the human body model: 100 pF discharged through 1.5 kΩ.
Operating Ratings (1)
Junction Temperature Range, TJ−40°C to +125°C
Input Supply Voltage, VIN(MIN) VO+ VDO
(1) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply
when operating the device outside of its rated operating conditions.
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Electrical Characteristics
Limits in standard typeface are for TJ= 25°C, and limits in boldface type apply over the full operating temperature range.
Unless otherwise specified: VIN = 5V, IL= 1A, COUT = 33 μF.
Symbol Parameter Conditions Typical LM3940 (1) Units
min max
3.20 3.40
VOOutput Voltage 5 mA ≤IL≤1A 3.3 V
3.13 3.47
IL= 5 mA
Line Regulation 20 40
4.5V ≤VIN ≤5.5V
(1) mV
50
Load Regulation 50 mA ≤IL≤1A 35 80
(2) IL(DC) = 100 mA
ZOOutput Impedance IL(AC) = 20 mA (rms) 35 mΩ
f = 120 Hz
4.5V ≤VIN ≤5.5V 15
10
IL= 5 mA 20
IQQuiescent Current mA
VIN = 5V 200
110
IL= 1A 250
BW = 10 Hz–100 kHz
enOutput Noise Voltage 150 μV (rms)
IL= 5 mA 0.8
IL= 1A 0.5 V
1.0
Dropout Voltage
VDO (2) 150
IL= 100 mA 110 mV
200
IL(SC) Short Circuit Current RL= 0 1.7 1.2 A
(1) All limits guaranteed for TJ= 25°C are 100% tested and are used to calculate Outgoing Quality Levels. All limits at temperature
extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
(2) Dropout voltage is defined as the input-output differential voltage where the regulator output drops to a value that is 100 mV below the
value that is measured at VIN = 5V.
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Thermal Performance 3-Lead TO-220 4 °C/W
Thermal Resistance, Junction-to-Case, θJC 3-Lead TO-263 4 °C/W
8-Lead LLP 6 °C/W
3-Lead TO-220 60 °C/W
Thermal Resistance, Junction-to-Ambient, θJA 3-Lead TO-263 80 °C/W
8-Lead LLP (1) 35 °C/W
(1) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. Exceeding the maximum allowable power dissipation will cause excessive die
temperature, and the regulator will go into thermal shutdown. The value of θJA (for devices in still air with no heatsink) is 60°C/W for the
TO-220 package, 80°C/W for the TO-263 package, and 174°C/W for the SOT-223 package. The effective value of θJA can be reduced
by using a heatsink (see Application Hints for specific information on heatsinking). The value of θJA for the LLP package is specifically
dependant on PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power
dissipation for the LLP package, refer to Application Note AN-1187. The θJA rating for the LLP is with a JESD51-7 test board having 6
thermal vias under the exposed pad.
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Typical Performance Characteristics Dropout Voltage
vs.
Dropout Voltage Temperature
Output Voltage Quiescent Current
vs. vs.
Temperature Temperature
Quiescent Current Quiescent Current
vs. vs.
VIN Load
Line Transient Response Load Transient Response
Ripple Rejection Low Voltage Behavior
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Typical Performance Characteristics (continued)
Output Impedance Peak Output Current
Application Hints
EXTERNAL CAPACITORS
The output capacitor is critical to maintaining regulator stability, and must meet the required conditions for both
ESR (Equivalent Series Resistance) and minimum amount of capacitance.
MINIMUM CAPACITANCE:
The minimum output capacitance required to maintain stability is 33 μF (this value may be increased without
limit). Larger values of output capacitance will give improved transient response.
ESR LIMITS:
The ESR of the output capacitor will cause loop instability if it is too high or too low. The acceptable range of
ESR plotted versus load current is shown in Figure 7.It is essential that the output capacitor meet these
requirements, or oscillations can result.
Figure 7. ESR Limits
It is important to note that for most capacitors, ESR is specified only at room temperature. However, the designer
must ensure that the ESR will stay inside the limits shown over the entire operating temperature range for the
design.
For aluminum electrolytic capacitors, ESR will increase by about 30X as the temperature is reduced from 25°C to
−40°C. This type of capacitor is not well-suited for low temperature operation.
Solid tantalum capacitors have a more stable ESR over temperature, but are more expensive than aluminum
electrolytics. A cost-effective approach sometimes used is to parallel an aluminum electrolytic with a solid
Tantalum, with the total capacitance split about 75/25% with the Aluminum being the larger value.
If two capacitors are paralleled, the effective ESR is the parallel of the two individual values. The “flatter” ESR of
the Tantalum will keep the effective ESR from rising as quickly at low temperatures.
HEATSINKING
A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of
the application. Under all possible operating conditions, the junction temperature must be within the range
specified under Absolute Maximum Ratings.
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To determine if a heatsink is required, the power dissipated by the regulator, PD, must be calculated.
Figure 8 shows the voltages and currents which are present in the circuit, as well as the formula for calculating
the power dissipated in the regulator:
IIN = IL+ IG
PD= (VIN −VOUT) IL+ (VIN) IG
Figure 8. Power Dissipation Diagram
The next parameter which must be calculated is the maximum allowable temperature rise, TR(max). This is
calculated by using the formula:
TR(max) = TJ(max) −TA(max)
Where: TJ(max)is the maximum allowable junction temperature, which is 125°C for commercial grade parts.
TA(max)is the maximum ambient temperature which will be encountered in the application.
Using the calculated values for TR(max) and PD, the maximum allowable value for the junction-to-ambient
thermal resistance, θ(JA), can now be found:
θ(JA) = TR(max)/PD
IMPORTANT: If the maximum allowable value for θ(JA) is found to be ≥60°C/W for the TO-220 package, ≥
80°C/W for the TO-263 package, or ≥174°C/W for the SOT-223 package, no heatsink is needed since the
package alone will dissipate enough heat to satisfy these requirements.
If the calculated value for θ(JA)falls below these limits, a heatsink is required.
HEATSINKING TO-220 PACKAGE PARTS
The TO-220 can be attached to a typical heatsink, or secured to a copper plane on a PC board. If a copper plane
is to be used, the values of θ(JA) will be the same as shown in the HEATSINKING TO-263 section for the TO-263.
If a manufactured heatsink is to be selected, the value of heatsink-to-ambient thermal resistance, θ(H−A), must
first be calculated:
θ(H−A) =θ(JA) − θ(C−H) − θ(J−C)
Where: θ(J−C)is defined as the thermal resistance from the junction to the surface of the case. A value of 4°C/W
can be assumed for θ(J−C) for this calculation.
θ(C−H) is defined as the thermal resistance between the case and the surface of the heatsink. The value of
θ(C−H) will vary from about 1.5°C/W to about 2.5°C/W (depending on method of attachment, insulator, etc.).
If the exact value is unknown, 2°C/W should be assumed for θ(C−H).
When a value for θ(H−A) is found using the equation shown above, a heatsink must be selected that has a value
that is less than or equal to this number.
θ(H−A) is specified numerically by the heatsink manufacturer in the catalog, or shown in a curve that plots
temperature rise vs. power dissipation for the heatsink.
HEATSINKING TO-263 AND SOT-223 PACKAGE PARTS
Both the TO-263 (“S”) and SOT-223 (“MP”) packages use a copper plane on the PCB and the PCB itself as a
heatsink. To optimize the heat sinking ability of the plane and PCB, solder the tab of the package to the plane.
Figure 9 shows for the TO-263 the measured values of θ(JA) for different copper area sizes using a typical PCB
with 1 ounce copper and no solder mask over the copper area used for heatsinking.
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Figure 9. θ(JA) vs. Copper (1 ounce) Area for the TO-263 Package
As shown in Figure 9, increasing the copper area beyond 1 square inch produces very little improvement. It
should also be observed that the minimum value of θ(JA) for the TO-263 package mounted to a PCB is 32°C/W.
As a design aid, Figure 10 shows the maximum allowable power dissipation compared to ambient temperature
for the TO-263 device (assuming θ(JA) is 35°C/W and the maximum junction temperature is 125°C).
Figure 10. Maximum Power Dissipation vs. TAMB for the TO-263 Package
Figure 11 and Figure 12 show the information for the SOT-223 package. Figure 12 assumes a θ(JA) of 74°C/W
for 1 ounce copper and 51°C/W for 2 ounce copper and a maximum junction temperature of 125°C.
Figure 11. θ(JA) vs. Copper (2 ounce) Area for the SOT-223 Package
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Figure 12. Maximum Power Dissipation vs. TAMB for the SOT-223 Package
Please see AN1028 for power enhancement techniques to be used with the SOT-223 package.
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PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Samples
(Requires Login)
LM3940IMP-3.3 ACTIVE SOT-223 DCY 4 1000 TBD CU SNPB Level-1-260C-UNLIM
LM3940IMP-3.3/NOPB ACTIVE SOT-223 DCY 4 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
LM3940IMPX-3.3 ACTIVE SOT-223 DCY 4 2000 TBD CU SNPB Level-1-260C-UNLIM
LM3940IMPX-3.3/NOPB ACTIVE SOT-223 DCY 4 2000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
LM3940IS-3.3 ACTIVE DDPAK/
TO-263 KTT 3 45 TBD CU SNPB Level-3-235C-168 HR
LM3940IS-3.3/NOPB ACTIVE DDPAK/
TO-263 KTT 3 45 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR
LM3940ISX-3.3 ACTIVE DDPAK/
TO-263 KTT 3 500 TBD CU SNPB Level-3-235C-168 HR
LM3940ISX-3.3/NOPB ACTIVE DDPAK/
TO-263 KTT 3 500 Pb-Free (RoHS
Exempt) CU SN Level-3-245C-168 HR
LM3940IT-3.3 ACTIVE TO-220 NDE 3 45 TBD CU SNPB Level-1-NA-UNLIM
LM3940IT-3.3/NOPB ACTIVE TO-220 NDE 3 45 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Nov-2012
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM3940IMP-3.3 SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3
LM3940IMP-3.3/NOPB SOT-223 DCY 4 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3
LM3940IMPX-3.3 SOT-223 DCY 4 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3
LM3940IMPX-3.3/NOPB SOT-223 DCY 4 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3
LM3940ISX-3.3 DDPAK/
TO-263 KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
LM3940ISX-3.3/NOPB DDPAK/
TO-263 KTT 3 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Nov-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM3940IMP-3.3 SOT-223 DCY 4 1000 349.0 337.0 45.0
LM3940IMP-3.3/NOPB SOT-223 DCY 4 1000 349.0 337.0 45.0
LM3940IMPX-3.3 SOT-223 DCY 4 2000 354.0 340.0 35.0
LM3940IMPX-3.3/NOPB SOT-223 DCY 4 2000 354.0 340.0 35.0
LM3940ISX-3.3 DDPAK/TO-263 KTT 3 500 358.0 343.0 63.0
LM3940ISX-3.3/NOPB DDPAK/TO-263 KTT 3 500 358.0 343.0 63.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Nov-2012
Pack Materials-Page 2
MECHANICAL DATA
NDE0003B
www.ti.com
MECHANICAL DATA
MPDS094A – APRIL 2001 – REVISED JUNE 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCY (R-PDSO-G4) PLASTIC SMALL-OUTLINE
4202506/B 06/2002
6,30 (0.248)
6,70 (0.264)
2,90 (0.114)
3,10 (0.122)
6,70 (0.264)
7,30 (0.287) 3,70 (0.146)
3,30 (0.130)
0,02 (0.0008)
0,10 (0.0040)
1,50 (0.059)
1,70 (0.067)
0,23 (0.009)
0,35 (0.014)
1 2 3
4
0,66 (0.026)
0,84 (0.033)
1,80 (0.071) MAX
Seating Plane
0°–10°
Gauge Plane
0,75 (0.030) MIN
0,25 (0.010)
0,08 (0.003)
0,10 (0.004) M
2,30 (0.091)
4,60 (0.181) M
0,10 (0.004)
NOTES: A. All linear dimensions are in millimeters (inches).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC TO-261 Variation AA.
MECHANICAL DATA
KTT0003B
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BOTTOM SIDE OF PACKAGE
TS3B (Rev F)
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