HV219 HV219 Initial Release Low Charge Injection 8-Channel High Voltage Analog Switch Features ! ! ! ! ! ! ! ! ! ! ! General Description HVCMOS technology for high performance Very low quiescent power dissipation-10A Output On-resistance typically 11 Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Serial shift register logic control with latches Flexible operating supply voltages Surface mount packages The Supertex HV219 is a low switch resistance, low charge injection 8-channel 200V analog switch integrated circuit (IC) intended primarily for medical ultrasound imaging. The device can also be used for NDE, non-destructive evaluation applications. The HV219 is a lower switch resistance, 11ohms versus 22ohms, version of the Supertex HV20220 device. The lower switch resistance will help reduce insertion loss. It has the same pin configuration as that of the Supertex HV20220PJ and the HV20220FG. The device is manufactured using Supertex's HVCMOS (high voltage CMOS) technology with high voltage bilateral DMOS structures for the outputs and low voltage CMOS logic for the input control. The outputs are configured as eight independent single pole single throw 11 ohms analog switches. The input logic is an 8bit serial to parallel shift register followed by an 8-bit parallel latch. The switch states are determined by the data in the latch. Logic high will correspond to a closed switch and logic low as an opened switch. Applications ! ! Medical Ultrasound Imaging Non-Destructive Evaluation The HV219 is designed to operate on various combinations of high voltage supplies. For example the VPP and VNN supplies can be: +40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to maximize the signal voltage for uni-polar negative, bi-polar, or unipolar positive. Block Diagram LATCHES LEVEL SHIFTERS OUTPUT SWITCHES D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW3 D LE CL SW4 D LE CL SW5 D LE CL SW6 D LE CL SW7 DIN CLK 8 BIT SHIFT REGISTER DOUT VDD GND LE CL VNN VPP A042705 Rev. 2 110504 1 HV219 Ordering Information VPP-VNN 200V Maximum Analog Switch Voltage 180VP-P Package Options 28-lead plastic chip carrier PLCC 48-lead TQFP HV219PJ HV219FG Die HV219X Absolute Maximum Ratings* VDD Logic supply VPP-VNN differential supply VPP Positive supply VNN Negative supply Logic input voltage Analog signal range Peak analog signal current Storage temperature Power dissipation -0.5V to +15V 220V -0.5V to VNN+200V +0.5V to -200V -0.5V to VDD+0.3V VNN to VPP 3.0A -65C to +125C 28-Lead PLCC 1.2W 48 Lead TQFP 1.0W *Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions Symbol VDD VPP VNN VIH VIL VSIG TA Parameter Logic power supply Positive high voltage supply Negative high voltage supply Input logic voltage high Input logic voltage low Analog signal voltage peak to peak Operating free air temperature Value 4.5V to 13.2V 40V to VNN+200V -40V to -160V VDD-1.5V to VDD 0V to 1.5V VNN+10V to VPP-10V 0C to 70C 2 A042705 HV219 Electrical Characteristics DC Characteristics (over recommended operating conditions unless otherwise noted) Sym RONS RONS RONL ISOL IPPQ INNQ IPPQ INNQ fSW IPP INN IDD IDDQ ISOR ISINK CIN Parameter Small Signal Switch On-Resistance Min 0C Max 15 13 13 9 12 11 Small Signal Switch On-Resistance Matching Large Signal Switch On-Resistance Switch Off Leakage per Switch DC offset Switch off DC offset Switch on Quiescent VPP supply current Quiescent VNN supply current Quiescent VPP supply current Quiescent VNN supply current Switch output peak current Output switch frequency 20 +25C Typ 13 11 11 9 10 8 Max 19 14 14 12 13 13 5.0 20 +70C Min Max 24 16 15 14 15 14 20 8 Average VNN supply current Units Ohms % Ohms Conditions VPP = +40V ISIG = 5mA VNN = -160V ISIG = 200mA VPP = +100V ISIG = 5mA VNN = -100V ISIG = 200mA VPP = +160V ISIG = 5mA VNN = -40V ISIG = 200mA ISIG = 5mA, VPP = +100V, VNN = -100V VSIG = VPP-10V, ISIG = 1A 5.0 1.0 10 15 A VSIG = VPP-10V and VNN+10V 300 500 100 100 300 500 300 500 mV mV RLOAD = 100K RLOAD = 100K 10 50 A All switches off -10 -50 A All switches off 10 50 A All switches on, ISW = 5mA -10 -50 A All switches on, ISW = 5mA 3.0 2.0 50 2.0 A kHz 6.5 7.0 8.0 4.0 5.0 5.5 4.0 5.0 5.5 6.5 7.0 8.0 4.0 5.0 5.5 4.0 5.0 5.5 VSIG duty cycle < 0.1% Duty cycle = 50% VPP = +40V VNN = -160V VPP = +100V VNN = -100V All output VPP = +160V switches are turning On VNN = -40V and Off at VPP = +40V 50KHz with VNN = -160V no load. VPP = +100V VNN = -100V VPP = +160V VNN = -40V 4.0 4.0 4.0 mA fCLK = 5MHz, VDD = 5.0V 10 10 10 A All logic inputs are static VOUT = VDD-0.7V VOUT = 0.7V 10 mA mA pF 3.0 Average VPP supply current Average VDD supply current Quiescent VDD supply current Data out source current Data out sink current Logic input capacitance Min 0.45 0.45 0.45 0.45 0.70 0.70 10 0.40 0.40 10 3 mA mA A042705 HV219 Electrical Characteristics AC Characteristics (over recommended operating conditions, V Sym tSD Parameter Set Up Time Before LE Rises 0C Min Max 150 Min 150 150 150 DD =5.0V, unless otherwise noted) +25C Typ Max +70C Min Max 150 150 Unit s ns ns ns ns ns ns tWLE tDO twCL tSU tH Time Width of LE Clock Delay Time to Data out Time Width of CL Set Up Time Data to Clock Hold Time Data from Clock fCLK Clock Frequency 5.0 5.0 5.0 MHz tr,tf Clock rise and fall Times 50 50 50 ns Ton Turn on Time 5.0 5.0 5.0 s Toff Turn off Time 5.0 5.0 5.0 s 20 20 20 20 20 20 20 20 20 dv/dt KO Kcr Iid CSG(off) CSG(on) +VSPK 150 150 15 35 Maximum VSIG Slew Rate Off Isolation Switch Crosstalk Output Switch Isolation Diode Current Off Capacitance SW to Gnd On Capacitance SW to Gnd 150 150 15 35 -30 -30 -58 -58 -60 8.0 -33 25 60 -VSPK dB dB 300 14 40 20 50 -VSPK +VSPK -30 V/ns -58 300 14 40 150 150 20 35 25 60 150 200 150 Output Voltage Spike 200 +VSPK 150 -VSPK 200 14 40 300 mA 25 60 pF pF mV mV mV 1450 Q 1050 Charge Injection 550 4 Conditions pC 50% duty cycle, fDATA = fCLK/2 VSIG = VPP-10V, RLOAD = 10K VSIG = VPP-10V, RLOAD = 10K VPP = +40V, VNN = -160V VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V F = 5MHz, 1K//15pF load F = 5.0MHz, 50 load F = 5.0MHz, 50 load 300ns pulse width, 2.0% duty cycle 0V, f = 1MHz 0V, f = 1MHz VPP = +40V, VNN = -160V, RLOAD = 50ohm VPP = +100V, VNN = -100V, RLOAD = 50ohm VPP = +160V, VNN = -40V, RLOAD = 50ohm VPP = +40V, VNN = -160V, VSIG = 0V VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V A042705 HV219 Power Up/Down Sequence 1) Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for applications powering GND of the IC with different voltages. Vsig must always be at or in between VPP and VNN or floating during power up/down transition. Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms. 2) 3) Logic Truth Table Data in the 8-bit Shift Register D1 D2 D3 D4 D5 D6 D7 D0 L H L H L H L H L H L H L H X X X X Notes: 1. 2. X X X X X X X X L H X X X X LE CL L L L L L L L L L L L L L L L L H X L L L L L L L L L L L L L L L L L H SW0 OFF ON SW1 SW2 Output Switch State SW3 SW4 SW5 SW6 SW7 OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF OFF HOLD PREVIOUS STATE OFF OFF OFF OFF OFF OFF The eight switches operate independently. Serial data is clocked in on the L to H transition clock. 3. The switches go to a state retaining their present condition at the rising edge of the LE . 4. When LE is low, the shift register data flows through the latch. 5. 6. Shift register clocking has no effect on the switch states if LE is high. The clear input overrides all other inputs. Logic Timing Waveform DN-1 DN+1 DN DATA IN 50% LE 50% 50% 50% t WLE t SD 50% 50% CLOCK t t SU t DATA OUT DD 50% t VOUT OFF t ON OFF 90% (TYP) 10% ON CLR h 50% 50% t WCL 5 A042705 HV219 Test Circuits VPP -10V VPP -10V RL ISOL 10K VOUT VOUT 100K VNN +10V VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND TON /TOFF Test Circuit DC Offset ON/OFF Switch OFF Leakage 5V VIN = 10 VP-P @5MHz VIN = 10 VP-P @5MHz VSIG IID VOUT 50 NC VNN RL 50 VPP VPP VDD VNN VNN GND KO = 20Log 5V VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND VOUT VIN KCR = 20Log OFF Isolation Isolation Diode Current 5V VOUT VIN Crosstalk +VSPK VOUT VOUT VOUT -V SPK 1000pF 50 VSIG 1K VPP VPP VDD VNN VNN GND 5V RL VPP VPP VDD VNN VNN GND 5V Q = 1000pF x VOUT Charge Injection Output Voltage Spike 6 A042705 HV219 Pin Configuration 28-Pin J-lead Package Outline 0.450 0.005 (11.430 0.127) D1 Pin #1 B D 0.480 0.010 (12.192 0.254) 0.027 0.003 (0.6858 0.0762) 28 Pin J-Lead Pin Function 1 SW3 2 SW3 3 SW2 4 SW2 5 SW1 6 SW1 7 SW0 8 SW0 9 N/C 10 VPP 11 N/C 12 VNN 13 GND 14 VDD Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function N/C DIN CLK LE CL DOUT SW7 SW7 SW6 SW6 SW5 SW5 SW4 SW4 e 0.050 0.010 (1.270 0.254) 0.1725 0.0075 (4.3815 0.1905) A A2 0.020 min. (0.508) 0.410 0.010 (10.414 0.254) B.C. of Bend Radii Q 0.110 0.010 (2.794 0.254) 25 24 23 22 21 20 19 26 18 27 17 28 16 1 15 2 14 3 13 4 12 5 6 7 8 9 10 11 Measurement Legend = Top View 28-Pin J-Lead Package 7 Dimensions in Inches (Dimensions in Millimeters) A042705 HV219 Pin Configuration 48-Pin TQFP 0.024 0.008 (0.610 0.2032) D, E 0.354 0.010 (8.992 0.254) L 0.354 0.010 (8.992 0.254) Pin #1 0.275 0.004 (6.985 0.102) D1, E1 0 - 7 0.275 0.004 (6.985 0.1016) A A2 0.055 0.004 (1.397 0.102) 0.020 BSC (0.508) 0.059 0.004 (1.4986 0.102) 0.039 TYP. (0.991) 48-Pin TQFP Pin Function 1 SW5 2 N/C 3 SW4 4 N/C 5 SW4 6 N/C 7 N/C 8 SW3 9 N/C 10 SW3 11 N/C 12 SW2 13 N/C 14 SW2 15 N/C 16 SW1 17 N/C 18 SW1 19 N/C 20 SW0 21 N/C 22 SW0 23 N/C 24 VPP Pin 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Function VNN N/C N/C GND VDD N/C N/C N/C DIN CLK LE CLR DOUT N/C SW7 N/C SW7 N/C SW6 N/C SW6 N/C SW5 N/C Pin 1 Pin #1 HV219 Measurement Legend = Dimensions in Inches (Dimensions in Millimeters) Pin 12 top view 48-pin TQFP A042705 8 A042705