HV219
Rev. 2 110504
1
Low Charge Injection
8-Channel High Voltage Analog Switch
Features
! HVCMOS technology for high performance
! Very low quiescent power dissipation-10µA
! Output On-resistance typically 11
! Low parasitic capacitance
! DC to 10MHz analog signal frequency
! -60dB typical off-isolation at 5MHz
! CMOS logic circuitry for low power
! Excellent noise immunity
! Serial shift register logic control with latches
! Flexible operating supply voltages
! Surface mount packages
Applications
! Medical Ultrasound Imaging
! Non-Destructive Evaluation
General Description
The Supertex HV219 is a low switch resistance, low charge
injection 8-channel 200V analog switch integrated circuit (IC)
intended primarily for medical ultrasound imaging. The device can
also be used for NDE, non-destructive evaluation applications. The
HV219 is a lower switch resistance, 11ohms versus 22ohms,
version of the Supertex HV20220 device. The lower switch
resistance will help reduce insertion loss. It has the same pin
configuration as that of the Supertex HV20220PJ and the
HV20220FG.
The device is manufactured using Supertex’s HVCMOS (high
voltage CMOS) technology with high voltage bilateral DMOS
structures for the outputs and low voltage CMOS logic for the input
control. The outputs are configured as eight independent single
pole single throw 11 ohms analog switches. The input logic is an 8-
bit serial to parallel shift register followed by an 8-bit parallel latch.
The switch states are determined by the data in the latch. Logic
high will correspond to a closed switch and logic low as an opened
switch.
The HV219 is designed to operate on various combinations of high
voltage supplies. For example the VPP and VNN supplies can be:
+40V/-160V, +100V/-100V, or +160V/-40V. This allows the user to
maximize the signal voltage for uni-polar negative, bi-polar, or uni-
polar positive.
Block Diagram
HV219
Initial Release
A
04
2
705
SW0
D
LE
CL
LE CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
8 BIT
SHIFT
REGISTER
LEVEL
SHIFTERS
OUTPUT
SWITCHES
LATCHES
V
PP
V
NN
V
DD
D
OUT
D
IN
CLK
SW1
SW2
SW3
SW4
SW5
SW6
SW7
GND
HV219
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Ordering Information
Package Options
VPP-VNN
Maximum Analog
Switch Voltage 28-lead plastic chip carrier PLCC 48-lead TQFP Die
200V 180VP-P HV219PJ HV219FG HV219X
Absolute Maximum Ratings*
VDD Logic supply -0.5V to +15V
VPP-VNN differential supply 220V
VPP Positive supply -0.5V to VNN+200V
VNN Negative supply +0.5V to –200V
Logic input voltage -0.5V to VDD+0.3V
Analog signal range VNN to VPP
Peak analog signal current 3.0A
Storage temperature -65°C to +125°C
28-Lead PLCC 1.2W Power dissipation
48 Lead TQFP 1.0W
*Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level may
affect device reliability. All voltages are referenced to device ground.
Operating Conditions
Symbol Parameter Value
VDD Logic power supply 4.5V to 13.2V
VPP Positive high voltage supply 40V to VNN+200V
VNN Negative high voltage supply -40V to -160V
VIH Input logic voltage high VDD-1.5V to VDD
VIL Input logic voltage low 0V to 1.5V
VSIG Analog signal voltage peak to peak VNN+10V to VPP-10V
TA Operating free air temperature 0°C to 70°C
HV219
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Electrical Characteristics
DC Characteristics (over recommended operating conditions unless otherwise noted)
0°C +25°C +70°C
Sym Parameter Min Max Min Typ Max Min Max Units Conditions
15 13 19 24 ISIG = 5mA
13 11 14 16 ISIG = 200mA
VPP = +40V
VNN = -160V
13 11 14 15 ISIG = 5mA
9 9 12 14 ISIG = 200mA
VPP = +100V
VNN = -100V
12 10 13 15 ISIG = 5mA
RONS Small Signal Switch
On-Resistance
11 8 13 14
Ohms
ISIG = 200mA
VPP = +160V
VNN = -40V
RONS Small Signal Switch
On-Resistance Matching 20 5.0 20 20 %
ISIG = 5mA, VPP = +100V,
VNN = -100V
RONL Large Signal Switch
On-Resistance 8 Ohms V
SIG = VPP-10V, ISIG = 1A
ISOL Switch Off Leakage per
Switch 5.0 1.0 10 15 µA VSIG = VPP-10V and VNN+10V
DC offset Switch off 300 100 300 300 mV RLOAD = 100K
DC offset Switch on 500 100 500 500 mV RLOAD = 100K
IPPQ Quiescent VPP supply
current 10 50 µA All switches off
INNQ Quiescent VNN supply
current -10 -50 µA All switches off
IPPQ Quiescent VPP supply
current 10 50 µA All switches on, ISW = 5mA
INNQ Quiescent VNN supply
current -10 -50 µA All switches on, ISW = 5mA
Switch output peak current 3.0 3.0 2.0 2.0 A VSIG duty cycle < 0.1%
fSW Output switch frequency 50 kHz Duty cycle = 50%
6.5 7.0 8.0 VPP = +40V
VNN = -160V
4.0 5.0 5.5 VPP = +100V
VNN = -100V
IPP Average VPP supply
current
4.0 5.0 5.5
mA VPP = +160V
VNN = -40V
6.5 7.0 8.0 VPP = +40V
VNN = -160V
4.0 5.0 5.5 VPP = +100V
VNN = -100V
INN Average VNN supply
current
4.0 5.0 5.5
mA VPP = +160V
VNN = -40V
All output
switches are
turning On
and Off at
50KHz with
no load.
IDD Average VDD supply
current 4.0 4.0 4.0 mA fCLK = 5MHz, VDD = 5.0V
IDDQ Quiescent VDD supply
current 10 10 10 µA All logic inputs are static
ISOR Data out source current 0.45 0.45 0.70 0.40 mA VOUT = VDD-0.7V
ISINK Data out sink current 0.45 0.45 0.70 0.40 mA VOUT = 0.7V
CIN Logic input capacitance 10 10 10 pF
HV219
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Electrical Characteristics
AC Characteristics (over recommended operating conditions, VDD=5.0V, unless otherwise noted)
0°C +25°C +70°C Sym Parameter
Min Max Min Typ Max Min Max
Unit
s
Conditions
tSD Set Up Time Before LE Rises 150 150 150 ns
tWLE Time Width of LE 150 150 150 ns
tDO Clock Delay Time to Data out 150 150 150 ns
twCL Time Width of CL 150 150 150 ns
tSU Set Up Time Data to Clock 15 15 8.0 20 ns
tH Hold Time Data from Clock 35 35 35 ns
fCLK Clock Frequency 5.0 5.0 5.0 MHz
50% duty cycle,
fDATA = fCLK/2
tr,tf Clock rise and fall Times 50 50 50 ns
Ton Turn on Time 5.0 5.0 5.0 µs
VSIG = VPP-10V,
RLOAD = 10K
Toff Turn off Time 5.0 5.0 5.0 µs
VSIG = VPP-10V,
RLOAD = 10K
20 20 20 VPP = +40V,
VNN = -160V
20 20 20 VPP = +100V,
VNN = -100V
dv/dt Maximum VSIG Slew Rate
20 20 20
V/ns VPP = +160V,
VNN = -40V
-30 -30 -33 -30 F = 5MHz, 1K//15pF
load
KO Off Isolation
-58 -58 -58
dB
F = 5.0MHz, 50 load
Kcr Switch Crosstalk -60 dB
F = 5.0MHz, 50 load
Iid Output Switch Isolation Diode
Current 300 300 300 mA
300ns pulse width, 2.0%
duty cycle
CSG(off) Off Capacitance SW to Gnd 14 25 14 20 25 14 25 pF 0V, f = 1MHz
CSG(on) On Capacitance SW to Gnd 40 60 40 50 60 40 60 pF 0V, f = 1MHz
+VSPK 150
-VSPK 200
mV
VPP = +40V,
VNN = -160V,
RLOAD = 50ohm
+VSPK 150
-VSPK 200
mV
VPP = +100V,
VNN = -100V,
RLOAD = 50ohm
+VSPK 150
-VSPK
Output Voltage Spike
200
mV
VPP = +160V,
VNN = -40V,
RLOAD = 50ohm
1450
VPP = +40V,
VNN = -160V,
VSIG = 0V
1050
VPP = +100V,
VNN = -100V,
VSIG = 0V
Q Charge Injection
550
pC
VPP = +160V,
VNN = -40V,
VSIG = 0V
HV219
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Power Up/Down Sequence
1) Power up/down sequence is arbitrary except GND must be powered up first and powered down last. This applies for
applications powering GND of the IC with different voltages.
2) Vsig must always be at or in between VPP and VNN or floating during power up/down transition.
3) Rise and fall times of the power supplies VDD, VPP, and VNN should not be less than 1.0ms.
Logic Truth Table
Data in the 8-bit Shift Register Output Switch State
D0 D1 D2 D3 D4 D5 D6 D7 LE CL
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
L L L OFF
H L L ON
X X X X X X X X H L HOLD PREVIOUS STATE
X X X X X X X X X H OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition clock.
3. The switches go to a state retaining their present condition at the rising edge of the LE .
4. When
LE is low, the shift register data flows through the latch.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The clear input overrides all other inputs.
Logic Timing Waveform
DATA
IN
LE
CLOCK
DATA
OUT
D
N - 1 N N + 1
DD
50%
50%
50%
50%
50%
50%
50%
50%
50%
OUT
(TYP)
V OFF
ON
CLR
t
WCL
90%
10%
tOFF
DD
SD
ON
t
tt
t
t
h
WLE
SU
t
HV219
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Test Circuits
Switch OFF Leakage
I
SOL
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
NN
+10V
V
PP
-10V
DC Offset ON/OFF
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
OUT
100KR
L
TON/T
OFF Test Circuit
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
PP
-10V
R
L
10K
V
OUT
Isolation Diode Current
I
ID
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
NN
V
SIG
Crosstalk
K
CR
= 20Log V
OUT
V
IN
V
IN
= 10 V
P-P
@5MHz
NC
50
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
50
Charge Injection
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
SIG
V
OUT
1000pF
Q = 1000pF x V
OUT
V
OUT
Output Voltage Spike
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
V
OUT
1KR
L
50
+V
SPK
-V
SPK
OFF Isolation
K
O
= 20Log V
OUT
V
IN
V
IN
= 10 V
P-P
@5MHz
V
PP
5V
V
NN
V
PP
V
NN
V
DD
GND
R
L
V
OUT
HV219
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Pin Configuration
Dimensions in Inches
(Dimensions in Millimeters)
Measurement Legend =
28 Pin J-Lead
Pin Function Pin Function
1SW3 15 N/C
2SW3 16 DIN
3SW2 17 CLK
4SW2 18 LE
5SW1 19 CL
6SW1 20 DOUT
7SW0 21 SW7
8SW0 22 SW7
9 N/C 23 SW6
10 VPP 24 SW6
11 N/C 25 SW5
12 VNN 26 SW5
13 GND 27 SW4
14 VDD 28 SW4
Pin #1
B.C. of Bend Radii
0.480 ± 0.010
(12.192 ± 0.254)
D
e
0.050 ± 0.010
(1.270 ± 0.254)
0.450 ± 0.005
(11.430 ± 0.127)
D
1
B0.027 ± 0.003
(0.6858 ± 0.0762)
0.1725 ± 0.0075
(4.3815 ± 0.1905)
A
A
2min.
0.020
(0.508)
0.410 ± 0.010
(10.414 ± 0.254)
0.110 ± 0.010
(2.794 ± 0.254)
Q
Top View
28-Pin J-Lead Package
1
2
3
4
567891011
12
13
14
15
16
17
18
19202122232425
26
27
28
28-Pin J-lead
Package Outline
HV219
A042705
8
48-Pin TQFP Pin Configuration
1#
n
iP
0° - 7°
BSC
0.354 ± 0.010
(8.992 ± 0.254)
0.275 ± 0.004
(6.985 ± 0.102)
0.354 ± 0.010
(8.992 ± 0.254)
D
1
, E
1
D, E
0.275 ± 0.004
(6.985 ± 0.1016)
A2
0.055 ± 0.004
(1.397 ± 0.102)
0.020
(0.508)
TYP.
0.039
(0.991)
A
0.059 ± 0.004
(1.4986 ± 0.102)
0.024 ± 0.008
(0.610 ± 0.2032)
L
1
# niP
Pin 1
top view
48-pin TQFP
Pin 12
HV219
48-Pin TQFP
Pin Function
1SW5
2 N/C
3SW4
4 N/C
5SW4
6 N/C
7 N/C
8SW3
9 N/C
10 SW3
11 N/C
12 SW2
13 N/C
14 SW2
15 N/C
16 SW1
17 N/C
18 SW1
19 N/C
20 SW0
21 N/C
22 SW0
23 N/C
24 VPP
Pin Function
25 VNN
26 N/C
27 N/C
28 GND
29 VDD
30 N/C
31 N/C
32 N/C
33 DIN
34 CLK
35 LE
36 CLR
37 DOUT
38 N/C
39 SW7
40 N/C
41 SW7
42 N/C
43 SW6
44 N/C
45 SW6
46 N/C
47 SW5
48 N/C
Dimensions in Inches
(Dimensions in Millimeters)
Measurement Legend =
A
04
2
705