TPS53211RGTT - Texas Instruments

VSEN

TPS53211

UDG-11173

FBG

CSN

BOOT

PHASE

2LGATE

1VCCDR

VCC

GND

COMP

PGOOD UGATE

CSP

OSC

PVCC

Enable

Power

Good

VIN

VOUT

TPS53211

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SLUSAA9 –SEPTEMBER 2011

Single-Phase PWM Controller with Light-Load Efficiency Optimization

1FEATURES APPLICATIONS

•1.5-V to 19-V Conversion Voltage Range •Server and Desktop Computer Subsystem

Power Supplies

•4.5-V to 14-V Supply Voltage Range

•DDR Memory and Termination Supply

•Voltage Mode Control

•Distributed Power Supply

•Skip Mode at Light Load for Efficiency

Optimization •General DC/DC Converter

•High Precision 0.5% Internal 0.8-V Reference DESCRIPTION

•Adjustable Output Voltage from 0.8 V to TPS53211 is a single phase PWM controller with

0.7×VIN integrated high-current drivers. It is used for 1.5 V up

•Internal Soft-Start to 19 V conversion voltage.

•Supports Pre-biased Startup TPS53211 features a skip mode solution that

•Supports Soft-Stop optimizes the efficiency at light load condition without

•Programmable Switching Frequency from compromising the output voltage ripple. The device

provides pre-biased startup, soft-stop, integrated

250 kHz to 1 MHz bootstrap switch, power good function, EN/Input

•Overcurrent Protection UVLO protection. It supports conversion voltages up

•Inductor DCR Sensing for Overcurrent to 19 V, and output voltages adjustable from 0.8 V to

0.7×VIN.

•RDS(on) Sensing for Zero Current Detection

•Overvoltage and Undervoltage Protection The TPS53211 is available in the 3 mm ×3 mm,

16-pin, QFN package (Green RoHs compliant and Pb

•Open Drain Power Good Indication free) and is specified from –40°C to 85°C.

•Internal Bootstrap Switch

•Integrated High-Current Drivers Powered by

VCCDR

•Small 3 mm x 3 mm, 16-Pin QFN Package

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS53211

SLUSAA9 –SEPTEMBER 2011

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

ORDERABLE MINIMUM

TA PACKAGE PINS OUTPUT SUPPLY ECO PLAN

DEVICE NUMBER QUANTITY

TPS53211RGTR Tape and Reel 3000

Plastic QFN Green (RoHS and

–40°C to 85°C 16

(RGT) no Pb/Br)

TPS53211RGTT Mini Reel 250

ABSOLUTE MAXIMUM RATINGS(1)

over operating free-air temperature range (unless otherwise noted) MIN MAX UNITS

VCC, EN –0.3 15 V

VCCDR –0.3 7.7 V

BOOT dc –0.3 36 V

dc –0.3 7.7 V

BOOT to PHASE transient <200ns –5 7.7 V

Input voltage range(2) dc –3 26 V

PHASE transient <200ns –5 30 V

FB, VSEN, OSC –0.3 3.6 V

VVCC >6.8 V –0.7 5.3 V

CSP, CSN VVCC ≤6.8 V –0.7 VCC-1.5 V

UGATE –0.3 36 V

dc –0.3 7.7 V

UGATE to PHASE,

Output voltage LGATE transient <200 ns –5 7.7 V

range(3) COMP –0.3 3.6 V

PGOOD –0.3 15 V

GND –0.3 0.3 V

Ground pins FBG –0.3 0.3

Human Body Model (HBM) 1500

Electrostatic V

discharge Charged Device Model (CDM) 500

Storage junction temperature –55 150 °C

Operating junction temperature –40 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

(3) Voltage values are with respect to the SW terminal.

THERMAL INFORMATION TPS53211

THERMAL METRIC(1) QFN UNITS

16 PINS

θJA Junction-to-ambient thermal resistance 51.3

θJCtop Junction-to-case (top) thermal resistance 85.4

θJB Junction-to-board thermal resistance 20.1 °C/W

ψJT Junction-to-top characterization parameter 1.3

ψJB Junction-to-board characterization parameter 19.4

θJCbot Junction-to-case (bottom) thermal resistance 6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS53211

www.ti.com

SLUSAA9 –SEPTEMBER 2011

RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNITS

VCC 4.5 14

EN –0.1 VVCC+0.1

VCCDR 4.5 7

BOOT dc –0.1 34

dc –0.1 7

BOOT to PHASE

Input voltage range transient <200ns –3 7 V

dc –1 24

PHASE transient <200ns –3 28

FB, VSEN, OSC –0.1 3.3

VVCC >6.8 V –0.1 5

CSP, CSN VVCC ≤6.8 V –0.1 VVCC–2

UGATE –0.1 34

dc –0.1 7

UGATE to PHASE, LGATE

Output voltage range transient <200 ns –3 7

COMP –0.1 3.3 V

PGOOD –0.1 12

GND –0.1 0.1

Ground pins FBG –0.1 0.1

Junction temperature range, TJ–40 125 °C

Operating free-air temperature, TA–40 85 °C

TPS53211

SLUSAA9 –SEPTEMBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS(1)

over operating free-air temperature range, VCC = 12V, PGND = GND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT SUPPLY

VVCC VCC supply voltage Nominal input voltage range 4.5 12 V

VPOR VCC POR threshold Ramp up; EN =’HI’4.1 4.25 4.4 V

VPORHYS VCC POR hysteresis VCCDR POR hysteresis 200 mV

ICC_STBY Standby current EN pin is low. VVCC= 12 V 60 µA

RBoot Rds(on) of the boot strap switch 10 Ω

DRIVER SUPPLY

VCCDR VCCDR Supply voltage Nominal input voltage range 4.5 7.0 V

VPORDR VCCDR POR threshold Ramp up; EN =’HI’3.15 3.32 3.50 V

VPORHYSDR VCCDR POR hysteresis VCCDR POR hysteresis 220 mV

ICCDR_STBY Standby current EN pin is low. VVCC = 12 V 100 µA

REFERENCE

VVREF VREF Internal precision reference voltage 0.8 V

TOLVREF VREF tolerance Close loop trim. 0°C≤TJ≤70°C–0.5% 0.5%

ERROR AMPLIFIER

UGBW(2) Unity gain bandwidth 14 MHz

AOL(2) Open loop gain 80 dB

IFB(int) FB Input leakage current Sourced from FB pin 10 nA

IEA(max) Output sinking and sourcing current 2.5 mA

SR(2) Slew rate 5 V/µs

ENABLE

VENH EN logic high 2.2 V

VENL EN logic low 600 mV

IEN EN pin current 12 µA

SOFT START

tSS_delay Delay after EN asserting EN = ‘HI’to “switching enabled”1024/fSW ms

tPGDELAY PGOOD startup delay time PG delay after soft-start begins 1560/fSW ms

RAMP

Ramp amplitude 4.5V <VVCC <12 V 2 V

PWM

tMIN(on)(2) Minimum ON time 40 ns

DMAX(2) Maximum duty cycle fSW = 1 MHz 70%

SWITCHING FREQUENCY

fSW(typ) Typical switching frequency ROSC = 61.9 kΩ360 400 440 kHz

fSW(min) Minumum switching frequency ROSC = 250 kΩ250 kHz

fSW(max) Maximum switching frequency ROSC = 14 kΩ1 MHz

fSW(tol) Switching frequency tolerance ROSC >12.4 kΩ –20% 20%

OVERCURRENT

CSP-CSN threshold for DCR

VOC_TH TA= 25°C 17 20 23 mV

sensing

(1) See PS pin description for levels.

(2) Ensured by design. Not production tested.

TPS53211

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SLUSAA9 –SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS(1) (continued)

over operating free-air temperature range, VCC = 12V, PGND = GND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

GATE DRIVERS

RHDHI(3) High-side driver sourcing resistance (VBOOT –VPH) forced to 5 V, high state 1 Ω

RHDLO High-side driver sinking resistance (VBOOT –VPH) forced to 5 V, low state 0.5 Ω

RLDHI Low-side driver sourcing resistance (VCCDR–GND) = 5 V, high state 0.7 Ω

RLDLO Low-side driver sinking resistance VCCDR–GND = 5 V, low state 0.33 Ω

POWER GOOD

VPGDL PG lower threshold Measured at VSEN w/r/t VREF 87% 89%

VPGDU PG upper threshold Measured at VSEN w//rt VREF 110% 113% 116%

VPGHYS PG hysteresis Measured at VSEN w/r/t VREF 3.5%

Time from VSEN out of +12.5% of VREF to

tOVPGDLY PG delay time at OVP 2.3 µs

PG low

Time from VSEN out of –12.5% of VREF to

tUVPGDLY PG delay time at UVP 2.3 µs

PG low

Minimum VCC voltage for valid PG at Measured at VVCC with 1 mA (or 2 mA) sink

VINMINPG 1 V

startup. current on PG pin at startup.

VPGPD PG pull-down voltage Pull down voltage with 4 mA sink current 0.2 0.4 V

IPGLK PG leakage current Hi-Z leakage current, apply 6.5 V in off state 7.8 12 16.2 µA

OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTION

VOVth OVP threshold Measured at the VSEN wrt. VREF. 110% 113% 116%

VUVth UVP threshold Measured at the VSEN wrt. VREF. 87% 89%

Time from VSEN out of +12.5% of VREF to

tOVPDLY OVP delay time 2.3 µs

OVP fault

Time from VSEN out of –12.5% of VREF to

tUVPDLY(3) UVP delay time 80 µs

UVP fault

THERMAL SHUTDOWN

THSD(3) Thermal shutdown Latch off controller, attempt soft-stop 130 140 150 °C

Controller starts again after temperature has

THSDHYS(3) Thermal shutdown hysteresis 40 °C

dropped

(3) Ensured by design. Not production tested.

VCCDR

UGATE

LGATE

PGOOD

PHASE

BOOT

COMP

CSN

GND

FBG

VCC

VSEN

OSC

CSP

15 14 13

5678

TPS53211

SLUSAA9 –SEPTEMBER 2011

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DEVICE INFORMATION

TPS53211

16 PINS

(TOP VIEW)

PIN FUNCTIONS

PIN DESCRIPTION

I/O

NAME NO.

BOOT 4 I Supply input for high-side drive (boot strap pin). Connect capacitor from this pin to SW pin

COMP 8 O Error amplifier compensation terminal. Type III compensation method is generally recommended for stability.

CSN 12 I Current sense negative input.

CSP 13 I Current sense positive input

EN 7 I Enable.

FB 9 I Voltage feedback. Use for OVP, UVP and PGD determination.

FBG 11 G Feedback ground for output voltage sense.

GND 16 G Logic ground and low-side gate drive return.

PHASE 3 O Output inductor connection to integrated power devices.

LGATE 2 O Low-side gate drive output.

OSC 14 O Frequency programming input.

PGOOD 6 O Power good output flag. Open drain output. Pull up to an external rail via a resistor.

UGATE 5 O High-side gate drive output.

VCC 15 I Supply input for analog control circuitry.

VCCDR 1 I/O Bias voltage for integrated drivers.

VSEN 10 I Output voltage sense

COMP

OSC

BOOT

LGATE

TPS53211

EN PGOOD

GND

UDG-11172

UV/OV

Threshold

Generation

0.8 V

Enable

Control

OSC

E/A

Control

Logic

PWM

LL One-Shot

Overtemp

VOUT Discharge

0.8 V x 87%

PWM

Ramp

VCCDR UVLO

XCON

HDRV

LDRV

OCP Logic

CSP CSN

0.8 V x 113%

VSEN

FBG

VCCDR

LDO

VCC

UVLO VCC

UGATE

PHASE

TPS53211

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SLUSAA9 –SEPTEMBER 2011

FUNCTIONAL BLOCK DIAGRAM

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Supply Current (mA)

G000

370

380

390

400

410

420

430

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Switching Frequency (kHz)

G000

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Powergood Hysteresis (%)

PGOOD Lower Hysteresis

PGOOD Upper Hysteresis

Measured at VSEN w/r/t VREF

G000

100

105

110

115

120

−40 −25 −10 5 20 35 50 65 80 95 110 125

Junction Temperature (°C)

Powergood Threshold (%)

Lower Threshold

Upper Threshold

G000

TPS53211

SLUSAA9 –SEPTEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS

Figure 1. VCC Current vs. Junction Temperature Figure 2. Switching Frequency vs. Junction Temperature

Figure 3. Power Good Hysteresis vs. Junction Figure 4. Power Good Threshold vs. Junction

Temperature Temperature

( )

OSC

200 R 78.5 150

= + ´ +

= ´

LR C

DCR

TPS53211

www.ti.com

SLUSAA9 –SEPTEMBER 2011

DETAILED DESCRIPTION

Introduction

The TPS53211 is a single-channel synchronous buck controller with integrated high-current drivers. The

TPS53211 is used for 1.5 V up to 19 V conversion voltage, and provides output voltage from 0.8 V to 0.7 VIN. It

operates with programmable switching frequency ranging from 250 kHz to 1 MHz.

This device employs a skip mode solution that optimizes the efficiency at light-load condition without

compromising the output voltage ripple. The device provides pre-bias startup, integrated bootstrap switch, power

good function, EN/Input UVLO protection. The TPS53211 is available in the 3 mm by 3mm 16-pin QFN package

and is specified from –40°C to 85°C.

Switching Frequency Setting

The clock frequency is programmed by the value of the resistor connected from the OSC pin to ground. The

switching frequency is programmable from 250 kHz to 1 MHz. The relation between the frequency and the OSC

resistance is given by Equation 1.

where

•ROSC is the resistor connected from the OSC pin to ground in kΩ

•fSW is the desired switching frequency in kHz (1)

Soft-Start Function

The soft-start function reduces the inrush current during the start-up. A slow rising reference voltage is generated

by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage is less than

800 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 800 mV, a

fixed 800 mV reference voltage is utilized for the error amplifier. The soft-start function is implemented only when

VCC and VCCDR are above the respective UVLO thresholds and the EN pin is released.

When the soft-start begins, the device initially waits for 1024 clock cycles and then starts to ramp up the

reference. After the reference voltage begins to rise, the PGOOD signal goes high after a 1560 clock-cycle delay.

UVLO Function

The TPS53211 provides UVLO protection for the input supply (VCC) and driver supply (VCCDR). If the supply

voltage is lower than UVLO threshold voltage minus the hysteresis, the device shuts off. When the voltage rises

above the threshold voltage, the device restarts. The typical UVLO rising threshold is 4.25 V for VCC and 3.32 V

for VCCDR. Hysteresis of 200 mV for VCC and 220 mV for VCCDR are also provided to prevent glitch.

Overcurrent Protection

The TPS53211 continuously monitors the current flowing through the inductor. The inductor DCR current sense

is implemented by comparing and monitoring the difference between the CSP and CSN pins. DCR current

sensing requires time constant matching between the inductor and the sensing network:

(2)

TPS53211 has two level OC thresholds: 20 mV and 30 mV for the voltage between the CSP and CSN pins.

If the voltage between the CSP and CSN pins exceeds the 20 mV current limit threshold, an OC counter starts to

increment to count the occurrence of the overcurrent events. The converter shuts down immediately when the

OC counter reaches four (4). The OC counter resets if the detected current is lower than the OC threshold after

an OC event. Normal operation can only be restored by cycling the VCC voltage.

If the voltage between the CSP and CSN pins is higher than 30 mV, the device latches off immediately. Normal

operation can be restored only by cycling the VCC voltage.

TPS53211

SLUSAA9 –SEPTEMBER 2011

www.ti.com

The TPS53211 has thermal compensation to adjust the OCP threshold in order to reduce the influence of

inductor DCR variation due to temperature change. The OCP level has a change rate of 0.35%/°C.

Overvoltage and Undervoltage Protection

The TPS53211 monitors the VSEN pin voltage to detect the overvoltage and undervoltage conditions. A resistor

divider with the same ratio as on the FB input is recommended for the VSEN input. The overvoltage and

undervoltage thresholds are set to ±13% of VOUT.

When the VSEN voltage is greater than 113% of the reference, the overvoltage protection is activated. The

high-side MOSFET turns off and the low-side MOSFET turns on. Normal operation can be restored only by

cycling the VCC pin voltage.

When the VSEN voltage is lower than 87% of the reference voltage, the undervoltage protection is triggered and

the PGOOD signal goes low. After 80 µs, the controller is latched off with both the upper and lower MOSFETs

turned off.

After both the undervoltage and overvoltage events, the device is latched off. Normal operation can be restored

only by cycling the VCC pin voltage.

Power Good

The TPS53211 monitors the output voltage through the VSEN. During start up, the power good signal delay after

the reference begins to rise is 1560 clock cycles. After this delay, if the output voltage is within ±9.5% of the

target value, PGOOD signal goes high.

At steady state, if the VSEN voltage is within 113% and 87% of the reference voltage, the power good signal

remains high. If VSEN voltage is outside of this limit, PGOOD pin is pulled low by the internal open drain output.

The PGOOD output is an open drain and requires an external pull-up resistor.

Over-Temperature Protection

The TPS53211 continuously monitors the die temperature. If the die temperature exceeds the threshold value

(140˚C typical), the device shuts off. When the device temperature lowers to 40˚C below the over-temperature

threshold, it restarts and return to normal operation.

VSEN

TPS53211

UDG-11173

FBG

CSN

BOOT

PHASE

2LGATE

1VCCDR

VCC

GND

COMP

PGOOD UGATE

CSP

OSC

PVCC

Enable

Power

Good

VIN

VOUT

( ) ( )

- ´

= ´

´f

IN OUT OUT

L ripple SW IN

V V V

IL V

TPS53211

www.ti.com

SLUSAA9 –SEPTEMBER 2011

APPLICATION INFORMATION

The following example illustrates the design process and component selection for a single output synchronous

buck converter using TPS53211. The schematic of a design example is shown in Figure 5. The specifications of

the converter are listed in Table 1.

Table 1. Specification of the Single Output Synchronous Buck Converter

PARAMETER TEST CONDITION MIN TYP MAX UNIT

VIN Input voltage 10.8 12 13.2 V

VOUT Output voltage 1.05 V

VRIPPLE Output ripple IOUT = 20 A 1% of VOUT V

IOUT Output current 20 A

fSW Switching frequency 400 kHz

Figure 5. Typical 12-V Input Application Circuit

Output Inductor Selection

Determine an inductance value that yields a ripple current of approximately 20% to 40% of maximum output

current. The inductor ripple current is determined by Equation 3:

(3)

The inductor requires a low DCR to achieve good efficiency, as well as enough room above peak inductor

current before saturation.

= + +

RIPPLE RIPPLE(C) RIPPLE(ESR) RIPPLE(ESL)

V V V V

=´ ´

L(ripple)

RIPPLE(C)

OUT SW

V8 C f

= ´

RIPPLE(ESR) L(ripple)

V I ESR

=IN

RIPPLE(ESL)

V ESL

( )

a ´ -

=´ ´ ´

L(ripple) OUT

RIPPLE(DCM)

SW OUT L(ripple)

I I

V2 f C I

( )

ON dcm

ON ccm

a =

VOUT

ax IL(ripple)

VRIPPLE

ax T

IOUT

UDG-11174

TPS53211

SLUSAA9 –SEPTEMBER 2011

www.ti.com

Output Capacitor Selection

The output capacitor selection is determined by output ripple and transient requirement. When operating in CCM,

the output ripple has three components:

(4)

(5)

(6)

(7)

When a ceramic output capacitor is chosen, the ESL component is usually negligible. In the case when multiple

output capacitors are used, the total ESR and ESL should be the equivalent of the all output capacitors in

parallel.

When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also

varies with load current and can be expressed as shown in Equation 8.

where

• α is the DCM On-Time coefficient and can be expressed as (8)

Figure 6. DCM VOUT Ripple Calculation

( ) ( )

= ´ ´ -

OUT

IN ripple

I I D 1 D

=OUT

( ) ´

=´

OUT

IN ripple SW IN

I D

Vf C

( )

æ ö

= ´

ç ÷

è ø

OUT

0.8

R1 R1

V 0.8

+ ´ ´

= ´ æ ö

+ ´ + ´ + + ´ ´

ç ÷

è ø

OUT

OUT OUT

LOAD

1 s C ESR

G 4 L

1 s C (ESR DCR) s L C

DCR R

=´ p´ ´

fDP

OUT

2 L C

=´ p´ ´

fESR

OUT

2 ESR C

TPS53211

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SLUSAA9 –SEPTEMBER 2011

Input Capacitor Selection

The selection of input capacitor should be determined by the ripple current requirement. The ripple current

generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS

ripple current from the converter can be expressed as:

where

•D is the duty cycle and can be expressed as (9)

To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be

placed close to the device. The ceramic capacitor is recommended due to the inherent low ESR and low ESL.

The input voltage ripple can be calculated as below when the total input capacitance is determined:

(10)

Output Voltage Setting Resistors Selection

The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 7. R1 is connected

between FB pin and the output, and R2 is connected between the FB pin and FBG. The recommended value for

R1 is between 1 kΩand 5 kΩ. Determine R2 using Equation 11.

(11)

Compensation Design

The TPS53211 employs voltage mode control. To effectively compensation the power stage and ensures fast

transient response, Type III compensation is typically used.

The control to output transfer function can be described in Equation 12.

(12)

The output LC filter introduces a double pole, calculated in Equation 13.

(13)

The ESR zero of can be calculated calculated in Equation 14

(14)

( )( )

( ) ( )

+ ´ ´ + + ´ ´

=æ ö

´ ´ + ´ + ´ ´ ´ + ´

ç ÷

è ø

1 1 3 4 2

2 3

1 2 3 1 3 4

2 3

1 s C (R R ) 1 s R C

GC C

s R (C C ) 1 s C R 1 s R C C

=´ p´ ´

fZ1

4 2

2 R C

= @

´ p´ + ´ ´ p´ ´

fZ2

1 3 1 1 1

1 1

2 (R R ) C 2 R C

R4 C2

+COMP

VREF

UGD-11176

UDG-11175

Frequency

fZ1 fZ2 fP2 fP3

Gain (dB)

=fP1 0

=´ p´ ´

fP2

3 1

2 R C

= @ ´ p´ ´

æ ö

´ p ´ ´ ç ÷

è ø

fP3

4 3

2 3

1 1

2 R C

C C

2 R C C

TPS53211

SLUSAA9 –SEPTEMBER 2011

www.ti.com

Figure 7 shows the configuration of Type III compensation and typical pole and zero locations. Equation 15

through Equation 17 describe the compensator transfer function and poles and zeros of the Type III network.

(15)

(16)

(17)

Figure 7. Type III Compensation Network Figure 8. Type III Compensation Network

Configuration Waveform

(18)

(19)

(20)

The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One

pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to

attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a

compromise between high phase margin and fast response. A phase margin higher than 45 degrees is required

for stable operation.

PACKAGE OPTION ADDENDUM

www.ti.com 12-Oct-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS53211RGTR ACTIVE QFN RGT 16 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TPS53211RGTT ACTIVE QFN RGT 16 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS53211RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS53211RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS53211RGTR QFN RGT 16 3000 367.0 367.0 35.0

TPS53211RGTT QFN RGT 16 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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