IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: menting buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. - - - 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) - 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages - Extended commercial range of - 40C to + 85C - VCC = 3.3V 0.3V, Normal Range - VCC = 2.7V to 3.6V, Extended Range - VCC = 2.5V 0.2V - CMOS power levels (0.4 W typ. static) - Rail-to-Rail output swing for increased noise margin Drive Features for ALVCH162373: - Balanced Output Drivers: 12mA - Low switching noise A buffered output-enable (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be enetered while the outputs are in the high-impedance state. The ALVCH162373 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. APPLICATIONS: * 3.3V High Speed Systems * 3.3V and lower voltage computing systems The ALVCH162373 has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistor. DESCRIPTION: This 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. The ALVCH162373 is particularly suitable for imple Functional Block Diagram 1 OE 1 LE 1 2 OE 48 2 LE 24 25 C1 C1 2 1D 1 47 13 1Q 1 1D 2D 1 36 2Q 1 1D TO 7 OTHER CH AN NELS TO 7 OTHER CH AN NELS EXTENDED COMMERCIAL TEMPERATURE RANGE MARCH 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4575/1 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION (1) ABSOLUTE MAXIMUM RATING Symbol VTERM(2) 1 OE 1 48 1 LE 1Q 1 2 47 1D 1 1Q 2 3 46 1D 2 TSTG Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature GND 4 45 GND IOUT DC Output Current IIK 50 mA - 50 mA 100 mA VTERM(3) 1Q 3 5 44 1D 3 1Q 4 6 43 1D 4 IOK Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 ICC ISS Continuous Current through each VCC or GND V CC 7 42 V CC 1Q 5 8 41 1D 5 1Q 6 9 40 1D 6 GND 10 39 GND 1Q 7 11 1Q 8 12 1D 8 2Q 1 13 38 SO48-1 SO48-2 37 SO48-3 36 2Q 2 14 35 2D 2 GND 15 34 GND 2Q 3 16 33 2D 3 2Q 4 17 32 2D 4 V CC 18 31 V CC 2Q 5 19 30 2D 5 2Q 6 20 29 2D 6 GND 21 28 GND 2Q 7 22 27 2D 7 2Q 8 23 26 2D 8 2 OE 24 25 2 LE - 0.5 to VCC + 0.5 - 65 to + 150 V C - 50 to + 50 mA NEW16link 1D 7 2D 1 CAPACITANCE (TA = +25oC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 5 Max. 7 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 7 9 pF VIN = 0V 7 9 pF CI/O NEW16link NOTE: 1. As applicable to the device type. FUNCTION TABLE (each 8-bit section)(1) SSOP/ TSSOP/TVSOP TOP VIEW PIN DESCRIPTION (1) xLE Latch Enable Inputs xQx 3-State Outputs xOE 3-State Output Enable Input (Active LOW) Outputs xOE xLE xDx xQx L H H H L H L L H X X Z L L X QO NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance QO = Level of Q before the indicated steady-state input conditions were established Description Data Inputs Unit V NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. Inputs Pin Names xDx Max. - 0.5 to + 4.6 NOTE: 1. These pins have "Bus-Hold." All other pins are standard inputs, outputs, or I/Os. 2 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = - 40C to +85C Symbol VIH VIL Parameter Input HIGH Voltage Level Input LOW Voltage Level VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) -- Max. -- VCC = 2.7V to 3.6V 2 -- -- VCC = 2.3V to 2.7V -- -- 0.7 VCC = 2.7V to 3.6V -- -- 0.8 Test Conditions Unit V V IIH Input HIGH Current VCC = 3.6V VI = VCC -- -- 5 IIL Input LOW Current VCC = 3.6V VI = GND -- -- 5 IOZH High Impedance Output Current VCC = 3.6V VO = VCC -- -- 10 A IOZL (3-State Output pins) -- -- 10 A VIK Clamp Diode Voltage VCC = 2.3V, IIN = - 18mA -- - 0.7 - 1.2 V VH Input Hysteresis VCC = 3.3V -- 100 -- mV VCC = 3.6V VIN = GND or VCC -- 0.1 40 A Quiescent Power Supply Current Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND -- -- 750 A ICCL ICCH ICCZ ICC VO = GND A NEW16link NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Bus-Hold Input Sustain Current VCC = 3.0V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V 75 -- -- - 45 -- -- VI = 0.8V VI = 1.7V IBHL IBHHO Max. -- Min. - 75 IBHL IBHH Typ.(2) -- Test Conditions VI = 2.0V VI = 0.7V 45 -- -- VI = 0 to 3.6V -- -- 500 Unit A A A IBHLO NEW16link NOTES: 1. Pins with Bus-hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient. 3 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.7V VCC = 3.0V VOL Output LOW Voltage Min. VCC - 0.2 Max. -- IOH = - 4mA 1.9 -- IOH = - 6mA 1.7 -- IOH = - 4mA 2.2 -- IOH = - 8mA 2 -- IOH = - 6mA 2.4 -- IOH = - 12mA 2 -- VCC = 2.3V to 3.6V IOL = 0.1mA -- 0.2 VCC = 2.3V IOL = 4mA -- 0.4 IOL = 6mA -- 0.55 VCC = 2.7V VCC = 3.0V IOL = 4mA -- 0.4 IOL = 8mA -- 0.6 IOL = 6mA -- 0.55 IOL = 12mA -- 0.8 Unit V V NEW16link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz SWITCHING CHARACTERISTICS VCC = 2.5V 0.2V VCC = 3.3V 0.3V Typical 19 Typical 22 4 5 Unit pF pF (1) VCC = 2.5V 0.2V VCC = 2.7V VCC = 3.3V 0.3V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Parameter Propagation Delay xDx to xQx Propagation Delay xLE to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Setup Time, data before LE Min. 1.5 Max. 5.3 Min. 1.5 Max. 4.5 Min. 1.5 Max. 4 Unit ns 2 5.6 2 5 2 4 ns 1.5 6.5 1.5 6 1.5 5 1.5 5.6 1.5 5.5 1.5 4.5 2 -- 2 -- 2 -- ns tH Hold Time, data after LE 1.5 -- 1.5 -- 1.5 -- ns tW Pulse Duration, LE HIGH or LOW 3.3 -- 3.3 -- 3.3 -- ns tSK(o) Output Skew(2) -- -- -- -- -- 500 ps NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 ns ns IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V0.3V VCC(1)= 2.7V VCC(2)= 2.5V0.2V 6 6 2 x Vcc VIH 2.7 2.7 Vcc V SAM E PHAS E INPUT TRANSITION VT 1.5 1.5 Vcc / 2 V OUTPUT VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 Unit V 30 tPLH tPH L tPLH tPH L V IH VT 0V V OH VT V OL V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF NEW16link ALV C Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 500 (1, 2) V IN CONTROL INPUT GND tPZL V OU T Pulse Generator D.U.T. OUTPUT SW ITCH NORM ALLY CLOSE D LOW tPZH OUTPUT SW ITCH NORM ALLY OPEN HIGH 500 RT DISABLE ENABLE Open CL ALV C Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. V LOAD /2 V LOAD /2 VT V LZ V OL tPH Z VT V OH V HZ 0V 0V SET-UP, HOLD, AND RELEASE TIMES DATA INPUT Switch VLOAD tS U tH tR EM ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL Open tS U tH NEW16link INPUT TSK ALV C Link (x) V IH VT 0V tPH L1 tPLH1 PULSE WIDTH V OH OUTPUT 1 tSK (x) V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V TIMING INPUT GND OUTPUT SKEW - 0V ALV C Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests tPLZ V IH VT LOW -HIGH-LOW PULSE VT V OL tSK (x) tW V OH VT V OL OUTPUT 2 VT HIGH-LOW -HIGH PULSE VT ALV C Link tPLH2 tPH L2 tSK (x) = t PLH2 - tP LH1 or tPH L2 - tP HL1 ALV C Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION ID T XX X XX XXX XX Bus-H old Fam ily D evice Type Package ALVC Tem p. Range CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink S m all Outline Package (SO48-1) Thin Shrink Sm all Outline Package (SO48-2) Thin Very Sm all Outline Package (SO48-3) 373 16-Bit Transparent D-Type Latch w ith 3-State O utputs 162 D ouble-D ensity with Resistors, 12m A H Bus-H old 74 - 40C to +85C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6