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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
MARCH 1999
1999 Integrated Device Technology, Inc. DSC-4575/1c
IDT74ALVCH162373
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT TRANS-
PARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
menting buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit latches or one16-bit latch.
When the latch enable (LE) input is high, the Q outputs follow the data
(D) inputs. When LE is taken low, the Q outputs are latched at the levels
set up at the D inputs.
A buffered output-enable (OE) can be used to place the eight outputs
in either a normal logic state (high or low logic levels) or a high-
impedance state. In the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The high-impedance state and the
increased drive provide the capability to drive bus lines without need for
interface or pullup components. OE does not affect internal operations
of the latch. Old data can be retained or new data can be enetered while
the outputs are in the high-impedance state.
The ALVCH162373 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
The ALVCH162373 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistor.
FEATURES:
– 0.5 MICRON CMOS Technology
–Typical t
SK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP,
and 0.40mm pitch TVSOP packages
– Extended commercial range of – 40°C to + 85°C
–V
CC = 3.3V ± 0.3V, Normal Range
–V
CC = 2.7V to 3.6V, E x tended Range
–V
CC = 2.5V ± 0.2V
– CMOS power levels (0.4µW typ. static)
– Rail-to-Rail output swing for increased noise margin
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
Functional Block Diagram
Drive Features for ALVCH162373:
– Balanced Output Drivers: ±12mA
– Low switching noise
1OE
C1
1D
1D147
1LE
1Q1
TO 7 OTHER CHANNELS
2OE
2D136
2LE
2Q1
TO 7 OTHER CHANNELS
1
48
2
24
25
13
C1
1D
DESCRIPTION:
This 16-bit transparent D-type latch is built using advanced dual metal
CMOS technology. The ALVCH162373 is particularly suitable for imple
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
1Q2
GND
VCC
GND
GND
SO48-1
SO48-2
SO48-3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
40
41
42
43
44
45
46
47
481
1Q1
1OE
1Q4
1Q3
1Q6
1Q5
1Q8
1Q7
2Q1
2Q3
2Q2
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1D2
GND
VCC
GND
GND
1D1
1LE
1D4
1D3
1D6
1D5
1D8
1D7
2D1
2D3
2D2
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
NOTE:
1. H = HIGH Voltage Le vel
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
QO = Level of Q before the indicated steady-state input conditions were
established
FUNCTION TABLE (each 8-bit section)(1)
PIN DESCRIPTION
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other c onditions above t hose indicated in the operational s ections
of this specification is not implied. Exposure to absolute maximum
rating conditi ons for extended periods may affec t reliability.
2. VCC terminals.
3. All terminals except V CC.
CAPACITANCE (TA = +25oC, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output
Capacitance VOUT = 0V 7 9 pF
CI/O I/O Port
Capacitance VIN = 0V 7 9 pF
NEW16link
NOTE:
1. As appl i cable to the device type.
ABSOLUTE MAXIMUM RATING (1)
Symbol Description Max. Unit
VTERM(2) Terminal Voltage
with Respect to GND – 0.5 to + 4.6 V
VTERM(3) Terminal Voltage
with Respect to GND – 0.5 to
VCC + 0.5 V
TSTG Storage Temperature – 65 to + 150 °C
IOUT DC Output Current – 50 to + 50 mA
IIK Continuous Clamp Current,
VI < 0 or VI > VCC ± 50 mA
IOK Continuous Clamp Current, VO < 0 – 50 mA
ICC
ISS Continuous Current through
each VCC or GND ±100 mA
NEW16link
NOTE:
1. These pins have “Bus-Hold. ” All other pins are standard inputs,
outputs, or I/Os .
SSOP/
TSSOP/TVSOP
TOP VIEW
PIN CONFIGURATION
Pin Names Description
xDx Data Inputs(1)
xLE Latch Enable Inputs
xQx 3-State Outputs
xOE 3-State Output Enable Input (Active LOW)
Inputs Outputs
xOE xLE xDx xQx
LHHH
LHLL
HXXZ
LLXQ
O
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C to +85°C
Symbol Param e te r Test C ondit ions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input HIGH Current VCC = 3.6V VI = VCC ——± 5µA
IIL Input LOW Current VCC = 3.6V VI = GND — — ± 5
IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——± 10µA
IOZL (3-S ta te O u tp u t p in s) VO = GND — — ± 10 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL
ICCH
ICCZ Quiescent Power Supply Current VCC = 3.6V
VIN = GND or VCC —0.140µA
∆ICC Quiescent Power Supply
Current Variation One input at VCC − 0.6V,
other inputs at VCC or GND — — 750 µA
NEW16lin
k
NOTE:
1. Typic al values are at VCC = 3.3V, +25°C ambi ent.
Symbol Parameter(1) Test Conditions Min. Typ.(2) Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3.0V VI = 2.0V – 75 — — µA
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 — — µA
IBHL VI = 0.7V 45 — —
I
BHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ± 500 µA
IBHLO NEW16link
BUS-HOLD CHARACTERISTICS
NOTES:
1. Pins wi th Bus-hold are i dent ified in the pi n descripti on.
2. Typic al values are at V CC = 3. 3V, +25°C ambient .
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
SWITCHING CHARACTERISTICS (1)
OPERATING CHARACTERISTICS, TA = 25oC
OUTPUT DRIVE CHARACTERISTICS
NOTE:
1. VIH and VIL must be within the min. or max. range shown in t he DC ELECTRICAL CHA RACTERIS TICS OVE R OPERATI NG RANGE tabl e for the
appropriate VCC range. T A = – 40°C to + 85°C.
Symbol Paramet er Test Conditions (1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 2.3V IOH = – 4mA 1.9 —
IOH = – 6mA 1.7 —
VCC = 2.7V IOH = – 4mA 2.2 —
IOH = – 8mA 2 —
VCC = 3.0V IOH = – 6mA 2.4 —
IOH = – 12mA 2 —
VOL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 2.3V IOL = 4mA — 0.4
IOL = 6mA — 0.55
VCC = 2.7V IOL = 4mA — 0.4
IOL = 8mA — 0.6
VCC = 3.0V IOL = 6mA — 0.55
IOL = 12mA — 0.8 NEW16link
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay
xDx to xQx 1.5 5.3 1.5 4.5 1.5 4 ns
tPLH
tPHL Propagation Delay
xLE to xQx 25.62524ns
tPZH
tPZL Output Enable Time
xOE to xQx 1.5 6.5 1.5 6 1.5 5 ns
tPHZ
tPLZ Output Disable Time
xOE to xQx 1.5 5.6 1.5 5.5 1.5 4.5 ns
tSU Setup Time, data before LE↓2—2—2—ns
tHHold Time, data after LE↓1.5 — 1.5 — 1.5 — ns
tWPulse Duration, LE HIGH or LOW 3.3 — 3.3 — 3.3 — ns
tSK(o) Output Skew(2) —————500ps
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two output s of the s am e package and switching in t he same direct i on.
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance
Outputs enabled CL = 0pF, f = 10Mhz 19 22 pF
CPD Power Dissipation Capacitance
Outputs disabled 45
pF
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1 , 2)
ALVC L ink
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2 tPHL2
VT
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ALV C Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
ALVC L ink
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
ALV C Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
ALV C Link
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VHZ
ALVC L ink
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two out puts.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the sam e bank.
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - TSK (x)
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 662 x VccV
VIH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
NEW16link
Test Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High GND
All Other tests Open NEW16link
DEFINITIONS:
CL= Load capacitance: i ncludes jig and probe capacitanc e.
RT = Termination resistance: s hould be equal to ZOUT of the P ulse
Generator. NOTE:
1. Diagram s hown for input Control E nable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
PULSE WIDTH
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74ALVCH162373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
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IDT XX ALVC XXX XX
PackageDevice Type
Temp. Range
PV
PA
PF
162
74
Shrink S ma ll Ou tline P a c kage (S O 4 8-1)
Thin Shrink Small Outline Package (SO48-2)
T hin Ve r y Small Ou tline Pack age (SO48- 3 )
16-Bit Transparent D-Type Latch with 3-State O utputs
– 40°C to +85°C
XXX
FamilyBus-Hold
373
Bus-Hold
D o u ble -Den s ity with R e s isto rs, ± 1 2 m A
H
