R EM MICROELECTRONIC-MARIN SA V6300 Ultra Low Power 3-Pin Voltage Surveillance with Time-out Typical Operating Configuration Features n Clear microprocessor restart after power up n Processor reset at power down n Reset output guaranteed down to VDD = 1 V VDD n Low power consumption: typ. 3 mA at VDD = 5 V n n n n n n n 1) O - 40 to +85 C temperature range O On request extended temperature range, -40 to +125 C On-chip oscillator No external components required Push-pull or Open drain output 1) TO-92, SOT-23 5L and SOT-223 packages Pin compatible with DS 1233 A in TO-92 and SOT-223 VDD VDD RES or RES V6300 RES or RES VSS On request Microprocessor VSS GND For Open drain version: Description Fig. 1 Pin Assignment The V6300 is a CMOS device which monitors the supply voltage of any electronic system, and generates the appropriate Reset signal. The thres hold defines the minimum allowed voltage which guarantees the good functionality of the system. As long as VDD stays upside this voltage level, the output stays inactive. TO-92 View Flat Front If VDD drops below VTH, the output gets active. When V DD rises V6300 1 above VTH, the output remains active for an additional 50 ms 2 3 (typ.). This al lows the system to stabilize before getting fully active. The threshold v oltage may be obtained in differ ent versions: 2.0 V, 2.4 V, 2.8 V, 3.5 V, 4.0 V, 4.5 V. VDD RES VSS or RES Applications All microprocessor applications where an automatic restart is required: n n n n n n SOT-223 1) SOT-23 5L VSS Computer electronics White / Brown goods Automotive electronics Industrial electronics Telecom systems Hand-held systems NC 3 4 2 RES or V SS RES 1) 1 On request NC 2 1 V6300 V6300 1 VSS 3 VDD 4 RES or RES 5 VDD Fig. 2 R V6300 Absolute Maximum Ratings Parameter Symbol Voltage at VDD to VSS VDD Vmin Vmax TSTO Min. voltage at RES or RES Max. voltage at RES or RES Storage temperature range Handling Procedures This device has built-in protection against high static voltages or electric fields; however; it is advised that normal precautions be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Conditions -0.3V to+10 V VSS - 0.3 V VDD + 0.3 V -65O to +150 OC Table 1 Operating Conditions Parameter Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Symbol Min. Typ. Max. Units 1) Operating temperature Positive supply voltage TA VDD -40 1 +125 8 O C V Table 2 1) The maximum operating temperature is confirmed by sampling at initial device qualification. Electrical Characteristics TA = -40 to +85 OC, unless otherwise specified Parameter Supply current 1) Threshold voltage Threshold hysteresis RES Output Low Level RES Output High Level Output leakage current 1) 2) 2) Symbol Test Conditions IDD IDD IDD VTH VTH VTH VTH VTH VTH VHYS VOL VOL VOL VOH VOH VOH ILEAK VDD = 2 V VDD = 5 V VDD = 8 V Version: A,G,M Version: B,H,N Version: C,I,O Version: D,J,P Version: E,K,Q Version: F,L,R VDD = 5 V, IOL = 8 mA VDD = 3 V, IOL = 4 mA VDD = 1 V, IOL = 50 mA VDD = 5 V, IOH = -8 mA VDD = 3 V, IOH = -4 mA VDD = 1 V, IOH = -100 mA VDD = 8 V Min. 1.77 2.09 2.48 3.11 3.55 4.05 Min. at 25 oC 1.84 2.18 2.59 3.23 3.70 4.22 4.3 2.3 850 Typ. Max. Max. at 25 oC 1.5 3.0 5.2 1.95 2.32 2.73 3.42 3.88 4.42 25 175 140 20 4.5 2.6 950 0.05 2.1 3.9 6.8 2.04 2.41 2.86 3.59 4.08 4.67 3.1 5.7 10.0 2.17 2.55 3.03 3.80 4.32 4.95 400 300 90 1 Unit mA mA mA V V V V V V mV mV mV mV V V mV mA Table 3 RES or RES open Only for Open drain versions Timing Characteristics VDD = 5.0 V, TA = -40 to +85OC, unless otherwise specified Parameter Power on reset time 3) Sensitivity 3) Reaction time 3) Symbol tPOR tSEN tR Test Conditions for VDD = 5 V to 3 V in 5 ms for VDD = 5 V to 3 V in 5 ms Tested on versions with VTH higher than 3 V Min. 25 20 22 Typ. 50 0.8 tR 75 Max. Units 75 ms 150 ms ms Table 4 2 R V6300 Timing Waveforms VDD tSEN VTH 1V tPOR Logic "1" tR tPOR t RES Logic "0" t Logic "1" RES Logic "0" t Fig.3 Block Diagram VDD Voltage Reference - Reset Logic Timer + RES or RES Oscillator Vss Fig.4 Pin Description SOT-2231) TO-92 Pin 1 2 3 Name Function Pin Name Function VDD RES or RES VSS Positive Supply Reset output Supply ground 1 2 3 4* Reset output Supply ground Positive Supply Supply ground Table 5 * Internally connected to pin 2 1) On request SOT-23 5L Pin 1 2 3 4 5 Name Function NC VSS NC RES or RES VDD No connection Supply ground No connection Reset output Positive supply RES or RES VSS VDD VSS Table 6 3 Table 7 R V6300 Version letter definition Ordering Information The V6300 is available with Push-pull or Open drain output stage and Reset active low or high. Output stage Ordering form: V6300 <version letter> < packaging> Push-pull, Reset active low A B 1) Push-pull, Reset active high G H 1) 1) Open drain, Reset active low M N 2.0 Threshold Voltage [V] 2.4 2.8 3.5 4.0 4.5 1) Example: Smart reset with: - Reset active low C I O D J P - Open drain output E 1) K 1) Q F L R Table 7 Chip form and SOT-223 on request 1) Non-stock items, minimum order 30 K pieces. - 2.8 V threshold - TO-92 package V6300 O TO-92 When ordering, please specify the complete part number. EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date O 2000 EM Microelectronic-Marin SA, 10/00, Rev. D/315 4