FAST CMOS OCTAL _|DT54/74FCT373T/ATICTIDT - 2373T/ATICT IDT54/74FCT533T/AT/CT at TRANSPARENT IDT54/74FCTS73T/AT/CT/DT - 2573T/AT/CT Integrated Device Technology, Inc. LATCHES FEATURES: Reduced system switching noise Common features: Low input and output leakage <111A (max.) DESCRIPTION: ~ CMOS power levels The FCT373T/FCT2373T, FCTS33T and FCTS731/ True TTL input and output compatibility FCT257. i i - ~ VOH = 3.3 (typ.) 2573T are octal transparent latches built using an ad ~ Vol = 0.3V (typ.) vanced dual metal CMOS technology. These octal latches Meets or exces ds JEDEC standard 18 specifications have 3-state outputs and are intended for bus oriented appli- : . oe vos cations. The flip-flops appear transparent to the data when Product available in Radiation Tolerant and Radiation Latch Enable (LE) is HIGH. When LE is LOW, the data that Enhanced versions wa ' a . meets the set-up time is latched. Data appears on the bus ~ Military product compliant to MIL-STD-883, ClassB = when the Output Enable (OE) is LOW. When Eis HIGH, the and DESC iv (ua mance) Pp Cc bus output is in the high- impedance state. - avai packaes IC, SSOP, QSOP, CERPACK The FCT2373T and FCT2573T have balanced drive out- puts with current limiting resistors. This offers low ground Features for FCT373T/FCTS33T/FCTS73T: bounce, minimal undershoot and controlled output fall times. ~ Std. A, C and D speed grades reducing the need for external series terminating resistors. ~ High drive outputs (-15mA lon, 4 8mA fol) , The FCT2xxxT parts are plug-in replacements for FCTxxxT Power off disable outputs permit live insertion parts Features for FCT2373T/FCT2573T: Std., A and speed grades ~ Resistor output (-15mMA |oH, 12mA lor Com.) (-12mA I0H, 12mMA lox Mil.) FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT3731/2373T AND IDT54/74FCT5731/2573T Do Di De Ds Da Ds De D7 Ls lr lr Ls Le Ls Ls Ls ot at ny ot ot ot ot 6 epl Ti vty i L| J AA L__al Oo 5, L 03 5 b, Q7 2564 cav" ot FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T Do Di D2 Ds Da Ds De D7 l D l D l D l D l D l D l D l D on oh oh ok oh ok oh G G G G G G G G ep LE TTT Tr | pWAYAAAY SY So Bh B2 Bs Bs Ss Se Or The 1OT is a registered trademark of Integrated Device Tachnolagy, inc. 2564 cnv" 02 MILITARY AND COMMERCIAL TEMPERATURE RANGES JUNE 1996 1996 Integrated Device Technology, Inc 6.12 25ea7IDTS4/74FCT373T/AT/CT/DT - 2373T/ATICT, IDTS4/74FCTS33 T/ATICT, IDTSA/74FCTS73T/ATICTIDT - 2573T/ATICT FAST CMOS OCTAL TRANSPARENT LATCHES PIN CONFIGURATIONS IDT54/74FCT373/2373T GND DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW IDT54/74FCT573/2573T DIP/SOIC/SSOP/QSOP/CERPACK Veco TOP VIEW IDT54/74FCT533 Voc DIP/SOIC/CERPACK - TOP VIEW Vee MILITARY AND COMMERCIAL TEMPERATURE RANGES INDEX 2564 cnv* 03 2564 cnv* 04 2564 crv" 05 2564 cnv* 06 INDEX uw g 8 slo$ 2564 crv! O7 16 9 46 4 2564 env" 08 S Lcc TOP VIEW 6.12 2IDTS4/74FCT373T/AT/CTIDT - 2373T/ATICT, IDTS4/74FCT533T/AT/CT, IDTS4/74FCTS73T/ATICT/OT - 2573T/AT/CT MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS OCTAL TRANSPARENT LATCHES FUNCTION TABLE (533) FUNCTION TABLE (373 and 573)") Inputs Outputs inputs Outputs DN LE OE On DN LE OE On H L L H H L H L H L H L H L L x xX H Zz Xx xX H zZ NOTE: - 2564tb101 NOTE: 2564 thi 02 1. H= HIGH Voitage Level 1, H =HIGH Voltage Level L = LOW Voltage Level L = LOW Voltage Level X = Don't Care X = Don't Care Z = High Impedance Z = High impedance DEFINITION OF FUNCTIONAL TERMS Data Latch Enable Input (Active HIGH) Enable 3-State 3-State Outputs 2564 tbl 03 ABSOLUTE MAXIMUM RATINGS") CAPACITANCE (Ta = +25C, f = 1.0MHz) Symbol Rating Commercial Military | Unit Symbol Parameter(1) Conditions | Typ. | Max. | Unit Vrerm(2)| Terminal Voltage | 0.5 to +7.0 | -0.5to+7.0| V CIN Input Vin =0V 6 10 | pF with Respect to Capacitance GND Gout [Output Vour=ov] 8 | 12 | pF VTeERM(3)| Terminal Voltage -0.5 to 0.5 to Vv Capacitance with Respect to Vcc +0.5 Voc +0.5 NOTE: 2564 Ink 05 GND 1. This parameter is measured at characterization but not tested. TA Operating 0 to +70 55 to +125 | C Temperature TRIAS Temperature 55 to +125 | -65 to +135 | C Under Bias TsTG Storage -55 to +125 | -65 to +150 | C Temperature Pr Power Dissipation 0.5 0.5 Ww louT DC Output -60 to +120 | -60 to +120 | mA Current NOTES: 2564 Ink 04 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Input and Vcc terminais only. 3. Outputs and I/O terminals only. 6.12 3IDT54/74FCT373T/ATICTIDT - 2373T/ATICT, IDTS4/74FCTS33T/ATICT, IDTSA/74FCTS73T/ATICTIDT - 2573T/ATICT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, Vcc = 5,0V + 5%; Military: Ta = 55C to +125C, Veco = 5.0V + 10% Symbol Parameter Test Conditions() Min. | Typ.@| Max. | Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 _ _ v VIL Input LOW Level Guaranteed Logic LOW Level _ _ 0.8 Vv WH Input HIGH Current) Vcc = Max. Vi=2.7V _ +H pA hit Input LOW Current!4) Vi=0.5V _ _ + 10ZH High Impedance Output Current Vcc = Max. Vo=2.7V _- _ +1 pA fOZL (3-State Output pins) Vo = 0.5V _ _ +H i" Input HIGH Current(4) Voc = Max., Vi = Vcc (Max.) _ +1 pA Vik Clamp Diode Voltage Vec = Min., lin =-18mA _ ~0.7 | -1.2 v VH Input Hysteresis _ _ 200 _ mV loc Quiescent Power Supply Current | Vcc = Max., VIN = GND or Vcc _ 0.01 1 mA 2564 Ink 06. OUTPUT DRIVE CHARACTERISTICS FOR FCT373T/533T/573T Symbol Parameter Test Conditions") Min. | Typ.!2)] Max. | Unit VOH Output HIGH Voltage Vcc = Min. loH = -6mA MIL. 2.4 3.3 Vv VIN = VIH or VIL lOH = 8mA COM'L. loH = -12mA MIL. 2.0 3.0 Vv loH=-15mA COM'L. VoL Output LOW Voltage Vec = Min. tou = 32mA MIL. _ 0.3 0.5 Vv VIN = ViH or VIL loL = 48mA COM'L. los Short Circuit Current Voc = Max., Vo = GND&) . -60 | -120 | -225} mA \OFF Input/Output Power Off Leakage)! Vcc = OV, VIN or Vo <4.5V _ _ H BA 2564 ink 07 OUTPUT DRIVE CHARACTERISTICS FOR FCT2373T/2573T Symbol Parameter Test Conditions) Min. | Typ.2)| Max. | Unit JODL Output LOW Current Vec = 5V, VIN = Vik or VIL, VouT= 1.5V@) 16 48 _ mA lODH Output HIGH Current Voc = 5V, VIN= ViH or Vi_, VouT= 1.5V@) -16 | ~48 _ mA VOH Output HIGH Voltage Vec = Min. 1OH = 12mA MIL. 2.4 3.3 _ Vv Vin = ViHor VIL loH = -15mA COMLL. Vou Output LOW Voltage Vec = Min. lou = 12mA _ 0.3 0.50 v VIN = Vit or Vic NOTES: 2584 Ink 08 1. For conditions shown as Max. or Min., us appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is t5yA at Ta = -55C. 5. This parameter is guaranteed but not tested. 6.12 4IDTS4/74FCT373T/AT/CTIDT - 2373T/ATICT, IDT54/74FCTS33T/ATICT, IDT54/74FCTS73T/AT/CT/DT - 2573T/AT/CT MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS OCTAL TRANSPARENT LATCHES POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions) Min. | Typ.) | Max. | Unit Alcc Quiescent Power Supply Current } Vcc = Max. _ 0.5 2.0 mA TTL Inputs HIGH Vin = 3.43) Icco Dynamic Power Supply Vcc = Max. Vin = Voc | FCTxxxT | 0.15 | 0.25 | mA/ Current4) Outputs Open Vin = GND MHz OE = GND FCT2xxxT | | 0.06 | 0.12 One Input Toggling 50% Duty Cycle Ic Total Power Supply Current!) Vcc = Max. Vin = Veco | FCTxxxT 1.5 3.5 mA Outputs Open Vin = GND] FCT2xxxT | 0.6 2.2 fi= 10MHz 50% Duty Cycle VIN =3.4 | FOTxxxT 1.8 45 OE = GND Vin = GND LE =Vec FCT2xxxT 0.9 3.2 One Bit Toggling Vc = Max. Vin=Vec | FCTxxxT | 3.0 | 6.06) Outputs Open Vin = GND| FCT2xxxT | ~ 1.2 13.46 fi= 2.5MHz 50% Duty Cycle VIN= 3.4 | FCTxxxT _ 5.0 | 14.0!) OE = GND Vin = GND LE = Vcc FCT2xxxT | 3.2 | 11.48 Eight Bits Toggling NOTES: 2564 tbl 09 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at Voc or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the [cc formula. These limits are guaranteed but not tested. 6. Ic = lQuiescent + lINPUTS + lOYNAMIC Ie = lec + Alec DHNT + Iccp (fcrv2 + fiNi) Icc = Quiescent Current Alcc = Power Supply Current for a TTL High Input (Vin = 3.4V) Dx = Duty Cycle for TTL Inputs High Nt = Number of TTL Inputs at Ox \Iccb = Dynamic Current Caused by an input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency N. = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.12 5IDTS4/74FCT373T/AT/CTIDT - 2373T/ATICT, IDTS4/74FCTS33 T/ATICT, IDTS4/74FCTS73T/AT/CTIDT - 2573T/ATICT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT3731/2373T/573T/2573T FCT373AT/2373AT/S73AT/2573AT Com. Mil. Com't. Mil. Symbol Pp t Conditions") min.@) | Max. | Min? | max. | Min | Max. | Min.2) | max. | Unit tPLH Propagation Delay Ct = 50pF 1.5 8.0 1.5 8.5 15 5.2 15 5.6 ns {PHL DN to ON Ru = 500Q {tPLH Propagation Delay 2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns tPHL LE to ON tPZH Output Enable Time 1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns tez tPHZ Output Disable Time 1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns tPLz tsu Set-up Time HIGH 2.0 _ 2.0 _ 2.0 _~ 2.0 _ ns or LOW, Dn to LE tH Hold Time HIGH 1.5 _ 1.5 _ 1.5 _ 1.5 _ ns or LOW, ON to LE tw LE Pulse Width HIGH 6.0 _ 6.0 _ 5.0 _ 6.0 _ ns 2564 tbl 10 FCT373CT/2373CT/S73CT/2S73CT FCT373D0T/S73DT Com. Mil. Com't. Mil. Symbol Parameter Conditions") min.) | Max._| Min. | Max. | Min.2) | Max. | min. | Max. | Unit {PLH Propagation Delay Ci = 50pF 1.5 4.2 1.5 5A 1.5 3.8 _ _ ns {PHL DN to ON Ri = 500Q tPLH Propagation Delay 2.0 5.5 2.0 8.0 2.0 4.0 _ _ ns {PHL LE to ON tPzH Quiput Enable Time 1.5 5.5 1.5 6.3 1.5 4.8 - _ ns tPZL tPHZ Output Disable Time 1.5 5.0 1.5 5.9 1.5 4.0 _ ns tPLz tsu Set-up Time HIGH 2.0 _ 2.0 _ 1.5 _ _ ns or LOW, DN to LE tH Hold Time HIGH 1.5 _ 1.5 _ 1.0 ~ _ _ ns or LOW, DN to LE tw LE Pulse Width HIGHS) 5.0 6.0 3.0 _ [ns 2564 tbl 11 FCT533T FCT533AT FCT533CT Com'l. Mil. Com'l. Nil. Com'l. Mil. Symbol! Parameter Conditions| min.@ | Max. [Min.@) | Max. | Min. | Max. | Min.@? | Max. | Min. | Max. | Min.?)| Max. | Unit tPLH Propagation Delay CL=50pF | 1.5 [10.0] 1.5 1/120] 15 [52] 15 756] 15 | 427) 15 | 5.7] ns tPHL DN to ON RL = 5002 tPLH Propagation Delay 2.0 113.0] 2.0 [140] 20 |] 85] 20 198] 20 155] 2.0 | 80] ns {PHL LE to ON tPZH Output Enable 1.5 [41.0] 1.5 1125] 15 765/15 [75] 1.5 755] 1.5 763] ns teze Time {PHZ Output Disable 15 770/15 |85]/15 [55715 765/15 1507 1.5 |59] ns {PLZ Time tsu Set-up Time HIGH 20 /|20]]20]]20 )] 20 | ] 20 | | ns or LOW, ON to LE tH Hold Time HIGH 1.5 {] 15 |] 15 |] 15 _ 1.5 | 1.5 ns or LOW, DN to LE tw LE Pulse Width HIGH 6.0 | ] 60 []50 | | 60 | )} 50 | |] 60 | | ns NOTES: 2564 to! 12 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 6.12 6IDTS4/74FCT373T/ATICTIDT - 2373T/ATICT, IDT54/74FCT533T/ATICT, IDTS4/74FCTS73T/AT/CTIDT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS Vec O-* 7.0V I 00Q Vin Pulse Generator D.U.T. 5000 - 2564 drw 09 SET-UP, HOLD AND RELEASE TIMES DATA 3V 1.5V INPUT 1s TIMING 3V INPUT 1.5V ASYNCHRONOUS CONTROL ov PRESET 3V CLEAR 1.5V ETC. av SYNCHRONOUS CONTROL av PRESET =M, ov 2564 drw 10 CLEAR CLOCK ENABLE ETC. PROPAGATION DELAY SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION 2564 drw 12 MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCH POSITION Test Switch Open Drain Disable Low Closed Enable Low All Other Tests Open DEFINITIONS: 2564 Ink 13 Ci= Load capacitance: includes jig and probe capacitance. Rt= Termination resistance: should be equal to ZouT of the Pulse Generator. PULSE WIDTH LOW-HIGH-LOW PULSE 1.5V tw HIGH-LOW-HIGH 1.5V PULSE 2564 drw 11 ENABLE AND DISABLE TIMES ENABLE DISABLE = ff WV CONTROL 1.5V INPUT ov La QUTPUT 3.5V NORMALLY LOW 0.3V VoL TT _ OUTPUT gwitcH gay OH NORMALLY Open Rae HIGH Pov ov 2564 drw 13 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for Ail Pulses: Rate < 1.0MHz; tr < 2.5ns; ta < 2.5nsIDT54/74FCT373T/AT/CTIDT - 2373T/ATICT, IDT54/74FCTS33T/ATICT, IDT54/74FCTS73T/AT/CTIDT - 2573T/ATICT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT Xx XXXX X X Temp. Range Family Device Type Package Process Blank Commercial B MIL-STD-883, Class B P Plastic DIP D CERDIP so Small Outline IC L Leadless Chip Carrier E CERPACK PY Shrink Smail Outline Package Q Quarter-size Small Outline Package 373T Non-Inverting Octal Transparent Latch 573T Non-Inverting Octal Transparent Latch 533T Inverting Octal Transparent Latch Blank High Drive 2 Balanced Drive | 54 -55C to +125C | 74 0C to +70C 2564 drw 14.