DATA SH EET
Product specification
Supersedes data of 2003 Aug 29 2003 Dec 12
INTEGRATED CIRCUITS
74HC32; 74HCT32
Quad 2-input OR gate
2003 Dec 12 2
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
FEATURES
•Wide supply voltage range from 2.0 to 6.0 V
•Symmetrical output impedance
•High noise immunity
•Low power dissipation
•Balanced propagation delays
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
GENERAL DESCRIPTION
The 74HC/HCT32 is a high-speed Si-gate CMOS device
and is pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT32 provides the 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. For 74HC32 the condition is VI= GND to VCC.
For 74HCT32 the condition is VI= GND to VCC −1.5 V.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/tPLH propagation delay nA, nB to nY CL= 15 pF; VCC =5V69ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per gate notes 1 and 2 16 28 pF
INPUT OUTPUT
nA nB nY
LLL
LHH
HLH
HHH
2003 Dec 12 3
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
ORDERING INFORMATION
TYPE NUMBER PACKAGE
TEMPERATURE
RANGE PINS PACKAGE MATERIAL CODE
74HC32N −40 to +125 °C 14 DIP14 plastic SOT27-1
74HCT32N −40 to +125 °C 14 DIP14 plastic SOT27-1
74HC32D −40 to +125 °C 14 SO14 plastic SOT108-1
74HCT32D −40 to +125 °C 14 SO14 plastic SOT108-1
74HC32DB −40 to +125 °C 14 SSOP14 plastic SOT337-1
74HCT32DB −40 to +125 °C 14 SSOP14 plastic SOT337-1
74HC32PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1
74HCT32PW −40 to +125 °C 14 TSSOP14 plastic SOT402-1
74HC32BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1
74HCT32BQ −40 to +125 °C 14 DHVQFN14 plastic SOT762-1
PINNING
PIN SYMBOL DESCRIPTION
1 1A data input
2 1B data input
3 1Y data output
4 2A data input
5 2B data input
6 2Y data output
7 GND ground (0 V)
8 3Y data output
9 3A data input
10 3B data input
11 4Y data output
12 4A data input
13 4B data input
14 VCC supply voltage
handbook, halfpage
MNA240
32
1
2
3
4
5
6
78
14
13
12
11
10
9
1A
1B
1Y
2A
2B
2Y
GND 3Y
3A
3B
4Y
4A
4B
VCC
Fig.1 Pin configuration DIP14, SO14 and
(T)SSOP14.
2003 Dec 12 4
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
handbook, halfpage
114
GND(1)
1A VCC
7
2
3
4
5
6
1B
1Y
2A
2B
2Y
13
12
11
10
9
4B
4A
4Y
3B
3A
8
GND
Top view 3Y
MNB060
Fig.2 Pin configuration DHVQFN14.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA242
1A
1B 1Y
2
13
2A
2B 2Y
5
46
3A
3B 3Y
10
98
4A
4B 4Y
13
12 11
Fig.3 Logic symbol.
handbook, halfpage
MNA243
3
≥ 1
≥ 1
≥ 1
≥ 1
2
1
6
5
4
8
10
9
11
13
12
Fig.4 Logic symbol (IEEE/IEC).
handbook, halfpage
MNA241
A
B
Y
Fig.5 Logic diagram (one gate).
2003 Dec 12 5
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For DIP14 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS 74HC32 74HCT32 UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 −VCC 0−VCC V
VOoutput voltage 0 −VCC 0−VCC V
Tamb operating ambient
temperature −40 +25 +125 −40 +25 +125 °C
tr,t
finput rise and fall times VCC = 2.0 V −−1000 −−−ns
VCC = 4.5 V −6.0 500 −6.0 500 ns
VCC = 6.0 V −−400 −−−ns
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +7.0 V
IIK input diode current VI<−0.5 V or VI>V
CC + 0.5 V; note 1 −±20 mA
IOK output diode current VO<−0.5 V or VO>V
CC + 0.5 V; note 1 −±20 mA
IOoutput source or sink current −0.5V<V
O<V
CC + 0.5 V; note 1 −±25 mA
ICC; IGND VCC or GND current note 1 −±50 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation Tamb =−40 to +125 °C; note 2 −300 mW
2003 Dec 12 6
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
DC CHARACTERISTICS
Family 74HC
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
Tamb =25°C; note 1
VIH HIGH-level input
voltage 2.0 1.5 1.2 −V
4.5 3.15 2.4 −V
6.0 4.2 3.2 −V
VIL LOW-level input voltage 2.0 −0.8 0.5 V
4.5 −2.1 1.35 V
6.0 −2.8 1.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−20 µA 2.0 1.9 2.0 −V
IO=−20 µA 4.5 4.4 4.5 −V
IO=−20 µA 6.0 5.9 6.0 −V
IO=−4.0 mA 4.5 3.98 4.32 −V
IO=−5.2 mA 6.0 5.48 5.81 −V
VOL LOW-level output
voltage VI=V
IH or VIL
IO=20µA 2.0 −0 0.1 V
IO=20µA 4.5 −0 0.1 V
IO=20µA 6.0 −0 0.1 V
IO= 4.0 mA 4.5 −0.15 0.26 V
IO= 5.2 mA 6.0 −0.16 0.26 V
ILI input leakage current VI=V
CC or GND 6.0 −−±0.1 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 6.0 −−2.0 µA
2003 Dec 12 7
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
Tamb =−40 to +85 °C
VIH HIGH-level input
voltage 2.0 1.5 −−V
4.5 3.15 −−V
6.0 4.2 −−V
VIL LOW-level input voltage 2.0 −−0.5 V
4.5 −−1.35 V
6.0 −−1.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−20 µA 2.0 1.9 −−V
IO=−20 µA 4.5 4.4 −−V
IO=−20 µA 6.0 5.9 −−V
IO=−4.0 mA 4.5 3.84 −−V
IO=−5.2 mA 6.0 5.34 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO=20µA 2.0 −−0.1 V
IO=20µA 4.5 −−0.1 V
IO=20µA 6.0 −−0.1 V
IO= 4.0 mA 4.5 −−0.33 V
IO= 5.2 mA 6.0 −−0.33 V
ILI input leakage current VI=V
CC or GND 6.0 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 6.0 −−20 µA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
2003 Dec 12 8
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
Note
1. All typical values are measured at Tamb =25°C.
Tamb =−40 to +125 °C
VIH HIGH-level input
voltage 2.0 1.5 −−V
4.5 3.15 −−V
6.0 4.2 −−V
VIL LOW-level input voltage 2.0 −−0.5 V
4.5 −−1.35 V
6.0 −−1.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−20 µA 2.0 1.9 −−V
IO=−20 µA 4.5 4.4 −−V
IO=−20 µA 6.0 5.9 −−V
IO=−4.0 mA 4.5 3.7 −−V
IO=−5.2 mA 6.0 5.2 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO=20µA 2.0 −−0.1 V
IO=20µA 4.5 −−0.1 V
IO=20µA 6.0 −−0.1 V
IO= 4.0 mA 4.5 −−0.4 V
IO= 5.2 mA 6.0 −−0.4 V
ILI input leakage current VI=V
CC or GND 6.0 −−±0.1 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 6.0 −−40 µA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
2003 Dec 12 9
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
Family 74HCT
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
Tamb =25°C; note 1
VIH HIGH-level input
voltage 4.5 to 5.5 2.0 1.6 −V
VIL LOW-level input
voltage 4.5 to 5.5 −1.2 0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−20 µA 4.5 4.4 4.5 −V
IO=−4 mA 4.5 3.98 4.32 −V
VOL LOW-level output
voltage VI=V
IH or VIL
IO=20µA 4.5 −0 0.1 V
IO= 4 mA 4.5 −0.15 0.25 V
ILI input leakage current VI=V
CC or GND 5.5 −−±0.1 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 5.5 −−2.0 µA
∆ICC additional quiescent
supply current per
input
VI=V
CC −2.1 V;
IO=0 4.5 to 5.5 −−430 µA
Tamb =−40 to +85 °C
VIH HIGH-level input
voltage 4.5 to 5.5 2.0 −−V
VIL LOW-level input
voltage 4.5 to 5.5 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−20 µA 4.5 4.4 −−V
IO=−4 mA 4.5 3.84 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO=20µA 4.5 −−0.1 V
IO= 4 mA 4.5 −−0.33 V
ILI input leakage current VI=V
CC or GND 5.5 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 5.5 −−20 µA
∆ICC additional quiescent
supply current per
input
VI=V
CC −2.1 V;
IO=0 4.5 to 5.5 −−540 µA
2003 Dec 12 10
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
Note
1. All typical values are measured at Tamb =25°C.
Tamb =−40 to +125 °C
VIH HIGH-level input
voltage 4.5 to 5.5 2.0 −−V
VIL LOW-level input
voltage 4.5 to 5.5 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−20 µA 4.5 4.4 −−V
IO=−4 mA 4.5 3.7 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO=20µA 4.5 −−0.1 V
IO= 4 mA 4.5 −−0.4 V
ILI input leakage current VI=V
CC or GND 5.5 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 5.5 −−40 µA
∆ICC additional quiescent
supply current per
input
VI=V
CC −2.1 V;
IO=0 4.5 to 5.5 −−590 µA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
2003 Dec 12 11
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
AC CHARACTERISTICS
Family 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF.
Note
1. All typical values are measured at Tamb =25°C.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =25°C; note 1
tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 2.0 −22 90 ns
4.5 −818ns
6.0 −615ns
tTHL/tTLH output transition time see Figs 6 and 7 2.0 −19 75 ns
4.5 −715ns
6.0 −613ns
Tamb =−40 to +85 °C
tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 2.0 −−115 ns
4.5 −−23 ns
6.0 −−20 ns
tTHL/tTLH output transition time see Figs 6 and 7 2.0 −−95 ns
4.5 −−19 ns
6.0 −−16 ns
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 2.0 −−135 ns
4.5 −−27 ns
6.0 −−23 ns
tTHL/tTLH output transition time see Figs 6 and 7 2.0 −−110 ns
4.5 −−22 ns
6.0 −−19 ns
2003 Dec 12 12
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
Family 74HCT
GND = 0 V; tr=t
f= 6 ns; CL=50pF.
Note
1. All typical values are measured at Tamb =25°C.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =25°C; note 1
tPHL/tPLH propagation
delay nA, nB to nY see Figs 6 and 7 4.5 −11 24 ns
tTHL/tTLH output transition time see Figs 6 and 7 4.5 −715ns
Tamb =−40 to +85 °C
tPHL/tPLH propagation
delay nA, nB to nY see Figs 6 and 7 4.5 −−30 ns
tTHL/tTLH output transition time see Figs 6 and 7 4.5 −−19 ns
Tamb =−40 to +125 °C
tPHL/tPLH propagation
delay nA, nB to nY see Figs 6 and 7 4.5 −−36 ns
tTHL/tTLH output transition time see Figs 6 and 7 4.5 −−22 ns
2003 Dec 12 13
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
AC WAVEFORMS
handbook, halfpage
MNA735
tPLH
tPHL
VM
VM
90%
10%
VMVM
nY output
nA, nB input
VI
GND
VOH
VOL
tTLH
tTHL
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
74HC32 : VM= 50%; VI= GND to VCC.
74HCT32: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
open
GND
VCC
VCC
VIVO
MNA245
D.U.T.
CL
RT
1000 Ω
PULSE
GENERATOR
S1
Fig.7 Load circuitry for switching times.
TEST S1
tPLH/tPHL open
tPLZ/tPZL VCC
tPHZ/tPZH GND
Definitions for test circuit:
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
2003 Dec 12 14
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
PACKAGE OUTLINES
UNIT A
max.
1 2 (1) (1)
b
1
cD
(1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
M
E
e
1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w
M
b
1
e
D
A
2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
2003 Dec 12 15
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
UNIT A
max. A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2003 Dec 12 16
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
17
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
2003 Dec 12 17
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
w
M
b
p
D
Z
e
0.25
17
14 8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
2003 Dec 12 18
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A
(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
2003 Dec 12 19
Philips Semiconductors Product specification
Quad 2-input OR gate 74HC32; 74HCT32
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratany otherconditionsabove thosegivenin the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warrantythatsuchapplicationswill be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusing orsellingthese products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands R44/04/pp20 Date of release: 2003 Dec 12 Document order number: 9397 750 12488
