CY22388/89/91 Factory Programmable Quad PLL Clock Generator with VCXO Features Benefits *Fully integrated phase-locked loops (PLLs) *QFN package: *40% smaller than 20-pin TSSOP *22% smaller than 16-pin TSSOP *Selectable Output Frequency *Programmable Output Frequencies *Out putFr equenc yRangeof5-166MHz *Input Frequency Range *Cr ys t al :10-30MHz *Ext er nal Ref er ence:1-100MHz *Analog VCXO *16-/20-pin TSSOP and 32-pin QFN packages *3.3V operation with 2.5V output buffer option *Meets most Digital Set Top Box, DVD Recorder, and DTV application requirements *Multiple high-performance PLLs allow synthesis of unrelated frequencies *Integration eliminates the need for external loop filter components *Meets critical timing requirements in complex system designs *Enables application compatibility *Complete VCXO solution with 120 ppm (typical pull range) Block Diagram C LK A C LK B P LL1 C LK C X IN VC X O P LL2 XOUT C LK D D ivider & M ultiplexer V IN C LK E P LL3 C LK F P LL4 C LK G C LK H FS 0/1/2 S elect Logic 25 VDD 1 24 O E /P D # 2 23 FS2 FS2 VD D 3 22 VDD 16 VIN VSS 4 6 15 VD D VSS 5 VSS 6 19 VSS 7 14 VSS VSS 7 18 C LK G C LKH 8 17 C LK F 3 14 FS2 CLKH 4 17 V IN 4 13 VDD VDD 5 VD D 5 12 VSS VSS VSS 6 11 C LK E CLKD C Y22389 CLK F CLKC 10 11 CLK E * 198 Champion Court 15 CLK G 12 21 VDD 20 VSS 16 13 9 14 8 CLKA 13 CLKB C LK C 12 C LK D 9 11 10 8 9 7 C LK B 10 C LK A C Y22391 VDD FS 1 CLKE VDD CLKC 15 NC 2 Cypress Semiconductor Corporation Document #: 38-07734 Rev. *B 26 VDD V IN VD D FS 0 FS 1 C Y 2 23 88 NC O E /P D 27 XOUT 18 NC VD D 3 28 XOUT CLKA 16 CLKB 1 29 XO UT 19 30 XIN 20 2 32 FS1 1 31 FS0 X IN FS 0 16 -P in TS S O P X IN 3 2 -P in Q F N 20-P in TSSO P NC Pin Configurations CLKD OE * San Jose, CA 95134-1709 * 408-943-2600 Revised October 10, 2006 CY22388/89/91 Pin Description Pin Name Pin Number 16-Pin TSSOP 20-Pin TSSOP Pin Description 32-Pin QFN XIN 1 1 30 Crystal Input or Reference Clock Input XOUT 16 20 27 Crystal Output (No connect if external clock is used) CLKA 7 9 11 Clock Output CLKB 8 8 10 Clock Output CLKC 9 10 14 Clock Output CLKD 10 7 9 Clock Output CLKE 11 11 15 Clock Output CLKF n/a 12 17 Clock Output CLKG n/a 13 18 Clock Output CLKH n/a 4 8 Clock Output 2 2 31 Frequency Select 0 FS0 FS1 3 3 32 Frequency Select 1 FS2 14 17 23 Frequency Select 2 OE/PD n/a 18 24 Output Enable Control/Power Down VIN 4 16 1 Analog Control Input for VCXO VDD 5,13,15 5,15,19 2,3,16,21,22,25,26 VSS 6,12 6,14 4,5,6,7,19,20 Ground NC n/a n/a 12,13,28,29 No Connect. Voltage Supply General Description crystal. Generally a design may require up to four oscillators to accomplish what could be done with a single CY22388. The CY22388 family of devices has an Analog VCXO (Voltage Controlled Crystal Oscillator), 4 PLLs, up to 8 clock outputs and frequency selection capabilities. The frequency selects do not modify any PLL frequency. Instead they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. This is illustrated in the following Frequency Selection tables and Functional Block Diagram. Each PLL is independent and can be configured to generate a VCO (Voltage Controlled Oscillator) frequency between 62.5 MHz and 250 MHz. Each PLL can then in turn be divided down with post dividers to generate the clock output frequency oft he us er ' schoi c e.Theout putdi v i deral l owseachcl oc k output to be divided by 1,2,3,4,5,6,8,9,10,12,15. The PLL maximum is reduced to 166 MHz in divide by 1 mode due to output buffer limitations. There is one programmable OE/PDWN. The OE/PDWN pin can be programmed as either an output enable pin or a power-down pin. The OE function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. Full-chip power down will disable all outputs as well as the PLLs and most of the active circuitry when low. Outputs that allow frequency switching perform the transition free of glitches. A glitch is defined as a high or low time shorter than half the smaller of the two periods being switched between. Extended low time (even many cycles in duration) is acceptable. Factory-Programmable CY22388/89/91 Factory programming is available for high- or low-volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. PLLs The advantage of having four PLLs is that a single device can generate up to four independent frequencies from a single Document #: 38-07734 Rev. *B Selected clock outputs are capable of being powered off a separate 2.5V supply. This will allow for driving lower voltage swing inputs. The CY22388/89/91 device still requires 3.3V to power the oscillator and all other internal PLL circuitry. For the 2.5V output option please refer to the CY22388 Application Note. Selected clocks and pinout diagrams will be explained in this application note. Clock D can obtain its output from either the reference source or PLL1/N1 with N1 being defined as the output divider for PLL1. Clock H is defined as a copy of clock D. Clock D is only available from PLL1/N1 on the 16-pin package. For CY22388, CLKB and CLKC have related frequencies. For CY22389 and CY22391, CLKD and CLKF have related frequencies, CLKA and CLKB have related frequencies, and Page 2 of 10 CY22388/89/91 CLKC and CLKE have related frequencies. Related frequencies come from the same PLL but can have different divider values. In order to minimize PPM (Parts Per Million) error on the clock outputs, a user should choose a crystal reference frequency that is a common multiple of the desired PLL frequencies. While this would be the ideal situation, this is not always the case and the PLLs have high-resolution counters internally to help minimize frequency deviation from the desired frequency. Frequency Select Pin Operation Table 1. CY22388 16-pin TSSOP Output Signal CLOCK A S2S1S0 CLOCK B S1S0 CLOCK C & CLOCK D S0 CLOCK E FIXED PLL VCO frequencies are generated by the following equation: FVCO = FREF * (P / Q) Table 2. CY22389 20-pin TSSOP Where FREF is the reference input frequency, P is the PLL feedback divider and Q is the reference input divider. Output Signal A PLL is a feedback system where the VCO frequency divided by P and reference frequency divided by Q are constantly being compared and the VCO frequency is adjusted to achieve a locked state. Figure 1 is a simplified drawing of a PLL. Figure 1. F R E F /Q V C O a nd O th e r c o m p o n e n ts F V C O Frequency Selection Lines CLOCK A S2S1S0 CLOCK B & CLOCK C S1S0 CLOCK D, CLOCK E, & CLOCK F S0 CLOCK G FIXED CLOCK H COPY OF CLOCK D Table 3. CY22391 32-pin QFN Output Signal /P Frequency Selection Lines Frequency Selection Lines CLOCK A S2S1S0 CLOCK B & CLOCK C S1S0 CLOCK D, CLOCK E, & CLOCK F S0 Document #: 38-07734 Rev. *B CLOCK G FIXED CLOCK H COPY OF CLOCK D Page 3 of 10 CY22388/89/91 There are three programmable reference operating modes for the CY22388/89/91 family of devices. The first mode utilizes an external pullable crystal and incorporates an internal Analog VCXO. The second mode configures the internal crystal oscillator to accept an external driven reference source from 1 to 100 MHz. The input capacitance on the XIN PIN when driven in this mode is 15 pF. The third mode disables the VCXO input control and sets the internal oscillator to a fixed frequency operation. The load capacitance seen by the external crystal when connected to PINS XIN and XOUT is equal to 12 pF. One of the key components to the CY22388/89/91 family of dev i c esi st heanal ogVCXO.TheVCXO i sus edt o" pul l "t he reference crystal higher or lower in order to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. The VCXO is completely analog, so there is infinite resolution on the VCXO pull curve. The Analog to Digital Converter steps that are normally associated with a digital VCXO input is not present in this device. A special pullable crystal must be used to in order to have adequate VCXO pull range. Pullable Crystal specifications are included in this data sheet. Document #: 38-07734 Rev. *B Please refer to the CY22388/89/91 Application Note for pullable crystal recommendations outside of the standard industry frequencies given in the Pullable Crystal Specifications. VCXO Profile Figure 2 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset. Figure 2. VCXO Profile . 200 150 100 Tuning [ppm] Analog VCXO 50 0 -50 0 0.5 1 1.5 2 2.5 3 3.5 -100 -150 -200 VCXO input [V] Page 4 of 10 CY22388/89/91 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit -0. 5 4.6 V -0. 5 VDD + 0.5 VDC Non-Functional -65 +125 C MIL-STD-883, Method 3015 2000 - Volts 10 ppm VDD/AVDD/VDDL Core Supply Voltage VIN Input Voltage Relative to VSS TS Temperature, Storage ESDHBM ESD Protection (Human Body Model) UL-94 Flammability Rating V-0 @1/8 in. MSL Moisture Sensitivity Level QFN package 3 16- and 20-pin TSSOP 1 - Pullable Crystal Specifications[1, 3] Parameter Description Comments Min. FNOM 13.5-MHz and 27-MHz Crystal AT-Cut Parallel resonance, Fundamental mode CLNOM Nominal Load Capacitance Order crystal at one specific CLNOM 0 ppm R1 Equivalent Series Resistance (ESR) DL Crystal Drive Level C0[2] Crystal Shunt Capacitance 1.5 C1[2] Crystal Motional Capacitance 12 F3SEPHI [3] F3SEPLO[3] Typ. Max. Unit See Note 3 11.4 12 12.6 pF Fundamental mode (CL = Series) - - 40 Nominal VDD @ 25C over 120 PPM Pull Range - - 300 W 3 4.0 pF 14 16.8 fF - ppm Third Overtone Separation from 3*FNOM Mechanical Third (High side of 3*FNOM) 240 - Third Overtone Separation from 3*FNOM Mechanical Third (Low side of 3*FNOM) - - -120 ppm Recommended Operating Conditions Min. Typ. Max. Unit VDD/AVDD/VDDL Operating Voltage Parameter Description 3.0 3.3 3.6 V TA Ambient Temperature -10 - 70 C CLOAD Maximum Load Capacitance - - 15 pF tPU Power-up time for all VDDs reach minimum specified voltage (power ramps must be monotonic) 0.05 - 500 ms Notes 1. Device operates to the following specs, which are guaranteed by design. 2. Increased tolerance available from pull range less than 120PPM. 3. Refer to CY22388 Application Note and online software for a list of Approved Crystal Specifications. Document #: 38-07734 Rev. *B Page 5 of 10 CY22388/89/91 DC Parameters[4] Parameter Description Min. Typ. Max. Unit VOH = VDD -0. 5,VDD = 3.3V 12 - - mA VOL = 0.5, VDD = 3.3V 12 - - mA Input High Current VIH = VDD, excluding Vin, Xin - 5 10 A Input Low Current VIL = 0V, excluding Vin, Xin - 5 10 A VIH Input High Voltage FS0/1/2 OE input CMOS levels 0.7xAVDD - - V VIL Input Low Voltage FS0/1/2 OE input CMOS levels - - 0.3xAVDD V VVCXO VIN Input Range 0 - AVDD V CIN Input Capacitance FS0/1/2 and OE Pins only - - 7 pF IVDD Supply Current VDD/AVDD/VDDL Current - 60 - mA CINXIN Input Capacitance at XIN VCXO Disabled External Reference - 15 - pF CINXTAL Input Capacitance at Crystal - 12 - pF IOH[5] IOL[5] Output High Current Output Low Current IIH IIL Conditions VCXO Disabled Fixed Freq. Oscillator AC Parameters Parameter[4] Description Conditions Min. Typ. Max. Units 1/t1 Output Frequency PLL minmax/Dividermaximum 4.2 - 166 MHz DC1 Output Duty Cycle (excluding REFOUT Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD 45 50 55 % Output Duty Cycle Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD 40 50 60 % 40 50 60 % DC2 External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz) External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is 125 MHz) DCREFOUT Output Duty Cycle Duty Cycle is defined in Figure 4; t2/t1, 50% of VDD (XIN Duty Cycle = 45/55%) ER Rising Edge Rate Output Clock Edge Rate. Measured from 20% to 80% of VDD. CLOAD = 15 pF. See Figure 5. 0.75 1.2 - V/ns EF Falling Edge Rate Output Clock Edge Rate. Measured from 80% to 20% of VDD. CLOAD = 15pF See Figure 5. 0.75 1.2 - V/ns T9 Clock Jitter Period Jitter - 250 - ps T10 PLL Lock Time - 1 5 ms fXO VCXO Crystal Pull Range - ppm - ppm Using non- SMD-49 crystal specified in " CY22388Appl i cat i on 110 120 Not e,ANC0002" Nominal Crystal Frequency Input assumed (0 ppm)@25C and 3.3V Using SMD-49 crystal specified in " CY22388Appl i c at i on Not e,ANC0002" 105 120 Nominal Crystal Frequency Input assumed (0 ppm)@25C and 3.3V Notes 4. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. 5. Custom Drive level and is available upon request Document #: 38-07734 Rev. *B Page 6 of 10 CY22388/89/91 Test and Measurement Set-up Figure 3. Test and Measurement V DDs O utputs DUT C LO A D 0.1F GND Voltage and Timing Definitions Figure 4. Duty Cycle Definition t1 t2 V DD 50% of V DD Clock O utput 0V Figure 5. ER = (0.6 VDD)/t3, EF = (0.6 VDD)/t4 t3 t4 V DD 80% of V DD 20% of V DD Clock O utput 0V Figure 6. FS Controlled Clock Output Finish Cycle Start at Full Cycle FS TWAIT Document #: 38-07734 Rev. *B Page 7 of 10 CY22388/89/91 Ordering Information Part Number[6] Type Production Flow Lead-free CY22388ZXC-XXX 16-pin TSSOP Commercial, 0C to +70C CY22389ZXC-XXX 20-pin TSSOP Commercial, 0C to +70C CY22391LFXC-XXX 32-pin QFN Commercial, 0C to +70C Package Drawing and Dimensions Figure 7. 16-lead TSSOP 4.40 mm Body Z16.173 51-85091-*A Note 6. The CY22388ZXC-xxx, CY22389ZXC-xxx, and CY22391LFXC-xxx are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document #: 38-07734 Rev. *B Page 8 of 10 CY22388/89/91 Figure 8. 20-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z20 51-85118-*A Figure 9. 32-Lead QFN (5 x 5 mm) LF32A 51-85188-*A All product and company names mentioned in this document are trademarks of their respective holder. Document #: 38-07734 Rev. *B Page 9 of 10 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY22388/89/91 Document History Page Document Title: CY22388/89/91 Factory Programmable Quad PLL Clock Generator with VCXO Document Number: 38-07734 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 320458 See ECN RGL New data sheet *A 389649 See ECN RGL Changed R1 value to max. 40 Changed DL comments and max. value to 300W Changed fXO min. value to 110ppm and typ. value to 120ppm *B 523597 See ECN RGL Specified a non-SMD-49 and SMD-49 crystal specs in the VCXO Pull Range Parameter Document #: 38-07734 Rev. *B Page 10 of 10