Precision Picoampere Input Current
Quad Operational Amplifier
OP497
Rev. E
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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FEATURES
Low offset voltage: 75 μV maximum
Low offset voltage drift: 1.0 μV/°C maximum
Very low bias current
25°C: 150 pA maximum
−40°C to +85°C: 300 pA maximum
Very high open-loop gain: 2000 V/mV minimum
Low supply current (per amplifier): 625 μA maximum
Operates from ±2 V to ±20 V supplies
High common-mode rejection: 114 dB minimum
APPLICATIONS
Strain gage and bridge amplifiers
High stability thermocouple amplifiers
Instrumentation amplifiers
Photocurrent monitors
High gain linearity amplifiers
Long-term integrators/filters
Sample-and-hold amplifiers
Peak detectors
Logarithmic amplifiers
Battery-powered systems
GENERAL DESCRIPTION
The OP497 is a quad op amp with precision performance in
the space-saving, industry standard 16-lead SOlC package.
Its combination of exceptional precision with low power and
extremely low input bias current makes the quad OP497 useful
in a wide variety of applications.
Precision performance of the OP497 includes very low offset
(<50 µV) and low drift (<0.5 µV/°C). Open-loop gain exceeds
2000 V/mV ensuring high linearity in every application. Errors
due to common-mode signals are eliminated by its common-
mode rejection of >120 dB. The OP497 has a power supply
rejection of >120 dB which minimizes offset voltage changes
experienced in battery-powered systems. The supply current
of the OP497 is <625 µA per amplifier, and it can operate with
supply voltages as low as ±2 V.
The OP497 uses a superbeta input stage with bias current
cancellation to maintain picoamp bias currents at all temperatures.
This is in contrast to FET input op amps whose bias currents
start in the picoamp range at 25°C but double for every 10°C
rise in temperature to reach the nanoamp range above 85°C.
The input bias current of the OP497 is <100 pA at 25°C.
PIN CONNECTIONS
OUT A 1
–IN A 2
+IN A 3
V+ 4
OUT D
16
–IN D
15
+IN D
14
V–
13
+IN B 5
–IN B 6
OUT B
NC
7
+IN C
12
–IN C
11
OUT C
NC
10
89
OP497
NC = NO CONNECT
00309-001
Figure 1. 16-Lead Wide Body SOIC (RW-16)
OUT A
1
–IN A
2
+IN A
3
V+
4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B
5
–IN B
6
OUT B
7
+IN C
10
–IN C
9
OUT C
8
OP497
00309-002
Figure 2. 14-Lead PDIP (N-14)
1k
100
10
+IB
IOS
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
VS = ±15V
VCM = 0V
INPUT CURRENT ( p A)
0
0309-003
–IB
Figure 3. Input Bias, Offset Current vs. Temperature
Combining precision, low power, and low bias current, the OP497
is ideal for a number of applications, including instrumentation
amplifiers, log amplifiers, photodiode preamplifiers, and long-
term integrators. For a single device, see the OP97 data sheet,
and for a dual device, see the OP297 data sheet.
OP497
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connections ............................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Typical Performance Characteristics ............................................. 5
Applications Information .............................................................. 10
AC Performance ......................................................................... 10
Guarding And Shielding ........................................................... 11
Open-Loop Gain Linearity ....................................................... 11
Applications Circuit ....................................................................... 12
Precision Absolute Value Amplifier ......................................... 12
Precision Current Pump ............................................................ 12
Precision Positive Peak Detector .............................................. 12
Simple Bridge Conditioning Amplifier ................................... 12
Nonlinear Circuits ...................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
2/09—Rev. D to Rev. E
Deleted 14-Lead CERDIP ............................................. Throughout
Changes to Features Section and General Description
Section ................................................................................................ 1
Delete Military Processed Devices Text, SMD Part Number,
ADI Part Number Table, and Dice Characteristics Figure ......... 3
Changes to Table 1 ............................................................................ 3
Changes to Absolute Maximum Ratings Section ......................... 4
Changes to Figure 12 ........................................................................ 6
Changes to Figure 18 and Figure 19 ............................................... 7
Changes to Figure 26 and Figure 28 ............................................... 8
Deleted OP497 Spice Macro-Model Section ............................... 10
Changes to Applications Information Section ............................ 10
Moved Figure 33 ............................................................................. 10
Deleted Table I. OP497 SPICE Net-List....................................... 11
Changes to Open-Loop Gain Linearity Section and
Figure 35 .......................................................................................... 11
Changes to Figure 40 ...................................................................... 13
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
11/01—Rev. C to Rev. D
Edits to Pin Connection Headings .................................................. 1
Deleted Wafer Test Limits ................................................................ 3
Edits to Absolute Maximum Ratings .............................................. 5
Edits to Outline Dimensions ......................................................... 16
Edits to Ordering Guide ................................................................ 17
OP497
Rev. E | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VS = ±15 V, unless otherwise noted.
Table 1.
F Grade G Grade
Parameter Symbol Condition Min Typ Max Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 40 75 80 150 μV
−40°C ≤ +85°C 70 150 120 250 μV
Average Input Offset Voltage Drift TCVOS T
MIN − TMAX 0.4 1.0 0.6 1.5 μV/°C
Long-Term Input Offset Voltage
Stability
0.1 0.1 μV/Month
Input Bias Current IB V
CM = 0 V 40 150 60 200 pA
−40° ≤ TA ≤ +85°C 60 200 80 300 pA
Average Input Bias Current Drift TCIB −40° ≤ TA ≤ +85°C 0.3 0.3 pA/°C
Input Offset Current IOS V
CM = 0 V 30 150 50 200 pA
−40° ≤ TA ≤ +85°C 50 200 80 300 pA
Average Input Offset Current Drift TCIOS 0.3 0.4 pA/°C
Input Voltage Range1 IVR ±13 ±14 ±13 ±14 V
T
MIN − TMAX ±13 ±13.5 ±13 ±13.5 V
Common-Mode Rejection CMR VCM = ±13 V 114 135 114 135 dB
T
MIN − TMAX 108 120 108 120 dB
Large Signal Voltage Gain AVO V
O = ±10 V, RL = 2 kΩ 1500 4000 1200 4000 V/mV
−40° ≤ TA ≤ +85°C 800 2000 800 2000 V/mV
Input Resistance Differential Mode RIN 30 30 MΩ
Input Resistance Common Mode RINCM 500 500 GΩ
Input Capacitance CIN 3 3 pF
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 2 kΩ ±13 ±13.7 ±13 ±13.7 V
R
L = 10 kΩ, TMIN − TMAX ±13 ±14 ±13 ±14 V
R
L = 10 kΩ ±13 ±13.5 ±13 ±13.5 V
Short Circuit ISC ±25 ±25 mA
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2 V to ±20 V 114 135 114 135 dB
V
S = ±2.5 V to ±20 V, TMIN − TMAX 108 120 108 120 dB
Supply Current (per Amplifier) ISY No load 525 625 525 625 μA
T
MIN − TMAX 580 750 580 750 μA
Supply Voltage Range VS Operating range ±2 ±20 ±2 ±20 V
T
MIN − TMAX ±2.5 ±20 ±2.5 ±20 V
DYNAMIC PERFORMANCE
Slew Rate SR 0.05 0.15 0.05 0.15 V/μs
Gain Bandwidth Product GBW 500 500 kHz
Channel Separation CS VO = 20 V p-p, fO = 10 Hz 150 150 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.3 0.3 μV/p-p
Voltage Noise Density en e
n = 10 Hz 17 17 nV/√Hz
e
n = 1 kHz 15 15 nV/√Hz
Current Noise Density in in = 10 Hz 20 20 fA/√Hz
1 Guaranteed by CMR test.
OP497
Rev. E | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply to packaged parts.
Table 2.
Parameter Rating
Supply Voltage ±20 V
Input Voltage1 20 V
Differential Input Voltage1 40 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 For supply voltages less than ±20 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case mounting conditions, that is,
θJA is specified for a device in socket for the PDIP package, and
θJA is specified for a device soldered to the printed circuit board
(PCB) for the SOIC package.
Table 3.
Package Type θJA θ
JC Unit
14-Lead PDIP (N-14) 76 33 °C/W
16-Lead SOIC (RW-16) 92 23 °C/W
1/4
OP497
V
2
2kΩ
CHANNEL S E P ARAT IO N = 20 log
()
–
+
50Ω
50kΩ
–
+
1/4
OP497
V
1
20V p - p @ 10Hz
V
1
V
2
/10,000
00309-004
Figure 4. Channel Separation Test Circuit
ESD CAUTION
OP497
Rev. E | Page 5 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = ±15 V, unless otherwise noted.
50
0
30
10
20
40
PERCENTAGE OF UNITS
INPUT OFFSET VOLT AGE (µV)
TA = 25° C
VS = ±15V
VCM = 0V
–100 –80 –60 –40 –20 0 20 40 60 80 100
00309-006
Figure 5. Typical Distribution of Input Offset Voltage
50
0
30
10
20
40
PERCENT AG E OF UNI T S
INPUT BIAS CURRE NT ( pA)
T
A
= 25°C
V
S
= ±15V
V
CM
= 0V
–100 –80 –60 –40 –20 0 20 40 60 80 100
0
0309-007
Figure 6. Typical Distribution of Input Bias Current
PERCENT AG E OF UNI T S
60
060
30
10
10
20
0
50
40
50403020
INPUT OFFSET CURRENT (p A)
T
A
= 25°C
V
S
= ±15V
V
CM
= 0V
0
0309-008
Figure 7. Typical Distribution of Input Offset Current
PERCENTAGE OF UNITS
50
00.8
30
10
0.1
20
0
40
0.70.60.50.40.30.2
TCV
OS
(µV/°C)
V
S
= ±15V
V
CM
= 0V
0
0309-009
Figure 8. Typical Distribution of TCVOS
1k
100
10
TEM P ERATURE (°C)
+I
B
I
OS
INPUT CURRENT (pA)
–75 –50 –25 0 25 50 75 100 125
00309-010
V
S
= ±15V
V
CM
= 0V
–I
B
Figure 9. Input Bias, Offset Current vs. Temperature
70
015
30
10
–10
20
–15
60
40
50
1050–5
–I
B
+I
B
INPUT BIAS CURRE NT (pA)
COMMON-MO DE VO L TAGE (V)
T
A
= 25° C
V
S
= ±15V
0
0309-011
Figure 10. Input Bias Current vs. Common-Mode Voltage
OP497
Rev. E | Page 6 of 16
±3
051
±1
0
±2
432
DEVIATION FROM FINAL VALUE (µV)
TIME AFT ER POWER APPLIED (M in utes)
TA = 25°C
VS = ±15V
VCM = 0V
0
0309-012
Figure 11. Input Offset Voltage Warm-Up Drift
10 100 1k 10k 100k 1M 10M
10k
1k
100
10
SOURCE RE SIST ANCE (Ω)
EFFECTIVE OFF SET VO LT AGE (µV)
T
A
= 25° C
0
0309-013
BALANCED O R UNBALANCED
V
S
= ±15V
V
CM
= 0V
Figure 12. Effective Offset Voltage vs. Source Resistance
100 1k 10k 100k 1M 10M 100M
100
10
1
0.1
SOURCE RES IST ANCE (Ω)
EFFECTIVE OFF SET VO LT AGE (µV/°C)
0
0309-014
BALANCED O R UNBALANCED
V
S
= ±15V
V
CM
= 0V
Figure 13. Effective TCVOS vs. Source Resistance
1k
100
10
1
VOLTAGE NO ISE
CURRENT NO ISE
T
A
= 25° C
V
S
= ±2V TO ±20V
VOLTAGE NOISE DENSITY (nV/ Hz)
CURRENT NO ISE DE NSIT Y (fA/ Hz)
FREQUENCY ( Hz )
1 10 100 1k
00309-015
Figure 14. Voltage Noise Density vs. Frequency
10
1
0.1
0.01
SOURCE RES I S T ANCE ( Ω)
TOTAL NOISE DENSITY (µV/ Hz)
1kHz
10Hz
100 1k 10k 100k 1M 10M
TA = 25°C
VS = ±2V TO ±20V
0
0309-016
Figure 15. Total Noise Density vs. Source Resistance
100
90
10
0%
1s5mV
0246810
TIME (Seconds)
NOI SE VOL TAGE (100mV/DIV )
VS = ±15V
TA = 25°C
00309-017
Figure 16. 0.1 Hz to 10 Hz Noise Voltage
OP497
Rev. E | Page 7 of 16
100
–40 10M
20
–20
1k
0
100
80
40
60
1M100k10k
225
180
135
90
PHASE ( Degrees)
OPEN-LOOP GAIN (dB)
FREQUENCY (Hz )
GAIN
PHASE
V
S
= ±15V
C
L
= 30pF
R
L
= 1MΩ
T
A
= 25°C
0
0309-018
Figure 17. Open-Loop Gain and Phase vs. Frequency
10k
1k
10011
LO AD RE SISTANCE (kΩ)
OPEN-LOOP GAIN (V/mV)
V
S
= ±15V
V
O
= ±10V
020
T
A
= 25°C
T
A
= 125° C
0
0309-019
Figure 18. Open-Loop Gain vs. Load Resistance
DIFFERENTI AL INPUT VOLT AG E (10µV/DI V)
OUTPUT VOLTAGE (V)
–15 –10 –5 0 5 10 15
RL = 2kΩ
VS = ±15V
VCN = ±10V
TA = 25°C
TA = 125°C
0
0309-020
Figure 19. Open-Loop Gain Linearity
160
01M
40
20
101
80
60
100
120
140
100k10k1k100
FREQ UENCY (Hz)
COMM ON-M ODE REJE CTION (dB)
V
S
= ±15V
T
A
= 25°C
0
0309-021
Figure 20. Common-Mode Rejection vs. Frequency
160
0
40
20
80
60
100
120
140
1M101 100k10k1k100
POWER SUP PLY REJECTIO N (dB)
FREQ UENCY (Hz)
0
0309-022
–PSR
+PSR
V
S
= ±15V
T
A
= 25°C
Figure 21. Power Supply Rejection vs. Frequency
35
0100k
15
5
1k
10
100
30
20
25
10k
FREQUENCY (Hz )
OUTPUT SWING (V p-p)
V
S
= ±15V
T
A
= 25°C
A
VCL
= +1
1% THD
R
L
= 10kΩ
0
0309-023
Figure 22. Maximum Output Swing vs. Frequency
OP497
Rev. E | Page 8 of 16
SUPPLY VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
(REFERRED TO SUPPLY VOLTAGES)
+
V
S
–0.5
–1.0
–1.5
1.5
1.0
0.5
–V
S
0±5±10±15±
T
A
= 25°C
20
0
0309-024
Figure 23. Input Common-Mode Voltage Range vs. Supply Voltage
35
010k
15
5
100
10
10
30
20
25
1k
LO AD RES I ST ANCE (Ω)
OUTPUT SWING (V p-p)
VS = ±15V
TA = 25°C
AVCL = +1
1% THD
fO = 1kHz
0
0309-025
Figure 24. Maximum Output Swing vs. Load Resistance
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE SWING (V)
(REFERRED TO SUPPLY VOLTAGES)
+
V
S
–0.5
–1.0
–1.5
1.5
1.0
0.5
–V
S
0±5±10±15±20
T
A
= 25°C
R
L
= 10kΩ
0
0309-026
Figure 25. Output Voltage Swing vs. Supply Voltage
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (PER AMPLIFIER) (µA)
700
2000 ±5 ±10 ±15 ±20
600
500
400
300
NO LOAD
25°C
125°C
0
0309-027
Figure 26. Supply Current (per Amplifier) vs. Supply Voltage
1k
0.001 100k
1
0.01
10
0.1
1
100
10
10k1k100
00309-028
V
S
= ±15V
T
A
= 25°C
A
V
= +1
FREQUENCY (Hz )
IM PE DANCE (Ω)
Figure 27. Closed-Loop Output Impedance vs. Frequency
35
–35 4
–20
–30
1
–25
0
15
–15
20
25
30
3
2
SHORT-CI RCUIT CURRENT (mA)
TIME FROM OUTPUT SHORT (Minutes)
T
A
= 25°C
T
A
= 125°C
T
A
= 25° C
V
S
= ±15V
OUTPUT SHORTED
TO GROUND
T
A
= 125°C
0
0309-029
Figure 28. Short-Circuit Current vs. Time at Various Temperatures
OP497
Rev. E | Page 9 of 16
70
010k
30
10
100
20
10
60
40
50
1k
LOAD CAPACITANCE (pF)
OVERSHOOT (%)
0
0309-030
VS = ±15V
TA = 25°C
AVCL = +1
VOUT = 100mV p-p
Figure 29. Small-Signal Overshoot vs. Load Capacitance
OP497
Rev. E | Page 10 of 16
APPLICATIONS INFORMATION
Extremely low bias current makes the OP497 attractive for use
in sample-and-hold amplifiers, peak detectors, and log amplifiers
that must operate over a wide temperature range. Balancing
input resistances is not necessary with the OP497. High source
resistance, even when unbalanced, only minimally degrades the
offset voltage and TCVOS.
The input pins of the OP497 are protected against large differential
voltage by back-to-back diodes and current-limiting resistors.
Common-mode voltages at the inputs are not restricted and
may vary over the full range of the supply voltages used.
The OP497 requires very little operating headroom about the
supply rails and is specified for operation with supplies as low as
±2 V. Typically, the common-mode range extends to within 1 V
of either rail. When using a 10 kΩ load, the output typically
swings to within 1 V of the rails.
AC PERFORMANCE
The ac characteristics of the OP497 are highly stable over its full
operating temperature range. Figure 30 shows the unity-gain
small signal response. Extremely tolerant of capacitive loading
on the output, the OP497 displays excellent response even with
1000 pF loads (see Figure 31).
10
90
100
0%
20mV 5µs
00309-032
Figure 30. Small Signal Transient Response (CLOAD = 100 pF, AVCL = +1)
10
90
100
0%
20mV 5µs
0
0309-033
Figure 31. Small Signal Transient Response (CLOAD = 1000 pF, AVCL = +1)
10
90
100
0%
2V 50µs
00309-034
Figure 32. Large Signal Transient Response (AVCL = +1)
–IN
+IN
2.5kΩ
V
+
V
OUT
V–
2.5kΩ
00309-031
Figure 33. Simplified Schematic Showing One Amplifier
OP497
Rev. E | Page 11 of 16
GUARDING AND SHIELDING
To maintain the extremely high input impedances of the OP497,
care must be taken in circuit board layout and manufacturing.
Board surfaces must be kept scrupulously clean and free of
moisture. Conformal coating is recommended to provide a
humidity barrier. Even a clean PCB can have 100 pA of leakage
currents between adjacent traces; therefore, use guard rings
around the inputs. Guard traces are operated at a voltage close
to that on the inputs, as shown in Figure 34, so that leakage
currents become minimal. In noninverting applications, connect
the guard ring to the common-mode voltage at the inverting
input. In inverting applications, both inputs remain at ground;
therefore, the guard trace should be grounded. Place guard
traces on both sides of the circuit board.
1/4
OP497
UNI T Y-GAIN F OLL O WE
R
NONINV ERTI NG AMPLI FIE R
INVERTING AMPLIFIER
B
8
A
1
PDIP
BOTTOM VIEW
–
+
–
+
–
+
1/4
OP497
1/4
OP497
00309-035
Figure 34. Guard Ring Layout and Connections
OPEN-LOOP GAIN LINEARITY
The OP497 has both an extremely high gain of 2000 V/mV
typical and constant gain linearity. This enhances the precision
of the OP497 and provides for very high accuracy in high
closed-loop gain applications. Figure 35 illustrates the typical
open-loop gain linearity of the OP497.
OUT PUT VOL T AG E (V)
–15 –10 –5 0 5 10 15
DIFFERENTI AL INPUT VOLT AG E (10µV/DI V)
R
L
= 10kΩ
V
S
= ±15V
V
CM
= 0V
T
A
= 25°C
T
A
= 125° C
0
0309-036
Figure 35. Open-Loop Gain Linearity
OP497
Rev. E | Page 12 of 16
APPLICATIONS CIRCUIT
PRECISION ABSOLUTE VALUE AMPLIFIER
The circuit in Figure 36 is a precision absolute value amplifier
with an input impedance of 30 M. The high gain and low
TCVOS of the OP497 ensure accurate operation with microvolt
input signals. In this circuit, the input always appears as a common-
mode signal to the op amps. The CMR of the OP497 exceeds
120 dB, yielding an error of less than 2 ppm.
+15
V
2
3
4
8
1
6
5
7
0V < VOUT < 10V
D1
1N4148
C1
30pF
D2
1N4148
1/4
OP497
1/4
OP497
–15V
V
IN R2
2kΩ
C3
0.1µF
R3
1kΩ
R1
1kΩ
C2
0.1µF
00309-037
Figure 36. Precision Absolute Value Amplifier
PRECISION CURRENT PUMP
Maximum output current of the precision current pump shown
in Figure 37 is ±10 mA. Voltage compliance is ±10 V with ±15 V
supplies. Output impedance of the current transmitter exceeds
3 M with linearity better than 16 bits.
2
3
1
7
85
6
4
–15V
+15V
–
+
V
IN
1/4
OP497
1/4
OP497
I
OUT
===
R5
V
IN
100Ω
V
IN
10mA/V
R3
10kΩ
R5
10kΩ
R4
10kΩ
R1
10kΩ
R2
10kΩ
I
OUT
±10mA
0
0309-038
Figure 37. Precision Current Pump
PRECISION POSITIVE PEAK DETECTOR
In Figure 38, the CH must be of polystyrene, Teflon®, or
polyethylene to minimize dielectric absorption and leakage.
The droop rate is determined by the size of CH and the bias
current of the OP497.
2
3
17
8
5
6
4
+15V
1N4148
2N930
RESET
1/4
OP497
1/4
OP497
+
+
+
–15V
V
OUT
0.1µF
0.1µF
C
H
V
IN
1kΩ
1kΩ
1kΩ
1kΩ
00309-039
Figure 38. Precision Positive Peak Detector
SIMPLE BRIDGE CONDITIONING AMPLIFIER
Figure 39 shows a simple bridge conditioning amplifier using
the OP497. The transfer function is
R
R
RR
R
VV F
REF
OUT ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
Δ+
=
The REF43 provides an accurate and stable reference voltage for
the bridge. To maintain the highest circuit accuracy, RF should
be 0.1% or better with a low temperature coefficient.
2
3
1
7
8
5
6
4
+5
V
REF43
6
2
4
+5V
RR
R
2.5V
R + ΔR
V
OUT
= V
REF
ΔR
R + ΔRR
1/4
OP497
1/4
OP497
V
REF
R
F
V
OUT
–5V
R
F
()
00309-040
Figure 39. Simple Bridge Conditioning Amplifier Using the OP497
OP497
Rev. E | Page 13 of 16
NONLINEAR CIRCUITS
Due to its low input bias currents, the OP497 is an ideal log
amplifier in nonlinear circuits, such as the squaring amplifier
and square root amplifier circuits shown in Figure 40 and
Figure 41. Using the squaring amplifier circuit in Figure 40
as an example, the analysis begins by writing a voltage loop
equation across Transistors Q1, Q2, Q3, and Q4.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
S4
REF
T4
S3
O
T3
S2
IN
T2
S1
IN
T1 I
I
InV
I
I
IInV
I
I
InV
I
I
InV
All the transistors in the MAT04 are precisely matched and at
the same temperature; therefore, the IS and VT terms cancel,
giving
2InIIN = InIO + InIREF = In (IO × IREF)
Exponentiating both sides of the thick equation lead to
()
REF
IN
OI
I
I
2
=
Op amp A2 forms a current-to-voltage converter which results
in VOUT = R2 × IO. Substituting (VIN/R1) for IIN and the previous
equation for IO yields
2
⎟
⎠
⎞
⎜
⎝
⎛
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=R1
V
I
R2
VIN
REF
OUT
1
2
367
5
C1
100pF
V+
2
3
81
4
V–
6
5
7
I
O
9
8
10
Q1
Q3
Q2
14
12
Q4
13
I
REF
MAT04
1/4
OP497
1/4
OP497
A2
A1
I
IN
V
IN
R1
133kΩ
–15V
R3
50kΩR4
50kΩ
C2
100pF
R2
33kΩ
V
OUT
00309-041
Figure 40. Squaring Amplifier
A similar analysis made for the square root amplifier circuit in
Figure 41 leads to its transfer function
)
)
R1
IV
R2V REFIN
OUT =
In these circuits, IREF is a function of the negative power supply. To
maintain accuracy, the negative supply should be well regulated.
For applications where very high accuracy is required, a voltage
reference can be used to set IREF. An important consideration for
the squaring circuit is that a sufficiently large input voltage can
force the output beyond the operating range of the output op
amp. Resistor R4 can be changed to scale IREF, or R1 and R2 can
be varied to keep the output voltage within the usable range.
1
2
3
67
5
V+
2
3
8
1
4
6
5
7
I
O
9
8
10
Q1
Q3Q2
14
12
Q4
13
MAT04
C2
100pF
1/4
OP497
1/4
OP497
V
OUT
R2
33kΩ
I
REF
I
IN
C1
100pF
–15V
V–
R5
2kΩR3
50kΩR4
50kΩ
V
IN
R1
33kΩ
0
0309-042
Figure 41. Square Root Amplifier
Unadjusted accuracy of the square root circuit is better than
0.1% over an input voltage range of 100 mV to 10 V. For a similar
input voltage range, the accuracy of the squaring circuit is better
than 0.5%.
OP497
Rev. E | Page 14 of 16
OUTLINE DIMENSIONS
COM PLI ANT TO JEDE C S TANDARDS MS-001
CONT ROLLING DIM E NS IONS ARE IN INCHES; M IL L IMETER DIMENS IONS
(IN PARE NTHESES) ARE ROUNDED-OFF I NCH EQUIVALE NT S FOR
REFERENCE ONLY AND ARE NOT AP P ROPRIATE FOR US E IN DES IGN.
CORNER L E ADS MAY BE CONFI GURED AS WHOLE O R HALF LEADS.
070606-A
0.022 ( 0 .56)
0.018 ( 0 .46)
0.014 ( 0 .36)
0.150 (3.81)
0.130 (3.30)
0.110 (2. 79)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
14
17
8
0.100 ( 2 .54)
BSC
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 ( 0 .38)
GAUGE
PLANE
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 ( 0 .13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.195 (4.95)
0.130 (3.30)
0.115 (2. 92)
Figure 42. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
CONT ROLLING DIMENSI ONS ARE IN MILLIMET ERS ; INCH DIMENSI ONS
(IN PARE NTHESE S ) ARE ROUNDED-OFF MIL LI METE R EQUIVAL E NT S FO R
REFE RE NCE ONLY AND ARE NOT APPROPRIATE FOR US E IN DESIG N.
COMP LI ANT TO JEDE C STANDARDS MS- 013-AA
032707-B
10.50 (0.4134 )
10.10 (0.3976 )
0.30 ( 0.0118)
0.10 ( 0.0039)
2.65 ( 0.1043)
2.35 ( 0.0925)
10.65 ( 0.4193)
10.00 ( 0.3937)
7.60 ( 0 .2992)
7.40 ( 0 .2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 ( 0.0079)
0.51 ( 0.0201)
0.31 ( 0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 ( 0.0500)
BSC
Figure 43. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
OP497
Rev. E | Page 15 of 16
ORDERING GUIDE
Model Temperature Range Package Description Package Option
OP497FP −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
OP497FPZ1 −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
OP497GP −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
OP497GPZ1 −40°C to +85°C 14-Lead Plastic Dual In-Line Package [PDIP] N-14
OP497FS −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
OP497FS-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
OP497FSZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
OP497FSZ-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
OP497GS −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W RW-16
OP497GS-REEL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
OP497GSZ1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
OP497GSZ-REEL1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_W] RW-16
1 Z = RoHS Compliant Part.
OP497
Rev. E | Page 16 of 16
NOTES
©1991–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00309-0-2/09(E)