2K x 8 Reprogrammable Registered PROM
CY7C245A
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-04007 Rev. *E Revised August 17, 2006
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
— 330 mW (commercial) for -25 ns
— 660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronou s register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
•5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM flo ating-gate technology
and byte-wide intelligent prog ramming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeate dly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A8
A9
INIT
CP
O7
O6
O4
O5
O3
PROGRAMMABLE
ARRAY MULTIPLEXER
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CP
CP
E/E S
E/ES
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12 19
A5
V
CC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3A10
NC
NC
NC
INIT
E/ES
O7
O6
A2
A1CP
O2
A8
INIT
INITIALIZE WORD
PROGRAMMABLE
A9
PROGRAMMABLE
MULTIPLEXER
DQ
C
A10
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A7
COLUMN
ADDRESS
ROW
ADDRESS
DIP Top View
LCC/PLCC (Opaque only) Top View
Selection Guide
7C245A-15 7C245A-18 7C245A-25 7C245A-35 Unit
Minimum Address Set-up Time 15 18 25 35 ns
Maximum Clock to Output 10 12 12 15 ns
Maximum Operating Current S tandard Commercial 120 120 90 90 mA
Military 120 120 120 mA
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CY7C245A
Document #: 38-04007 Rev. *E Page 2 of 13
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Addi tional flexibility is
provided with a programmable synchronous (ES) or
asynchronous (E) output enable and asynchronous initial-
ization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the
synchronous en able (E S) has be en prog ra mmed, the regi ste r
will be in the set condition causi ng the outputs (O0–O7) to be
in the OFF or high-impedance state. If the asynchronous
enable (E) is being used, the outputs will come up in the OFF
or high-impedance state only if the enable (E) input is at a
HIGH logic level. Data is read by applying the memory location
to the address inputs (A0–A10) and a logic LOW to the enable
input. The stored data is accessed and loaded into the master
flip-flops of the data register during the address set-up time. At
the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs
(O0–O7).
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enabl e (ES) is bei ng used, the outpu ts will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin i s switched to a
logic LOW, the subse quent positive clock ed ge will return the
output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
low-to-high transition of the clo ck. This unique feature allows
the CY7C245A decoders and sen se amplifiers to access the
next location while previously addressed data remains stable
on the outputs.
System timing is simplified in tha t the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facili tate implementation of other sophis-
ticated functions such as a built-in “jump start” address. When
activated, the initialize control inp ut causes the contents of a
user-programmed 2049th 8-bit word to be loaded into the
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are progra mmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clo ck (CP). The initialize data will app ear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
Erasure Characteristics
W avelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for era sure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 35 minutes. The 7C245A need s
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the PROM is exposed to high-intensity
UV light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Bit Map Data
Programmer Address RAM Data
Decimal Hex Contents
00 Data
.
.
.
.
.
.
.
.
.
2047 7FF Data
2048 800 Init Byte
2049 801 Control Byte
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
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CY7C245A
Document #: 38-04007 Rev. *E Page 3 of 13
Figure 1. Programming Pinouts
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Table 1. Mode Selection
Mode Read or Output Disable Pin Function[1]
A10–A4A3A2–A1A0CP E, ESINIT O7–O0
Other A10–A4A3A2–A1A0PGM VFY VPP D7–D0
Read A10–A4A3A2–A1A0VIL/VIH VIL VIH O7–O0
Output Disable A10–A4A3A2–A1A0XV
IH VIH High Z
Initialize A10–A4A3A2–A1A0XV
IL VIL Init. Byte
Program A10–A4A3A2–A1A0VILP VIHP VPP D7–D0
Program Verify A10–A4A3A2–A1A0VIHP VILP VPP O7–O0
Program Inhibit A10–A4A3A2–A1A0VIHP VIHP VPP High Z
Intelligent Program A10–A4A3A2–A1A0VILP VIHP VPP D7–D0
Program Synchronous Enable A10–A4VIHP A2–A1VPP VILP VIHP VPP High Z
Program Initializati on Byte A10–A4VILP A2–A1VPP VILP VIHP VPP D7–D0
Blank Check Zeros A10–A4A3A2–A1A0VIHP VILP VPP Zeros
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
D7
D6
D4
D5
D3
15
A9
A10
VPP
VFY
PGM
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0
A4
A3
A8
NC
NC
D7
D6
A2
A1
D2
A10
VPP
VFY
PGM
NC
A9
DIP Top View LCC/PLCC (Opaque Only) Top View
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
SMD Cross Reference
SMD Number Suffix Cypress Number
5962-88735 033X CY7C245A-25LMB
5962-88735 04LX CY7C245A-25DMB
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
Note
1. X = “don’t care” but not to exceed VCC + 5%.
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CY7C245A
Document #: 38-04007 Rev. *E Page 4 of 13
Maximum Ratings[2]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0. 5V to +7. 0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input V oltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
UV Erasure............... ... ... .............. .. ..............7258 Wsec/cm2
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[3] −55°C to +125°C 5V ±10%
Industrial –40°C to +85°C 5V ±10%
Electrical Characteristics Over the Operating Range[4,5]
Parameter Description Test Conditions 7C245A-15 7C245A-18 7C245A-25
7C245A-35
7C245A-45 Unit
Min. Max. Min. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA
VIN = VIH or VIL 2.4 2.4 2.4 V
VOL Output LOW V oltage VCC = Min., IOL = 16 mA
VIN = VIH or VIL 0.4 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical
HIGH Voltage for All Inputs 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Input LOW Level Guaranteed Input Log ical
LOW Voltage for All Inputs 0.8 0.8 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 −10 +10 −10 +10 µA
VCD Input Clamp Diode Voltage Note 5
IOZ Output Leakage Current GND < V O < VCC Output
Disabled[6] −10 +10 −10 +10 −10 +10 µA
IOS Output Short Circuit Current VCC = Max., VOUT = 0.0V[7] −20 −90 −20 −90 −20 −90 mA
ICC Power Supply Current VCC = Max.,
IOUT = 0 mA Com’l 120 120 90 mA
Mil 120 120
VPP Programming Supply Voltage 12 13 12 13 12 13 V
IPP Programming Supply Current 50 50 50 mA
VIHP Input HIGH Programming V oltage 3.0 3.0 3.0 V
VILP Input LOW Programming Voltage 0.4 0.4 0.4 V
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Notes
2. The voltage on any input or I/ O pin cannot exceed the power pin during power-u p.
3. TA is the “instant on” case temp erature.
4. See page 3 of this data sheet for Group A subgroup testin g information.
5. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
6. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
7. For test purposes, not more than one output at a time should be shorted. Short circuit te st duration should not exceed 30 seconds.
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CY7C245A
Document #: 38-04007 Rev. *E Page 5 of 13
Notes
8. Applies only when the synchronous (ES) function is used.
9. Applies only when the asynch ronous (E) function is used.
AC Test Loads and Waveforms[4, 5]
Switching Characteristics Over Operating Range[4, 5]
Parameter Description 7C245A-15 7C245A-18 7C245A-35 7C245A-25 7C245A-35 Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
tSA Address Set-Up to Clock HIGH 15 18 25 35 45 ns
tHA Address Hold from Clock HIGH 0 0 0 0 0 ns
tCO Clock HIGH to Valid Output 10 12 12 15 25 ns
tPWC Clock Pulse Width 10 12 15 20 20 ns
tSES ES Set-Up to Clock HIGH 10 10 12 15 15 ns
tHES ES Hold from Clock HIGH 5 5 5 5 5 ns
tDI Delay from INIT to Va l i d O u t p u t 15 20 20 20 35 ns
tRI INIT Recovery to Clock HIGH 10 12 15 20 20 ns
tPWI INIT Pulse Width 10 12 15 20 25 ns
tCOS Valid Output from Clock HIGH[8] 15 15 15 20 30 ns
tHZC Inactive Output from Clock
HIGH[8] 15 15 15 20 30 ns
tDOE Valid Output from E LOW[9] 12 15 15 20 30 ns
tHZE Inactive Output from E HI GH[9] 15 15 15 20 30 ns
3.0V
5V
OUTPUT
R1 250Ω
R2
167Ω
50 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10%
90%
10%
5ns 5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(b) HighZ Load
OUTPUT 2.0V
Equivalent to: TH ÉVENINEQUIVALENT
100Ω
R1 250Ω
(a) Normal Load
R2
167Ω
ALL INPUT PULSES
≤≤
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CY7C245A
Document #: 38-04007 Rev. *E Page 7 of 13
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −
55
25 125
1.2
1.1
1.6
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK-TO-OUTPUT TIME
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY C URRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (
°
C)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. VCC
0.6
1.2
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
AMBIENT TEMPERATURE (°C)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I CC
NORMALIZED I
CC
VCC =5.0V
TA=25°C
TA=25
°
C
0.6
0.6
1.02
1.00
0.98
0.96
0.94
0.92
025 5075
CLOCK PERIOD (ns)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
100 0.0 1000
TA=25°C
VCC =4.5V
TA=25
°
C
f= f
MAX
25
0.88
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
4.0
1.4
1.2
1.0
0.8
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK-TO-OUTPUT TIME
0.4
SUPPLY VOLTAGE (V)
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
TA=25°C
1.0
0.8
0.6
NORMALIZED I
CC
0.90
VCC =5.5V
TA=25°C
Ordering Information
Speed (ns) ICC
(mA) Ordering
Code Package
Type Package Type Operating
Range
tSA tCO
15 10 120 CY7C245A-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
15 10 120 CY7C245A-15JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
18 12 120 CY7C245A-18QMB Q64 28-Pin Windowed Leadless Chip Carrier Military
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CY7C245A
Document #: 38-04007 Rev. *E Page 8 of 13
f
18 12 120 CY7C245A-18WMB W14 24-Lead (300-Mil) Windowed CerDIP Military
25 15 60 CY7C245A-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
25 15 90 CY7C245A-25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
35 20 60 CY7C245A-35WC W14 24-Lead (300-Mil) Windowed CerDIP Commercial
120 CY7C245A-35QMB Q64 28-Pin Win dowed Leadless Chip Carrier Military
Ordering Information (continued)
Speed (ns) ICC
(mA) Ordering
Code Package
Type Package Type Operating
Range
tSA tCO
Package Diagrams
Figure 2. 24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
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CY7C245A
Document #: 38-04007 Rev. *E Page 11 of 13
Figure 6. 24-Lead (300-Mil) SOIC S13
Package Diagrams (continued)
PIN 1 ID
SEATING PLANE
0.597[15.163]
0.615[15.621]
112
13 24
*
*
*
0.291[7.391]
0.300[7.620]
0.394[10.007]
0.419[10.642]
0.050[1.270]
TYP.
0.092[2.336]
0.105[2.667]
0.004[0.101]
0.0118[0.299]
0.0091[0.231]
0.0125[0.317]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
0
.026[0.66
0
]
0.032[0.812]
0.004[0.101]
PART #
S24.3 STANDARD PKG.
SZ24.3 LEAD FREE PKG.
MIN.
MAX.
NOTE :
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
3. DIMENSIONS IN INCHES
4. PACKAGE WEIGHT 0.65gms
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
51-85025-*C
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CY7C245A
Document #: 38-04007 Rev. *E Page 12 of 13
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic on duct or Cor po rati on assu me s no resp onsi b i lity f or th e u s e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significan t injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 7. 24-Lead (300-Mil) Windowed CerDIP W14
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
51-80086-**
MIL-STD-1835 D-9 Config. A
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CY7C245A
Document #: 38-04007 Rev. *E Page 13 of 13
Document History Page
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 113863 3/6/02 DSG Changed from Spec number: 38-00074 to 38-04007
*A 118894 10/09/02 GBI Updated ordering information
*B 122248 12/27/02 RBI Added power-up requirements to Operating Conditions information
*C 130688 10/30/03 LSY Added CY7C245A-15JI part number
*D 130942 11/10/03 KKV Minor change: soft copy became corrup ted after sign off and before Tech
Pubs. Replaced with correct copy
*E 499542 See ECN PCI Updated ordering information
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