ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 CLASS V, 12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS5463-SP FEATURES 1 * * * * * * * * * * * 500-MSPS Sample Rate Available With Radiation Hardness Specified (RHA) - Total Ionizing Dose 100 krad(Si), ELDRS Free 100 krad(Si) 12-Bit Resolution, 10-Bits Effective Number of Bits (ENOB) SNR > 64.5 dBFS at 450 MHz and 500 MSPS SFDR > 64.0 dBc at 450 MHz and 500 MSPS 2.2-VPP Differential Input Voltage LVDS-Compatible Outputs Total Power Dissipation: 2.2 W Offset Binary Output Format Output Data Transitions on the Rising and Falling Edges of a Half-Rate Output Clock On-Chip Analog Buffer, Track and Hold, and Reference Circuit * * Available in a 84-Pin Ceramic Nonconductive Tie-Bar Package (HFG). Military Temperature Range (-55C to 125C Tcase) APPLICATIONS * * * * * * Test and Measurement Instrumentation Software-Defined Radio Data Acquisition Power Amplifier Linearization Communication Instrumentation Radar DESCRIPTION/ORDERING INFORMATION The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs from the 3.3-V supply. The ADS5463 input buffer isolates the internal switching of the onboard track and hold (T and H) from disturbing the signal source. An internal reference generator is also provided to simplify the system design further. The ADS5463 has outstanding low noise and linearity over input frequency. The ADS5463 is available in a 84-pin ceramic nonconductive tie-bar package (HFG). The ADS5463 is built on state-of-the-art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full military temperature range (-55C to 125C Tcase). VIN VIN A1 TH1 + TH2 S + TH3 A2 ADC1 A3 ADC3 - - VREF S DAC1 ADC2 DAC2 Reference 5 5 5 Digital Error Correction CLK CLK Timing OVR OVR DRY DRY D[11:0] B0061-03 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGING/ORDERING INFORMATION (1) TEMPERATURE PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING 5962-0720801VXC 5962-0720801VXC ADS5463MHFG-V 5962R0720802VXC 5962R0720802VXC ADS5463MHFG-RHA ADS5463HFGMPR ADS5463HFG/EM (3) EVAL ONLY -55C to 125C Tcase 84 / HFG 25C (1) (2) (3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. No Burn-In, etc.) and are tested to a temperature rating of 25C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance over the full MIL specified temperature range of -55C to 125C or operating life. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Supply voltage AVDD5 to GND 6 AVDD3 to GND 5 DVDD3 to GND 5 AC signal AIN, AIN to GND (2) AIN to AIN (2) Voltage difference between pin and ground Voltage difference between these pins 0.4 to 4.4 DC signal, TJ = 125C 1.0 to 3.8 AC signal -5.2 to 5.2 DC signal, TJ = 125C AC signal CLK, CLK to GND (2) CLK to CLK (2) Voltage difference between pin and ground Voltage difference between these pins DC signal, TJ = 105C DC signal, TJ = 105C -3.3 to 3.3 TJ Maximum junction temperature TSTG Storage temperature range (2) 2 0.1 to 4.7 1.1 to 3.7 Characterized case operating temperature range V -2.8 to 2.8 -3.3 to 3.3 TC V -0.3 to (AVDD5 + 0.3) AC signal DC signal, TJ = 125C (1) -4 to 4 DC signal, TJ = 125C Data output to GND (2) LVDS digital outputs V -0.3 to (AVDD5 + 0.3) DC signal, TJ = 105C DC signal, TJ = 105C UNIT V V -2.6 to 2.6 -0.3 to (DVDD3 + 0.3) V -55 to 125 C 150 C -65 to 150 C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Valid when supplies are within recommended operating range. Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 Recommended Operating Conditions MIN TYP MAX UNIT Supplies AVDD5 Analog supply voltage 4.75 5 5.25 V AVDD3 Analog supply voltage 3 3.3 3.6 V DVDD3 Output driver supply voltage 3 3.3 3.6 V Analog Input VCM Differential input range 2.2 Vpp Input common mode 2.4 V 10 pF Digital Output Maximum differential output load Clock Input CLK input sample rate (sine wave) 500 Clock amplitude, differential sine wave Clock duty cycle Tc Operating case temperature MSPS 3 Vpp 50 % -55 125 C Electrical Characteristics Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS ADS5463-RHA MIN Resolution TYP ADS5463-SP MAX MIN TYP MAX UNIT 12 12 Bits 2.2 2.2 VPP Analog Inputs Differential input range Input resistance (dc) Each input to VCM 500 500 Input capacitance Each input to ground 2.5 2.5 pF Analog input bandwidth 1000 2000 2.38 2.4 1000 2000 2.38 2.4 MHz Internal Reference Voltage VREF Reference voltage Full Temp Range 2.42 2.42 V Dynamic Accuracy No missing codes Assured Assured DNL Differential linearity error fIN = 210 MHz Full Temp Range -0.98 0.95 1.2 -0.98 0.95 1.2 LSB INL Integral linearity error fIN = 210 MHz Full Temp Range -3.5 1.5 3.5 -2.9 1.5 2.9 LSB Full Temp Range -0.5 0.5 -0.5 Offset error Offset temperature coefficient Gain error Gain temperature coefficient 0.0009 Full Temp Range -5 5 -0.02 0.5 0.0009 -5 5 -0.02 %FS %FS/C %FS %FS/C Power Supply Copyright (c) 2008-2012, Texas Instruments Incorporated 3 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com Electrical Characteristics (continued) Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS ADS5463-RHA MIN ADS5463-SP MAX UNIT IAVDD5 5 V analog supply current 345 335 mA IAVDD3 3.3 V analog supply current 148 140 mA 88 88 mA 2.450 2.425 W VIN = full scale, IDVDD3 3.3 V digital fIN = 300 MHz, supply FS = 500 MSPS current(includes LVDS) Power dissipation 4 Full Temp Range TYP MAX MIN TYP Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 Electrical Characteristics Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS ADS5463-RHA MIN TYP ADS5463-SP MAX MIN TYP MAX UNIT Dynamic AC Characteristics fIN = 10 MHz 65.4 65.4 fIN = 70 MHz 65.3 65.3 TC = 25C fIN = 100 MHz TC = TC,MAX 65.2 60.5 63.5 TC = 25C TC = TC,MAX 65.0 60.0 Signal-to-noise ratio TC = TC,MAX 64.9 58.0 62.7 64.9 61.9 fIN = 450 MHz 64.5 64.5 fIN = 650 MHz 63.7 63.7 fIN = 900 MHz 62.8 62.8 fIN = 1.0 GHz 62.2 62.2 fIN = 10 MHz 63.5 63.5 fIN = 70 MHz 64.2 64.2 TC = 25C fIN = 100 MHz TC = TC,MAX 65.0 57.9 64.0 55.2 TC = TC,MAX 64.0 56.9 TC = 25C fIN = 300 MHz 55.2 56.6 TC = TC,MIN Spurious free dynamic range 65.0 58.6 TC = 25C TC = TC,MAX 57.9 58.8 TC = TC,MIN fIN = 210 MHz 64.0 51.2 54.1 64.0 dBc 51.3 TC = TC,MIN 56.2 fIN = 450 MHz 64.0 64.0 fIN = 650 MHz 61.6 61.6 fIN = 900 MHz 54.5 54.5 fIN = 1.0 GHz 51.6 51.6 Copyright (c) 2008-2012, Texas Instruments Incorporated dBFS 61.3 TC = TC,MIN SFDR 65.0 63.2 TC = 25C fIN = 300 MHz 63.6 62.4 TC = TC,MIN SNR 65.2 62.7 TC = TC,MIN fIN = 210 MHz 64.1 5 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com Electrical Characteristics (continued) Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS ADS5463-RHA MIN TYP 63.5 fIN = 70 MHz 64.2 64.2 TC = TC,MAX 65.4 57.9 TC = TC,MAX 64.4 55.2 TC = TC,MAX 55.2 64.4 56.9 TC = 25C fIN = 300 MHz 65.4 56.6 TC = TC,MIN Second harmonic 64.3 51.2 54.1 64.3 56.2 fIN = 450 MHz 64.4 64.4 fIN = 650 MHz 67.1 67.1 fIN = 900 MHz 62.9 62.9 fIN = 1.0 GHz 58.6 58.6 fIN = 10 MHz 104 104 fIN = 70 MHz 104 104 TC = 25C TC = TC,MAX 87.0 64.0 85.0 59.0 TC = TC,MAX 85.0 64.1 TC = 25C fIN = 300 MHz 66.7 65.3 TC = TC,MIN Third harmonic 87.0 65.6 TC = 25C TC = TC,MAX 69.0 68.5 TC = TC,MIN fIN = 210 MHz dBc 51.3 TC = TC,MIN fIN = 100 MHz UNIT 58.6 TC = 25C fIN = 210 MHz 57.9 MAX 58.8 TC = TC,MIN 76.0 61.9 70.1 76.0 dBc 61.9 TC = TC,MIN 6 TYP 63.5 TC = 25C HD3 MIN fIN = 10 MHz fIN = 100 MHz HD2 ADS5463-SP MAX 64.8 fIN = 450 MHz 73.3 73.3 fIN = 650 MHz 61.6 61.6 fIN = 900 MHz 54.5 54.5 fIN = 1.0 GHz 51.6 51.6 Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 Electrical Characteristics Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS ADS5463-RHA MIN TYP ADS5463-SP MAX MIN TYP MAX UNIT Dynamic AC Characteristics (continued) fIN = 10 MHz 61.9 61.9 fIN = 70 MHz 62.2 62.2 TC = 25C fIN = 100 MHz TC = TC,MAX 62.0 55.9 58.4 TC = 25C SINAD TC = TC,MAX 62.0 53.8 TC = TC,MAX 61.9 50.2 54.9 61.9 56.1 fIN = 450 MHz 61.6 61.6 fIN = 650 MHz 59.4 59.4 fIN = 900 MHz 54.3 54.3 fIN = 1.0 GHz 51.4 51.4 fIN = 10 MHz 83.1 83.1 fIN = 70 MHz 80.2 80.2 TC = 25C fIN = 100 MHz TC = TC,MAX 81.8 68.0 77.5 62.0 77.5 66.5 TC = 25C TC = TC,MAX 70.6 67.1 TC = TC,MIN fIN = 300 MHz 81.8 72.6 TC = 25C TC = TC,MAX 72.2 70.6 TC = TC,MIN fIN = 210 MHz 78.2 62.0 69.3 78.2 dBc 66.3 TC = TC,MIN 66.3 fIN = 450 MHz 80.6 80.6 fIN = 650 MHz 80.0 80.0 fIN = 900 MHz 79.4 79.4 fIN = 1.0 GHz 77.6 77.6 Copyright (c) 2008-2012, Texas Instruments Incorporated dBc 52.2 TC = TC,MIN Worst harmonic/spur (other than HD2 and HD3) 62.0 56.7 TC = 25C fIN = 300 MHz 55.8 56.2 TC = TC,MIN Signal-to-noise and distortion 62.0 58.0 TC = TC,MIN fIN = 210 MHz 58.0 7 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com Electrical Characteristics (continued) Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, -1 dBFS differential input, and 3 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS ADS5463-RHA MIN TYP ADS5463-SP MAX 63.5 63.5 fIN = 70 MHz 64 64 TC = 25C TC = TC,MAX 65.2 57.8 57.8 TC = TC,MAX 64.1 55.0 55.0 TC = TC,MAX 63.8 53.9 51.0 55.6 fIN = 450 MHz 63.7 63.7 fIN = 650 MHz 60.5 60.5 fIN = 900 MHz 53.9 53.9 fIN = 1.0 GHz 50.8 50.8 Effective number of bits TC = 25C fIN = 100 MHz TC = TC,MAX 10.1 9.3 9.0 9.4 TC = 25C TC = TC,MAX 10.0 8.9 8.65 Bits 9.1 TC = 25C TC = TC,MAX 10.0 9.0 TC = TC,MIN fIN = 300 MHz 10.1 9.3 TC = TC,MIN fIN = 210 MHz dBc 63.8 51.0 TC = TC,MIN 9.9 8.8 8.05 9.9 8.3 TC = TC,MIN RMS idle-channel noise 64.1 56.2 TC = 25C fIN = 300 MHz 65.2 55.9 TC = TC,MIN Total harmonic distortion UNIT 58.1 TC = 25C fIN = 210 MHz MAX 58.3 TC = TC,MIN ENOB TYP fIN = 10 MHz fIN = 100 MHz THD MIN 9.0 Inputs tied to common-mode 0.7 0.7 LSB LVDS Digital Outputs VOD Differential output voltage VOC Common mode output voltage 8 247 1.125 350 454 247 1.375 1.125 350 454 1.375 mV V Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 Sample N-1 N+4 N+2 ta N N+1 N+3 tCLKH N+5 tCLKL CLK CLK Latency = 3.5 Clock Cycles tDRY DRY DRY tDATA D[11:0], OVR N-1 N N+1 D[11:0], OVR T0158-01 Figure 1. Timing Diagram Copyright (c) 2008-2012, Texas Instruments Incorporated 9 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com Timing Characteristics Typical values at TC = 25C, full temperature range is TC,MIN = -55C to TC,MAX = 125C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock (unless otherwise noted) PARAMETER (1) ta TEST CONDITIONS MIN TYP MAX UNIT Aperture delay 200 ps Aperture jitter, rms 160 fs Latency 3.5 cycles tCLK Clock period 2 tCLKH Clock pulse duration, high 1 tCLKL Clock pulse duration, low tDRY CLK to DRY delay (2) Zero crossing 750 1500 2500 ps tDATA CLK to DATA/OVR delay (2) Zero crossing 650 1150 1750 ps tSKEW DATA to DRY skew tDATA-tDRY -1250 -400 700 ps tRISE DRY/DATA/OVR rise time 500 ps tFALL DRY/DATA/OVR fall time 500 ps (1) (2) 10 50 ns ns 1 ns Timing parameters are assured by design or characterization, but not production tested. <10pF load on each output pin. DRY, DATA and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation delay. Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 PIN CONFIGURATION GND D4 D5 D4 D5 GND D6 DVDD3 D7 D6 D8 D7 D9 D8 D10 D9 D11 D10 DRY D11 DRY HFG PACKAGE (TOP VIEW) 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 D3 DVDD3 2 62 D3 GND 3 61 D2 AVDD5 4 60 D2 NC 5 59 D1 NC 6 58 D1 VREF 7 57 D0 GND 8 56 D0 AVDD5 9 55 GND GND 10 54 DVDD3 CLK 11 53 NC CLK 12 52 NC GND 13 51 NC AVDD5 14 50 NC AVDD5 15 49 NC GND 16 48 NC AIN 17 47 NC AIN 18 46 NC GND 19 45 OVR AVDD5 20 44 OVR 43 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 GND Copyright (c) 2008-2012, Texas Instruments Incorporated AVDD3 GND AVDD3 GND AVDD3 GND RESERVED GND AVDD5 GND RESERVED GND AVDD5 GND AVDD5 GND AVDD5 GND GND AVDD5 GND ADS5463 GND GND 11 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION AIN 17 Differential input signal (positive) AIN 18 Differential input signal (negative) AVDD5 4, 9, 14, 15, 20, 23, 25, 27, 29, 33 AVDD3 37, 39, 41 Analog power supply (3.3 V) (Suggestion for 250 MSPS: leave option to connect to 5 V for ADS5440/4 compatibility) 2, 54, 70 Output driver power supply (3.3 V) DVDD3 Analog power supply (5 V) GND 1, 3, 8, 10, 13, 16, 19, 21, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 43, 55, 64, 69 CLK 11 Differential input clock (positive). Conversion initiated on rising edge. 12 Differential input clock (negative) CLK Ground D0, D0 56, 57 LVDS digital output pair, least-significant bit (LSB) D1-D3, D1-D3 58-63 LVDS digital output pair D4-D5, D4-D5 65-68 LVDS digital output pairs D6-D10, D6-D10 71-80 LVDS digital output pairs D11, D11 81, 82 LVDS digital output pair, most-significant bit (MSB) DRY, DRY 83, 84 Data ready LVDS output pair 5-6, 46-53 No connect (5 and 6 should be left floating, 46-53 are possible future bit additions for this pinout and therefore can be connected to a digital bus or left floating) OVR, OVR 44, 45 Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. RESERVED 31, 35 Reserved for possible future control features NC VREF 7 Reference voltage Thermal Characteristics (1) TYP UNIT RJA Junction-to-free-air thermal resistance PARAMETER Junction-to-case thermal resistance TEST CONDITIONS 21.81 C/W RJC Junction-to-case thermal resistance MIL-STD-883 Test Method 1012 0.849 C/W (1) This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package. To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI typically recommends an 11,9 mm2 board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device within recommended operating conditions. This pad must be electrically at ground potential. 12 Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 Years in Estimated Life www.ti.com Electromigration Fail Mode Continuous Tj - C Figure 2. ADS5463 Estimated Life at Elevated Temperature Electromigration Fail Mode Copyright (c) 2008-2012, Texas Instruments Incorporated 13 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS Typical plots at TA = 25C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock, (unless otherwise noted) 14 AC PERFORMANCE vs INPUT AMPLITUDE (100 MHz Input Signal) AC PERFORMANCE vs INPUT AMPLITUDE (300 MHz Input Signal) Figure 3. Figure 4. SFDR vs CLOCK LEVEL SNR vs CLOCK LEVEL Figure 5. Figure 6. Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock, (unless otherwise noted) SFDR vs AVDD5 ACROSS TEMPERATURE SNR vs AVDD5 ACROSS TEMPERATURE Figure 7. Figure 8. SFDR vs AVDD3 ACROSS TEMPERATURE SNR vs AVDD3 ACROSS TEMPERATURE Figure 9. Figure 10. Copyright (c) 2008-2012, Texas Instruments Incorporated 15 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical plots at TA = 25C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock, (unless otherwise noted) SFDR vs DVDD3 ACROSS TEMPERATURE SNR vs DVDD3 ACROSS TEMPERATURE Figure 11. Figure 12. SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY Figure 13. Figure 14. APPLICATION INFORMATION Theory of Operation The ADS5463 is a 12-bit, 500-MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion process is initiated by the rising edge of the external input clock. The differential input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in offset binary format. Input Configuration The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching. The input common mode is set internally through a 500- resistor connected from 2.4 V to each of the inputs. This results in a differential input impedance of 1 k. 16 Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 For a full-scale differential input, each of the differential lines of the input signal (pins 17 and 18) swings symmetrically between 2.4 V + 0.55 V and 2.4 V - 0.55 V. This means that each input has a maximum signal swing of 1.1 Vpp for a total differential input signal swing of 2.2 Vpp. The maximum swing is determined by the internal reference voltage generator, eliminating the need for any external circuitry for this purpose. The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in Figure 15 shows one possible configuration using an RF transformer with termination either on the primary or on the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back transformers, which also demonstrate good performance. If voltage gain is required, a step-up transformer can be used. Besides the transformer configurations, Texas Instruments offers a wide selection of single-ended operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas Instruments' THS9001, also can be used for high-input-frequency applications. For large voltage gains at intermediate-frequencies in the 50-MHz - 500-MHz range, the configuration shown in Figure 16 can be used. The component values can be tuned for different intermediate frequencies. The example shown is located on the evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data sheet (SLOS426). Z0 50 W R0 50 W AIN R 200 W AC Signal Source ADS5463M AIN Mini-Circuits JTX-4-10T S0176-03 Figure 15. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer 1000 pF VIN 1000 pF AIN THS9001 50 W 18 mH 39 pF ADS5463M 50 W VIN 1000 pF 0.1 mF AIN THS9001 1000 pF S0177-03 Figure 16. Using the THS9001 IF Amplifier With the ADS5463 Copyright (c) 2008-2012, Texas Instruments Incorporated 17 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 From 50 W Source VIN www.ti.com 348 W 100 W +5V 78.9 W 49.9 W 0.22 mF 100 W AIN THS4509 ADS5463M 49.9 W 18 pF AIN VREF CM 49.9 W 0.22 mF 78.9 W 49.9 W 0.22 mF 0.1 mF 0.1 mF 348 W S0193-02 Figure 17. Using the THS4509 With the ADS5463 For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like the THS4509 (see Figure 17) is a good solution, as it minimizes board space and reduces the number of components. In this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to differential, and sets the proper input common-mode voltage to the ADS5463. The 50- resistors and 18-pF capacitor between the THS4509 outputs and ADS5463 inputs (along with the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (-3 dB). Input termination is accomplished via the 78.9- resistor and 0.22-F capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-F capacitor and 49.9- resistor are inserted to ground across the 78.9- resistor and 0.22-F capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348- feedback resistor. See the THS4509 data sheet for further component values to set proper 50- termination for other common gains. Because the ADS5463 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a single power supply input with V S+ = 5 V and V S- = 0 V (ground). This maintains maximum headroom on the internal transistors of the THS4509. Clock Inputs The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. In low-input-frequency applications, where jitter may not be a big concern, the use of a single-ended clock (see Figure 18) could save some cost and board space without any trade-off in performance. When clocked with this configuration, it is best to connect CLK to ground with a 0.01 F capacitor, while CLK is ac-coupled with a 0.01-F capacitor to the clock source, as shown in Figure 18. Square Wave or Sine Wave CLK 0.01 mF ADS5463M CLK 0.01 mF S0168-05 Figure 18. Single-Ended Clock 18 Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com SGLS378D - MARCH 2008 - REVISED AUGUST 2012 0.1 mF Clock Source CLK ADS5463M CLK S0194-02 Figure 19. Differential Clock For jitter-sensitive applications, the use of a differential clock has advantages (as with any other ADC) at the system level. The differential clock allows for common-mode noise rejection at the PCB level. With a differential clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications because the board clock jitter is superior. A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise on jitter. Figure 19 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details. The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-k resistors. It is recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking, the ADS5463 features good tolerance to clock common-mode variation. Additionally, the internal ADC core uses both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided. Digital Outputs The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal (DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits. The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs with too much capacitance, which shortens the data-valid timing window. The values given for timing were obtained with a measured 14-pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential parasitic capacitance). Power Supplies The ADS5463 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5 and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched supplies tend to generate more noise components that can be coupled to the ADS5463. The user may be able to supply power to the device with a less-than-ideal supply and still achieve good performance. It is not possible to make a single recommendation for every type of supply and level of decoupling for all systems. The power consumption of the ADS5463 does not change substantially over clock rate or input frequency as a result of the architecture and process. Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up sequence is recommended. When there is a delay in power up between these two supplies, the one that lags could have current sinking through an internal diode before it powers up. The sink current can be large or small depending on the impedance of the external supply and could damage the device or affect the supply source. The best power up sequence is one of the following options (regardless of when AVDD5 powers up): * Power up both AVDD3 and DVDD3 at the same time (best scenario), OR * Keep the voltage difference less than 0.8 V between AVDD3 and DVDD3 during the power up (0.8 V is not a hard specification - a smaller delta between supplies is safer). If the above sequences are not practical then the sink current from the supply needs to be controlled or protection added externally. The max transient current (on the order of msec) for the DVDD3 or AVDD3 pin is 500 mA to avoid potential damage to the device or reduce its lifetime. Copyright (c) 2008-2012, Texas Instruments Incorporated 19 ADS5463-SP SGLS378D - MARCH 2008 - REVISED AUGUST 2012 www.ti.com The values for the analog and clock inputs given in the Absolute Maximum Ratings are valid when the supplies are on. When the power supplies are off and the clock or analog inputs are still being actively driven, the input voltage and current need to be limited to avoid device damage. If the ADC supplies are off, max/min continuous dc voltage is 0.95 V and max dc current is 20 mA for each input pin (clock or analog), relative to ground. Layout Information The evaluation board represents a good guideline of how to lay out the board to obtain the maximum performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces should be isolated from any external source of interference or noise, including the digital outputs as well as the clock traces. The clock signal traces also should be isolated from other signals, especially in applications where low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when considering the heat dissipation of the device. 20 Copyright (c) 2008-2012, Texas Instruments Incorporated ADS5463-SP www.ti.com DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value Aperture Delay The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay Clock Pulse Duration/Duty Cycle The duty cycle of a clock signal is the ratio of the time the clock signal remains at a logic high (clock pulse duration) to the period of the clock signal. Duty cycle is typically expressed as a percentage. A perfect differential sine wave clock results in a 50% duty cycle. Maximum Conversion Rate The maximum sampling rate at which certified operation is given. All parametric testing is performed at this sampling rate unless otherwise noted. Minimum Conversion Rate The minimum sampling rate at which the ADC functions Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. DNL is the deviation of any single step from this ideal value, measured in units of LSB. Integral Nonlinearity (INL) INL is the deviation of the ADC transfer function from a best-fit line determined by a least-squares curve fit of that transfer function. The INL at each analog input value is the difference between the actual transfer function and this best-fit line, measured in units of LSB. Gain Error Gain error is the deviation of the ADC actual input full-scale range from its ideal value. Gain error is given as a percentage of the ideal input full-scale range. Offset Error Offset error is the deviation of output code from midcode when both inputs are tied to common-mode. SGLS378D - MARCH 2008 - REVISED AUGUST 2012 Temperature drift (with respect to gain error and offset error) specifies the change from the value at the nominal temperature to the value at TMIN or TMAX. It is computed as the maximum variation the parameters over the whole temperature range divided by TMIN - TMAX. Signal-to-Noise Ratio (SNR) SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and in the first five harmonics. P SNR + 10log 10 S PN (1) SNR is given either in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Signal-to-Noise and Distortion (SINAD) SINAD is the ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN) and distortion (PD), but excluding dc. PS SINAD + 10log 10 PN ) PD (2) SINAD is given either in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to Full Scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3 dB for a full-scale input amplitude. Total Harmonic Distortion (THD) THD is the ratio of the power of the fundamental (PS) to the power of the first five harmonics (PD). P THD + 10log 10 S PD (3) THD is typically given in units of dBc (dB to carrier). Two-Tone Intermodulation Distortion IMD3 is the ratio of the power of the fundamental (at frequencies f1, f2) to the power of the worst spectral component at either frequency 2f1 - f2 or 2f2 - f1). IMD3 is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's full-scale range. Temperature Drift Copyright (c) 2008-2012, Texas Instruments Incorporated 21 PACKAGE OPTION ADDENDUM www.ti.com 21-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 5962-0720801VXC ACTIVE CFP HFG 84 1 TBD Call TI Call TI -55 to 125 59620720801VXC ADS5463MHFG-V 5962R0720802VXC ACTIVE CFP HFG 84 1 TBD Call TI Call TI -55 to 125 5962R 0720802VXC ADS5463MHFG-RHA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. 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