5962-0720801VXC - Texas Instruments High-Performance Analog

Reference

Timing

CLK

OVR D[11:0]

CLK

DRY

VREF

VIN

VIN TH1

5 5

DAC2ADC2

ADC3

DAC1

ADC1

DigitalErrorCorrection

–

B0061-03

DRY

OVR

A1 TH2 A2 A3TH3

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

CLASS V, 12-BIT, 500-MSPS ANALOG-TO-DIGITAL CONVERTER

Check for Samples: ADS5463-SP

1FEATURES

• 500-MSPS Sample Rate • Available in a 84-Pin Ceramic Nonconductive

Tie-Bar Package (HFG).

• Available With Radiation Hardness Specified

(RHA) - Total Ionizing Dose 100 krad(Si), • Military Temperature Range

ELDRS Free 100 krad(Si) (–55°C to 125°C Tcase)

• 12-Bit Resolution, 10-Bits Effective Number of APPLICATIONS

Bits (ENOB) • Test and Measurement Instrumentation

• SNR > 64.5 dBFS at 450 MHz and 500 MSPS • Software-Defined Radio

• SFDR > 64.0 dBc at 450 MHz and 500 MSPS • Data Acquisition

• 2.2-VPP Differential Input Voltage • Power Amplifier Linearization

• LVDS-Compatible Outputs • Communication Instrumentation

• Total Power Dissipation: 2.2 W • Radar

• Offset Binary Output Format

• Output Data Transitions on the Rising and

Falling Edges of a Half-Rate Output Clock

• On-Chip Analog Buffer, Track and Hold, and

Reference Circuit

DESCRIPTION/ORDERING INFORMATION

The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and

3.3-V supply, while providing LVDS-compatible digital outputs from the 3.3-V supply. The ADS5463 input buffer

isolates the internal switching of the onboard track and hold (T and H) from disturbing the signal source. An

internal reference generator is also provided to simplify the system design further. The ADS5463 has outstanding

low noise and linearity over input frequency.

The ADS5463 is available in a 84-pin ceramic nonconductive tie-bar package (HFG). The ADS5463 is built on

state-of-the-art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full

military temperature range (–55°C to 125°C Tcase).

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGING/ORDERING INFORMATION(1)

ORDERABLE PART

TEMPERATURE PACKAGE(2) TOP-SIDE MARKING

NUMBER

5962-0720801VXC

5962-0720801VXC ADS5463MHFG-V

–55°C to 125°C Tcase 5962R0720802VXC

84 / HFG 5962R0720802VXC ADS5463MHFG-RHA

ADS5463HFG/EM(3)

25°C ADS5463HFGMPR EVAL ONLY

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) These units are intended for engineering evaluation only. They are processed to a non-compliant flow

(e.g. No Burn-In, etc.) and are tested to a temperature rating of 25°C only. These units are not suitable

for qualification, production, radiation testing or flight use. Parts are not warranted for performance

over the full MIL specified temperature range of -55°C to 125°C or operating life.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)

VALUE UNIT

AVDD5 to GND 6

Supply voltage AVDD3 to GND 5 V

DVDD3 to GND 5

AC signal –0.3 to (AVDD5 + 0.3)

Voltage difference between

AIN, AIN to GND(2) DC signal, TJ= 105°C 0.4 to 4.4 V

pin and ground DC signal, TJ= 125°C 1.0 to 3.8

AC signal –5.2 to 5.2

Voltage difference between

AIN to AIN(2) DC signal, TJ= 105°C –4 to 4 V

these pins DC signal, TJ= 125°C –2.8 to 2.8

AC signal –0.3 to (AVDD5 + 0.3)

Voltage difference between

CLK, CLK to GND(2) DC signal, TJ= 105°C 0.1 to 4.7 V

pin and ground DC signal, TJ= 125°C 1.1 to 3.7

AC signal –3.3 to 3.3

Voltage difference between

CLK to CLK(2) DC signal, TJ= 105°C –3.3 to 3.3 V

these pins DC signal, TJ= 125°C –2.6 to 2.6

Data output to GND(2) LVDS digital outputs –0.3 to (DVDD3 + 0.3) V

TCCharacterized case operating temperature range –55 to 125 °C

TJMaximum junction temperature 150 °C

TSTG Storage temperature range –65 to 150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) Valid when supplies are within recommended operating range.

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

Recommended Operating Conditions MIN TYP MAX UNIT

Supplies

AVDD5 Analog supply voltage 4.75 5 5.25 V

AVDD3 Analog supply voltage 3 3.3 3.6 V

DVDD3 Output driver supply voltage 3 3.3 3.6 V

Analog Input

Differential input range 2.2 Vpp

VCM Input common mode 2.4 V

Digital Output

Maximum differential output load 10 pF

Clock Input

CLK input sample rate (sine wave) 500 MSPS

Clock amplitude, differential sine wave 3 Vpp

Clock duty cycle 50 %

TcOperating case temperature –55 125 °C

Electrical Characteristics

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock

(unless otherwise noted)

PARAMETER TEST CONDITIONS ADS5463-RHA ADS5463-SP

MIN TYP MAX MIN TYP MAX UNIT

Resolution 12 12 Bits

Analog Inputs

Differential input 2.2 2.2 VPP

range

Input resistance Each input to VCM 500 500 Ω

(dc)

Input Each input to ground 2.5 2.5 pF

capacitance

Analog input 1000 2000 1000 2000 MHz

bandwidth

Internal Reference Voltage

VREF Reference Full Temp Range 2.38 2.4 2.42 2.38 2.4 2.42 V

voltage

Dynamic Accuracy

No missing Assured Assured

codes

DNL Differential fIN = 210 MHz Full Temp Range –0.98 ±0.95 1.2 –0.98 ±0.95 1.2 LSB

linearity error

INL Integral linearity fIN = 210 MHz Full Temp Range –3.5 ±1.5 3.5 –2.9 ±1.5 2.9 LSB

error

Offset error Full Temp Range –0.5 0.5 –0.5 0.5 %FS

Offset 0.0009 0.0009 %FS/°C

temperature

coefficient

Gain error Full Temp Range –5 5 –5 5 %FS

Gain –0.02 –0.02 %FS/°C

temperature

coefficient

Power Supply

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

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Electrical Characteristics (continued)

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock

(unless otherwise noted)

PARAMETER TEST CONDITIONS ADS5463-RHA ADS5463-SP

MIN TYP MAX MIN TYP MAX UNIT

IAVDD5 5 V analog 345 335 mA

supply current

IAVDD3 3.3 V analog 148 140 mA

supply current VIN = full scale,

IDVDD3 3.3 V digital 88 88 mA

fIN = 300 MHz, Full Temp Range

supply FS= 500 MSPS

current(includes

LVDS)

Power 2.450 2.425 W

dissipation

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

Electrical Characteristics

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock

(unless otherwise noted)

PARAMETER TEST CONDITIONS ADS5463-RHA ADS5463-SP

MIN TYP MAX MIN TYP MAX UNIT

Dynamic AC Characteristics

fIN = 10 65.4 65.4

MHz

fIN = 70 65.3 65.3

MHz TC= 25°C 65.2 64.1 65.2

fIN = 100 TC= TC,MAX 60.5 62.7

MHz TC= TC,MIN 63.5

TC= 25°C 65.0 63.6 65.0

fIN = 210 TC= TC,MAX 60.0 62.4

MHz TC= TC,MIN 63.2

SNR Signal-to-noise ratio dBFS

TC= 25°C 64.9 62.7 64.9

fIN = 300 TC= TC,MAX 58.0 61.3

MHz TC= TC,MIN 61.9

fIN = 450 64.5 64.5

MHz

fIN = 650 63.7 63.7

MHz

fIN = 900 62.8 62.8

MHz

fIN = 1.0 62.2 62.2

GHz

fIN = 10 63.5 63.5

MHz

fIN = 70 64.2 64.2

MHz TC= 25°C 65.0 57.9 65.0

fIN = 100 TC= TC,MAX 57.9 58.8

MHz TC= TC,MIN 58.6

TC= 25°C 64.0 55.2 64.0

fIN = 210 TC= TC,MAX 55.2 56.6

MHz TC= TC,MIN 56.9

Spurious free dynamic

SFDR dBc

TC= 25°C 64.0 54.1 64.0

range fIN = 300 TC= TC,MAX 51.2 51.3

MHz TC= TC,MIN 56.2

fIN = 450 64.0 64.0

MHz

fIN = 650 61.6 61.6

MHz

fIN = 900 54.5 54.5

MHz

fIN = 1.0 51.6 51.6

GHz

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

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Electrical Characteristics (continued)

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock

(unless otherwise noted)

PARAMETER TEST CONDITIONS ADS5463-RHA ADS5463-SP

MIN TYP MAX MIN TYP MAX UNIT

fIN = 10 63.5 63.5

MHz

fIN = 70 64.2 64.2

MHz TC= 25°C 65.4 57.9 65.4

fIN = 100 TC= TC,MAX 57.9 58.8

MHz TC= TC,MIN 58.6

TC= 25°C 64.4 55.2 64.4

fIN = 210 TC= TC,MAX 55.2 56.6

MHz TC= TC,MIN 56.9

HD2 Second harmonic dBc

TC= 25°C 64.3 54.1 64.3

fIN = 300 TC= TC,MAX 51.2 51.3

MHz TC= TC,MIN 56.2

fIN = 450 64.4 64.4

MHz

fIN = 650 67.1 67.1

MHz

fIN = 900 62.9 62.9

MHz

fIN = 1.0 58.6 58.6

GHz

fIN = 10 104 104

MHz

fIN = 70 104 104

MHz TC= 25°C 87.0 69.0 87.0

fIN = 100 TC= TC,MAX 64.0 68.5

MHz TC= TC,MIN 65.6

TC= 25°C 85.0 66.7 85.0

fIN = 210 TC= TC,MAX 59.0 65.3

MHz TC= TC,MIN 64.1

HD3 Third harmonic dBc

TC= 25°C 76.0 70.1 76.0

fIN = 300 TC= TC,MAX 61.9 61.9

MHz TC= TC,MIN 64.8

fIN = 450 73.3 73.3

MHz

fIN = 650 61.6 61.6

MHz

fIN = 900 54.5 54.5

MHz

fIN = 1.0 51.6 51.6

GHz

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

Electrical Characteristics

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock

(unless otherwise noted)

PARAMETER TEST CONDITIONS ADS5463-RHA ADS5463-SP

MIN TYP MAX MIN TYP MAX UNIT

Dynamic AC Characteristics (continued)

fIN = 10 61.9 61.9

MHz

fIN = 70 62.2 62.2

MHz TC= 25°C 62.0 58.0 62.0

fIN = 100 TC= TC,MAX 55.9 58.0

MHz TC= TC,MIN 58.4

TC= 25°C 62.0 55.8 62.0

fIN = 210 TC= TC,MAX 53.8 56.2

MHz TC= TC,MIN 56.7

Signal-to-noise and

SINAD dBc

TC= 25°C 61.9 54.9 61.9

distortion fIN = 300 TC= TC,MAX 50.2 52.2

MHz TC= TC,MIN 56.1

fIN = 450 61.6 61.6

MHz

fIN = 650 59.4 59.4

MHz

fIN = 900 54.3 54.3

MHz

fIN = 1.0 51.4 51.4

GHz

fIN = 10 83.1 83.1

MHz

fIN = 70 80.2 80.2

MHz TC= 25°C 81.8 72.2 81.8

fIN = 100 TC= TC,MAX 68.0 70.6

MHz TC= TC,MIN 72.6

TC= 25°C 77.5 70.6 77.5

fIN = 210 TC= TC,MAX 62.0 67.1

MHz

Worst harmonic/spur TC= TC,MIN 66.5

(other than HD2 and dBc

TC= 25°C 78.2 69.3 78.2

HD3) fIN = 300 TC= TC,MAX 62.0 66.3

MHz TC= TC,MIN 66.3

fIN = 450 80.6 80.6

MHz

fIN = 650 80.0 80.0

MHz

fIN = 900 79.4 79.4

MHz

fIN = 1.0 77.6 77.6

GHz

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

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Electrical Characteristics (continued)

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1 dBFS differential input, and 3 VPP differential clock

(unless otherwise noted)

PARAMETER TEST CONDITIONS ADS5463-RHA ADS5463-SP

MIN TYP MAX MIN TYP MAX UNIT

fIN = 10 63.5 63.5

MHz

fIN = 70 64 64

MHz TC= 25°C 65.2 57.8 65.2

fIN = 100 TC= TC,MAX 57.8 58.3

MHz TC= TC,MIN 58.1

TC= 25°C 64.1 55.0 64.1

fIN = 210 TC= TC,MAX 55.0 55.9

MHz TC= TC,MIN 56.2

Total harmonic

THD dBc

TC= 25°C 63.8 53.9 63.8

distortion fIN = 300 TC= TC,MAX 51.0 51.0

MHz TC= TC,MIN 55.6

fIN = 450 63.7 63.7

MHz

fIN = 650 60.5 60.5

MHz

fIN = 900 53.9 53.9

MHz

fIN = 1.0 50.8 50.8

GHz

ENOB Effective number of bits TC= 25°C 10.1 9.3 10.1

fIN = 100 TC= TC,MAX 9.0 9.3

MHz TC= TC,MIN 9.4

TC= 25°C 10.0 8.9 10.0

fIN = 210 TC= TC,MAX 8.65 9.0 Bits

MHz TC= TC,MIN 9.1

TC= 25°C 9.9 8.8 9.9

fIN = 300 TC= TC,MAX 8.05 8.3

MHz TC= TC,MIN 9.0

RMS idle-channel Inputs tied to common-mode 0.7 0.7 LSB

noise

LVDS Digital Outputs

VOD Differential output 247 350 454 247 350 454 mV

voltage

VOC Common mode output 1.125 1.375 1.125 1.375 V

voltage

CLK

D OVR[11:0],

N+1

N+5

tCLKL

tDRY

tDATA

tCLKH

D[11:0], OVR

CLK

N+2

N+3

N+4

DRY

NN+1N–1

Sample

N–1

T0158-01

Latency = 3.5 Clock Cycles

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

Figure 1. Timing Diagram

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Timing Characteristics

Typical values at TC= 25°C, full temperature range is TC,MIN = –55°C to TC,MAX = 125°C, sampling rate = 500 MSPS, 50%

clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3 VPP differential clock (unless otherwise noted)

PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT

taAperture delay 200 ps

Aperture jitter, rms 160 fs

Latency 3.5 cycles

tCLK Clock period 2 50 ns

tCLKH Clock pulse duration, high 1 ns

tCLKL Clock pulse duration, low 1 ns

tDRY CLK to DRY delay(2) Zero crossing 750 1500 2500 ps

tDATA CLK to DATA/OVR delay(2) Zero crossing 650 1150 1750 ps

tSKEW DATA to DRY skew tDATA–tDRY -1250 -400 700 ps

tRISE DRY/DATA/OVR rise time 500 ps

tFALL DRY/DATA/OVR fall time 500 ps

(1) Timing parameters are assured by design or characterization, but not production tested. <10pF load on each output pin.

(2) DRY, DATA and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation

delay.

GND

AVDD5

GND

AVDD5

GND

AVDD5

GND

AVDD5

GND

DVDD3

RESERVED

GND

AVDD5

GND

RESERVED

GND

AVDD3

GND

AVDD3

OVR

GND

AVDD3

GND

DRY

DVDD3

DRY

GND

D11

AVDD5

D11

D10

VREF

GND

AVDD5

GND

CLK

GND

AVDD5

DVDD3

GND

AIN

GND

AVDD5

GND

ADS5463

HFGPACKAGE

(TOP VIEW)

7983 7882 7781 76 758084 74 72 71 7073 69 68 67 66 65 64

22 4123 24 25 26 27 28 29 30 31 32 33 34

36 37 38 39 40 42

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

PIN CONFIGURATION

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

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TERMINAL FUNCTIONS

TERMINAL DESCRIPTION

NAME NO.

AIN 17 Differential input signal (positive)

AIN 18 Differential input signal (negative)

4, 9, 14, 15, 20, 23,

AVDD5 Analog power supply (5 V)

25, 27, 29, 33 Analog power supply (3.3 V) (Suggestion for 250 MSPS: leave option to connect to 5 V for

AVDD3 37, 39, 41 ADS5440/4 compatibility)

DVDD3 2, 54, 70 Output driver power supply (3.3 V)

1, 3, 8, 10, 13, 16,

19, 21, 22, 24, 26,

GND 28, 30, 32, 34, 36, Ground

38, 40, 42, 43, 55,

64, 69

CLK 11 Differential input clock (positive). Conversion initiated on rising edge.

CLK 12 Differential input clock (negative)

D0, D0 56, 57 LVDS digital output pair, least-significant bit (LSB)

D1-D3, 58–63 LVDS digital output pair

D1-D3

D4–D5, 65–68 LVDS digital output pairs

D4–D5

D6–D10, 71–80 LVDS digital output pairs

D6–D10

D11, D11 81, 82 LVDS digital output pair, most-significant bit (MSB)

DRY, DRY 83, 84 Data ready LVDS output pair

No connect (5 and 6 should be left floating, 46–53 are possible future bit additions for this pinout

NC 5–6, 46–53 and therefore can be connected to a digital bus or left floating)

Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale

OVR, OVR 44, 45 range.

RESERVED 31, 35 Reserved for possible future control features

VREF 7 Reference voltage

Thermal Characteristics(1)

PARAMETER TEST CONDITIONS TYP UNIT

RθJA Junction-to-free-air thermal resistance Junction-to-case thermal resistance 21.81 °C/W

RθJC Junction-to-case thermal resistance MIL-STD-883 Test Method 1012 0.849 °C/W

(1) This CQFP package has built-in vias that electrically and thermally connect the bottom of the die to a pad on the bottom of the package.

To efficiently remove heat and provide a low-impedance ground path, a thermal land is required on the surface of the PCB directly

underneath the body of the package. During normal surface mount flow solder operations, the heat pad on the underside of the package

is soldered to this thermal land creating an efficient thermal path. Normally, the PCB thermal land has a number of thermal vias within it

that provide a thermal path to internal copper areas (or to the opposite side of the PCB) that provide for more efficient heat removal. TI

typically recommends an 11,9 mm2board-mount thermal pad. This allows maximum area for thermal dissipation, while keeping leads

away from the pad area to prevent solder bridging. A sufficient quantity of thermal/electrical vias must be included to keep the device

within recommended operating conditions. This pad must be electrically at ground potential.

ElectromigrationFailMode

ContinuousTj °C–

YearsinEstimatedLife

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

Figure 2. ADS5463 Estimated Life at Elevated Temperature Electromigration Fail Mode

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TYPICAL CHARACTERISTICS

Typical plots at TA= 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,

and 3 VPP differential clock, (unless otherwise noted)

AC PERFORMANCE AC PERFORMANCE

vs vs

INPUT AMPLITUDE (100 MHz Input Signal) INPUT AMPLITUDE (300 MHz Input Signal)

Figure 3. Figure 4.

SFDR SNR

vs vs

CLOCK LEVEL CLOCK LEVEL

Figure 5. Figure 6.

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

TYPICAL CHARACTERISTICS (continued)

Typical plots at TA= 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,

and 3 VPP differential clock, (unless otherwise noted)

SFDR SNR

vs vs

AVDD5 ACROSS TEMPERATURE AVDD5 ACROSS TEMPERATURE

Figure 7. Figure 8.

SFDR SNR

vs vs

AVDD3 ACROSS TEMPERATURE AVDD3 ACROSS TEMPERATURE

Figure 9. Figure 10.

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TYPICAL CHARACTERISTICS (continued)

Typical plots at TA= 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,

and 3 VPP differential clock, (unless otherwise noted)

SFDR SNR

vs vs

DVDD3 ACROSS TEMPERATURE DVDD3 ACROSS TEMPERATURE

Figure 11. Figure 12.

SFDR SNR

vs vs

INPUT FREQUENCY AND SAMPLING FREQUENCY INPUT FREQUENCY AND SAMPLING FREQUENCY

Figure 13. Figure 14.

APPLICATION INFORMATION

Theory of Operation

The ADS5463 is a 12-bit, 500-MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core

operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs.

The conversion process is initiated by the rising edge of the external input clock. The differential input signal is

captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower

resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling

clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in

a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in

offset binary format.

Input Configuration

The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor

track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.

The input common mode is set internally through a 500-Ωresistor connected from 2.4 V to each of the inputs.

This results in a differential input impedance of 1 kΩ.

ADS5463M

THS9001 AIN

AIN

VIN

VIN THS9001

S0177-03

1000pF 1000pF

39pF

50 W

50 W0.1 Fm

1000pF 1000pF

18 Hm

ADS5463M

AIN

S0176-03

200 W

ACSignal

Source

Mini-Circuits

JTX-4-10T

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SGLS378D –MARCH 2008–REVISED AUGUST 2012

For a full-scale differential input, each of the differential lines of the input signal (pins 17 and 18) swings

symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal

swing of 1.1 Vpp for a total differential input signal swing of 2.2 Vpp. The maximum swing is determined by the

internal reference voltage generator, eliminating the need for any external circuitry for this purpose.

The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in

Figure 15 shows one possible configuration using an RF transformer with termination either on the primary or on

the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back

transformers, which also demonstrate good performance. If voltage gain is required, a step-up transformer can

be used.

Besides the transformer configurations, Texas Instruments offers a wide selection of single-ended operational

amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas

Instruments' THS9001, also can be used for high-input-frequency applications. For large voltage gains at

intermediate-frequencies in the 50-MHz – 500-MHz range, the configuration shown in Figure 16 can be used.

The component values can be tuned for different intermediate frequencies. The example shown is located on the

evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found

in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data

sheet (SLOS426).

Figure 15. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer

Figure 16. Using the THS9001 IF Amplifier With the ADS5463

CLK

ADS5463M

CLK

SquareWaveor

SineWave

0.01 Fm

S0168-05

18pF

AIN

AIN VREF

ADS5463M

+5V

THS4509

348 W

100 W

78.9 W

78.9 W49.9 W

VIN

From

Source

49.9 W

0.1 Fm0.1 Fm

0.22 Fm

0.22 Fm0.22 Fm

S0193-02

ADS5463-SP

SGLS378D –MARCH 2008–REVISED AUGUST 2012

www.ti.com

Figure 17. Using the THS4509 With the ADS5463

For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like

the THS4509 (see Figure 17) is a good solution, as it minimizes board space and reduces the number of

components.

In this configuration, the THS4509 amplifier circuit provides 10-dB of gain, converts the single-ended input to

differential, and sets the proper input common-mode voltage to the ADS5463. The 50-Ωresistors and 18-pF

capacitor between the THS4509 outputs and ADS5463 inputs (along with the input capacitance of the ADC) limit

the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is accomplished via the 78.9-Ωresistor

and 0.22-μF capacitor to ground, in conjunction with the input impedance of the amplifier circuit. A 0.22-μF

capacitor and 49.9-Ωresistor are inserted to ground across the 78.9-Ωresistor and 0.22-μF capacitor on the

alternate input to balance the circuit. Gain is a function of the source impedance, termination, and 348-Ω

feedback resistor. See the THS4509 data sheet for further component values to set proper 50-Ωtermination for

other common gains. Because the ADS5463 recommended input common-mode voltage is 2.4 V, the THS4509

is operated from a single power supply input with V S+ = 5 V and V S– = 0 V (ground). This maintains maximum

headroom on the internal transistors of the THS4509.

Clock Inputs

The ADS5463 clock input can be driven with either a differential clock signal or a single-ended clock input, with

little or no difference in performance between both configurations. In low-input-frequency applications, where

jitter may not be a big concern, the use of a single-ended clock (see Figure 18) could save some cost and board

space without any trade-off in performance. When clocked with this configuration, it is best to connect CLK to

ground with a 0.01 μF capacitor, while CLK is ac-coupled with a 0.01-μF capacitor to the clock source, as shown

in Figure 18.

Figure 18. Single-Ended Clock

CLK

ADS5463M

CLK

0.1 Fm

Clock

Source

S0194-02

ADS5463-SP

www.ti.com

SGLS378D –MARCH 2008–REVISED AUGUST 2012

Figure 19. Differential Clock

For jitter-sensitive applications, the use of a differential clock has advantages (as with any other ADC) at the

system level. The differential clock allows for common-mode noise rejection at the PCB level. With a differential

clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications because the

board clock jitter is superior.

A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum

ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise

on jitter. Figure 19 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details.

The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩresistors. It is

recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,

the ADS5463 features good tolerance to clock common-mode variation. Additionally, the internal ADC core uses

both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.

Digital Outputs

The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal

(DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits.

The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the

ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a

half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital

outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs

with too much capacitance, which shortens the data-valid timing window. The values given for timing were

obtained with a measured 14-pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential

parasitic capacitance).

Power Supplies

The ADS5463 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5

and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). The use of low-noise power

supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies; switched

supplies tend to generate more noise components that can be coupled to the ADS5463. The user may be able to

supply power to the device with a less-than-ideal supply and still achieve good performance. It is not possible to

make a single recommendation for every type of supply and level of decoupling for all systems.

The power consumption of the ADS5463 does not change substantially over clock rate or input frequency as a

result of the architecture and process.

Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up

sequence is recommended. When there is a delay in power up between these two supplies, the one that lags

could have current sinking through an internal diode before it powers up. The sink current can be large or small

depending on the impedance of the external supply and could damage the device or affect the supply source.

The best power up sequence is one of the following options (regardless of when AVDD5 powers up):

• Power up both AVDD3 and DVDD3 at the same time (best scenario), OR

• Keep the voltage difference less than 0.8 V between AVDD3 and DVDD3 during the power up (0.8 V is not a

hard specification - a smaller delta between supplies is safer).

If the above sequences are not practical then the sink current from the supply needs to be controlled or

protection added externally. The max transient current (on the order of msec) for the DVDD3 or AVDD3 pin is

500 mA to avoid potential damage to the device or reduce its lifetime.

ADS5463-SP

SGLS378D –MARCH 2008–REVISED AUGUST 2012

www.ti.com

The values for the analog and clock inputs given in the Absolute Maximum Ratings are valid when the supplies

are on. When the power supplies are off and the clock or analog inputs are still being actively driven, the input

voltage and current need to be limited to avoid device damage. If the ADC supplies are off, max/min continuous

dc voltage is ±0.95 V and max dc current is 20 mA for each input pin (clock or analog), relative to ground.

Layout Information

The evaluation board represents a good guideline of how to lay out the board to obtain the maximum

performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane

for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces

should be isolated from any external source of interference or noise, including the digital outputs as well as the

clock traces. The clock signal traces also should be isolated from other signals, especially in applications where

low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when

considering the heat dissipation of the device.

THD +10log10 PS

SINAD +10log10 PS

PN)PD

SNR +10log10 PS

ADS5463-SP

www.ti.com

SGLS378D –MARCH 2008–REVISED AUGUST 2012

DEFINITION OF SPECIFICATIONS Temperature drift (with respect to gain error and

offset error) specifies the change from the value at

Analog Bandwidth the nominal temperature to the value at TMIN or TMAX.

The analog input frequency at which the power of the It is computed as the maximum variation the

fundamental is reduced by 3 dB with respect to the parameters over the whole temperature range divided

low-frequency value by TMIN – TMAX.

Aperture Delay Signal-to-Noise Ratio (SNR)

The delay in time between the rising edge of the input SNR is the ratio of the power of the fundamental (PS)

sampling clock and the actual time at which the to the noise floor power (PN), excluding the power at

sampling occurs dc and in the first five harmonics.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay (1)

Clock Pulse Duration/Duty Cycle SNR is given either in units of dBc (dB to carrier)

The duty cycle of a clock signal is the ratio of the time when the absolute power of the fundamental is used

the clock signal remains at a logic high (clock pulse as the reference, or dBFS (dB to full scale) when the

duration) to the period of the clock signal. Duty cycle power of the fundamental is extrapolated to the

is typically expressed as a percentage. A perfect converter’s full-scale range.

differential sine wave clock results in a 50% duty

cycle. Signal-to-Noise and Distortion (SINAD)

SINAD is the ratio of the power of the fundamental

Maximum Conversion Rate (PS) to the power of all the other spectral components

The maximum sampling rate at which certified including noise (PN) and distortion (PD), but excluding

operation is given. All parametric testing is performed dc.

at this sampling rate unless otherwise noted.

Minimum Conversion Rate

The minimum sampling rate at which the ADC (2)

functions SINAD is given either in units of dBc (dB to carrier)

Differential Nonlinearity (DNL) when the absolute power of the fundamental is used

An ideal ADC exhibits code transitions at analog input as the reference, or dBFS (dB to Full Scale) when the

values spaced exactly 1 LSB apart. DNL is the power of the fundamental is extrapolated to the

deviation of any single step from this ideal value, converter’s full-scale range.

measured in units of LSB. Effective Resolution Bandwidth

Integral Nonlinearity (INL) The highest input frequency where the SNR (dB) is

INL is the deviation of the ADC transfer function from dropped by 3 dB for a full-scale input amplitude.

a best-fit line determined by a least-squares curve fit Total Harmonic Distortion (THD)

of that transfer function. The INL at each analog input THD is the ratio of the power of the fundamental (PS)

value is the difference between the actual transfer to the power of the first five harmonics (PD).

function and this best-fit line, measured in units of

LSB.

Gain Error (3)

Gain error is the deviation of the ADC actual input THD is typically given in units of dBc (dB to carrier).

full-scale range from its ideal value. Gain error is

given as a percentage of the ideal input full-scale Two-Tone Intermodulation Distortion

range. IMD3 is the ratio of the power of the fundamental (at

frequencies f1, f2) to the power of the worst spectral

Offset Error component at either frequency 2f1– f2or 2f2– f1).

Offset error is the deviation of output code from mid- IMD3 is either given in units of dBc (dB to carrier)

code when both inputs are tied to common-mode. when the absolute power of the fundamental is used

as the reference, or dBFS (dB to full scale) when the

power of the fundamental is extrapolated to the

converter’s full-scale range.

Temperature Drift

PACKAGE OPTION ADDENDUM

www.ti.com 21-Nov-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-0720801VXC ACTIVE CFP HFG 84 1 TBD Call TI Call TI -55 to 125 5962-

0720801VXC

ADS5463MHFG-V

5962R0720802VXC ACTIVE CFP HFG 84 1 TBD Call TI Call TI -55 to 125 5962R

0720802VXC

ADS5463MHFG-RHA

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 21-Nov-2013

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS5463-SP :

•Catalog: ADS5463

•Enhanced Product: ADS5463-EP

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

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