2×, 31.76 W, Digital Input,
Filterless Stereo Class D Audio Amplifier
Data Sheet
SSM3582A
Rev. A Document Feedback
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FEATURES
Digital input stereo, high efficiency Class-D amplifier
Operates from a single 4.5 V to 16.5 V supply
State-of-the-art, proprietary, filterless Σ-Δ modulation
106.5 dB SNR at PO = 8.1 W, RL = 8 Ω, AV = 19 dB,
PVDD = 12 V, A weighted
0.004% THD + N at 5 W into 8 Ω
38.5 µV rms output voltage noise, f = 20 Hz to 20 kHz,
A weighted, PVDD = 16 V, 8 Ω
Pop and clickless on and off sequence
2× 14.67 W output at 12 V supply to 4 Ω loads at <1% THD + N
2× 14.4 W output at 16 V supply to 8 Ω loads at <1% THD + N
Mono mode for increased maximum output power
1× 49.69 W output at 16 V supply to 2 Ω loads at <1% THD + N
Support for low impedance loads
As low as 3 Ω/5 μH in stereo mode
As low as 2 Ω/5 μH in mono mode
High power efficiency
93.8% efficiency into an 8 Ω load
90.6% efficiency into a 4 Ω load
12.34 mA quiescent current with single 12 V PVDD supply
Single-supply operation with internal LDOs or option to use
an external 5 V and 1.8 V supply for lowest power
consumption
I2C control and hardware modes with up to 16 pin-selectable
slots/addresses
Supported sample rates from 8 kHz to 192 kHz with 24-bit
resolution
Multiple PCM audio serial data formats
TDM slave with support for up to 16 devices on a single bus
I2S or left justified slave
Adjustable full-scale output tailored for many PVDD sources
2- and 3-cell Li-Ion batteries
Digital volume control with selectable smooth ramp
Automatic power-down function
Supply monitoring automatic gain control (AGC) function
reduces system brownout
Standalone operational mode without I2C
Temperature sensor with 1°C step readout via I2C
Short-circuit, undervoltage, and thermal protection
Thermal early warning
Power-on reset
PVDD sensing ADC
40-lead, 6 mm × 6 mm LFCSP with thermal pad
APPLICATIONS
Mobile computing
All in one computers
Portable electronics
Wireless speakers
Televisions
FUNCTIONAL BLOCK DIAGRAM
OUTL+
OUTL–
SDA
SCL
ADDR0
ADDR1
PVDD
DVDD
AGND
BSTL+
BSTL–
PGND
DAC
PVDD
ADC TEMPERATURE
SENSOR
DVDD
1.8V LDO
VOLUME
BATTERY
AGC
SSM3582A
THREE-LEVEL
Σ-Δ
MODULATOR FULL BRIDGE
POWER STAGE
I
2
C
CONTROL
I
2
S
TDM
INTERFACE
BCLK
FSYNC
SDATA OUTR+
OUTR–
BSTR+
BSTR–
DAC THREE-LEVEL
Σ-Δ
MODULATOR FULL BRIDGE
POWER STAGE
DVDD_EN AVDD
AVDD
5V LDO
AVDD_EN
21861-001
Figure 1.
SSM3582A Data Sheet
Rev. A | Page 2 of 58
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications .................................................................................... 4
Digital Input/Output Specifications .......................................... 8
Digital Timing Specifications ..................................................... 9
Digital Input Timing Specifications .......................................... 9
Absolute Maximum Ratings ......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions .......................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 25
Overview ...................................................................................... 25
Power Supplies ............................................................................ 25
Power-Up Sequence ................................................................... 26
Power-Down Operation ............................................................ 26
Clocking ....................................................................................... 26
Digital Audio Serial Interface ................................................... 26
Standalone Operation ................................................................ 30
Mono Mode ................................................................................ 31
Analog and Digital Gain ........................................................... 31
Pop and Click Suppression ....................................................... 31
Temperature Sensor ................................................................... 31
Faults and Limiter Status Reporting ........................................ 32
VBAT (PVDD) Sensing ............................................................... 32
Limiter and Battery Tracking Threshold Control ................. 32
High Frequency Clipper ............................................................ 35
EMI Noise ................................................................................... 35
Output Modulation Description .............................................. 35
Bootstrap Capacitors ................................................................. 36
Power Supply Decoupling......................................................... 36
Output EMI Filtering ................................................................. 36
PCB Placement ........................................................................... 36
Layout .......................................................................................... 37
Register Summary .......................................................................... 38
Register Details ............................................................................... 39
Applications Information ............................................................. 56
Typical Application Circuit ...................................................... 56
Outline Dimensions ....................................................................... 58
Ordering Guide .......................................................................... 58
REVISION HISTORY
8/2020—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Change to General Description Section ........................................ 3
Changes to Table 1 ........................................................................... 4
Changes to Table 5 ........................................................................... 8
Change to Table 16 ......................................................................... 28
Changes to Mono Mode Section and Table 19 .......................... 31
Changes to Figure 76 Caption ...................................................... 33
Change to Table 46 ........................................................................ 52
Change to Table 51 ........................................................................ 55
Changes to Figure 86 ..................................................................... 56
Changes to Figure 87 ..................................................................... 57
12/2019—Revision 0: Initial Version
Data Sheet SSM3582A
Rev. A | Page 3 of 58
GENERAL DESCRIPTION
The SSM3582A is a fully integrated, high efficiency, digital
input stereo Class-D audio amplifier. The device can operate from
a single supply and requires only a few external components,
significantly reducing the circuit bill of materials.
A proprietary, spread spectrum Σ-Δ modulation scheme enables
direct connection to the speaker and ensures state-of-the-art
analog performance while lowering radiated emissions
compared to other Class-D architectures. An optional ultralow
electromagnetic interference (EMI) mode significantly reduces
radiated emissions above 100 MHz, enabling longer speaker cable
lengths. Audio is transmitted digitally to the amplifier, minimizing
the possibility of signal corruption in digital environments. The
amplifier provides outstanding analog performance, with a
106 dB signal-to-noise ratio and a low 0.004% total harmonic
distortion + noise (THD + N).
The SSM3582A operates from a single 4.5 V to 16.5 V supply and
is capable of delivering 2× 15 W rms continuously into 8 Ω and
4 Ω loads at <1% total harmonic distortion (THD). The efficient
modulation scheme maintains excellent power efficiency over a
wide range of impedances: 93.8% into an 8 Ω load and 90.6%
into a 4 Ω load. Optimization of the output pulse maintains
performance at impedances as low as 3 Ω/5 μH, enabling its use
with extended bandwidth tweeters.
The pulse code modulation (PCM) audio serial port supports
most common protocols, such as I2S, left justified, and time
division multiplexing (TDM), and can address up to 16 devices
on a single interface, for up to 32 audio playback channels.
IC operation is controlled through a dedicated I2C interface.
The two ADDRx pins (2×, five-level) define up to 16 individual
addresses in I2C and standalone modes and automatically set
the default TDM slots attribution.
A micropower shutdown mode is triggered by removing the
digital audio interface clock, with a typical current of <1 µA.
A software power-down mode is also available.
An automatic power-down feature shuts down the amplifier
and the digital-to-analog converter (DAC) when no signal is
present at the input, minimizing power consumption during
digital silence. The device restarts when nonzero data is present at
the input. Mute and unmute transitions are pop and click free.
The SSM3582A is specified over the commercial temperature
range of −40°C to +85°C. The device has built in thermal
shutdown and output short-circuit protection, as well as an
early thermal warning with programmable gain limiting to
maintain operation.
The SSM3582A is available in a 40-lead, 6 mm × 6 mm lead
frame chip scale package (LFCSP), with a thermal pad to
improve heat dissipation.
SSM3582A Data Sheet
Rev. A | Page 4 of 58
SPECIFICATIONS
PVDD = 12 V, AVDD = 5 V (external), DVDD = 1.8 V (external), load resistance (RL) = 8 Ω + 33 μH, BCLK = 3.072 MHz, FSYNC = 48 kHz,
TA = −40°C to +85°C, unless otherwise noted. The measurements are taken with a 20 kHz AES17 low-pass filter. The other load impedances
used are 4 Ω + 15 μH and 3 Ω + 10 μH. Measurements are taken with a 20 kHz AES17 low-pass filter, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power Per Channel PO
Stereo Mode f = 1 kHz, both channels driven
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 14.4 W
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 8.1 W
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 2.76 W
RL = 8 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 1.41 W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 18 W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 10 W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 3.43 W
RL = 8 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 1.75 W
RL = 4 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 25.6 W
RL = 4 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 14.67 W
RL = 4 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 5.06 W
RL = 4 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 2.6 W
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 31.76 W
R
L
= 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PV
DD
= 12 V
18.31
W
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 6.3 W
RL = 4 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 3.21 W
Mono Mode f = 1 kHz
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 35.4 36.11 W
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 20.0 20.46 W
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 7 W
RL = 3 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 3.58 W
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 44.26 44.96 W
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 25 25.49 W
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 8.7 W
RL = 3 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 4.43 W
RL = 2 Ω, THD + N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 49 49.69 W
RL = 2 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 27.7 28.55 W
RL = 2 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 9.85 W
RL = 2 Ω, THD +N < 1%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 5 W
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 16 V 59.2 62.4 W
R
L
= 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PV
DD
= 12 V
34.2
35.5
W
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 12.22 W
RL = 2 Ω, THD + N = 10%, f = 1 kHz, 20 kHz BW, PVDD = 5 V 6.22 W
Minimal Load Inductance Speaker inductance 5 μH
Efficiency η
Stereo Mode Both channels driven
PO = 10 W, RL = 8 Ω, PVDD = 12 V 94 %
PO = 10 W, RL = 8 Ω, PVDD = 12 V (low EMI mode) 93.8 %
PO = 18 W, RL = 4 Ω, PVDD = 12 V 90.6 %
PO = 15 W, RL = 4 Ω, PVDD = 12 V (low EMI mode) 89.5 %
Data Sheet SSM3582A
Rev. A | Page 5 of 58
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Mono Mode
PO = 25 W, RL = 3 Ω, PVDD = 12 V 92.3 %
PO = 25 W, RL = 3 Ω, PVDD = 12 V (low EMI mode) 92.1 %
PO = 35 W, RL = 2 Ω, PVDD = 12 V 83.8 89.9 %
PO = 35 W, RL = 2 Ω, PVDD = 12 V (low EMI mode) 83.8 89.7 %
PO = 35 W, RL = 2 Ω, PVDD = 16 V 81.2 89.9 %
PO = 35 W, RL = 2 Ω, PVDD = 16 V (low EMI mode) 80.6 89.9 %
Total Harmonic Distortion +
Noise
THD + N PO = 5 W into 8 Ω, f = 1 kHz, PVDD = 12 V 0.004 %
PO = 10 W into 2 Ω, f = 1 kHz, PVDD = 16 V, mono mode 0.004 0.024 %
Output Stage On Resistance RON 100 mΩ
Overcurrent Protection
Trip Point
IOC Stereo mode 4.68 6 A peak
Average Switching
Frequency
fSW 300 kHz
Differential Output Offset
Voltage
VOOS AV = 19 dB ±1 ±5 mV
Crosstalk between Left and
Right
Measured at 1 kHz with regards to full-scale output 75 100 dB
POWER SUPPLIES
Supply Voltage Range PVDD 4.5 16.5 V
AVDD 4.5 5.0 5.5 V
DVDD 1.62 1.8 1.98 V
Power Supply Rejection
Ratio
PSRR
PVDD PSRRAC PVDD ripple voltage (VRIPPLE) = 100 mV rms at 1 kHz 70 86 dB
PVDD ripple voltage (VRIPPLE) = 1 V rms at 1 kHz 70 88 dB
AVDD PSRRAC AVDD ripple voltage (VRIPPLE) = 100 mV rms at 1 kHz 53 58 dB
AVDD ripple voltage (VRIPPLE) = 100 mV rms at 17 kHz 53 58 dB
ANALOG GAIN AV Measured with 0 dBFS input at 1 kHz
Gain = 00 PVDD ≥ 6.3 V 6.2 V peak
Gain = 01 PVDD ≥ 9 V 8.75 V peak
Gain = 10 PVDD ≥ 12.6 V 12.5 V peak
Gain = 11 PVDD = 16 V 15.5 V peak
SHUTDOWN CONTROL1
Turn On Time, Volume
Ramp Disabled
tWU Time from SPWDN = 0 to output switching, DAC_HV = 1 or
DAC_MUTE_x = 1, tWU = 4 FSYNC cycles to 7 FSYNC cycles +
7.68 ms
Sampling frequency (fS) =
12 kHz
8.01 8.27 ms
fS = 24 kHz 7.84 7.98 ms
fS = 48 kHz 7.76 7.83 ms
fS = 96 kHz 7.72 7.76 ms
fS = 192 kHz 7.70 7.72 ms
Turn On Time, Volume
Ramp Enabled
tWUR Time from SPWDN = 0 to full volume output switching,
DAC_HV = 0 and DAC_MUTE_x = 0, VOL_x = 0x40
fS = 12 kHz tWUR = tWU + 15.83 ms 23.84 24.10 ms
fS = 24 kHz tWUR = tWU + 15.83 ms 23.67 23.81 ms
fS = 48 kHz tWUR = tWU + 15.83 ms 23.59 23.66 ms
fS = 96 kHz tWUR = tWU + 7.92 ms 15.64 15.68 ms
fS = 192 kHz tWUR = tWU + 0.99 ms 8.69 8.71 ms
Turn Off Time, Volume
Ramp Disabled
tSD Time from SPWDN = 1 to full power-down, DAC_HV = 1 or
DAC_MUTE_x = 1
100 µs
SSM3582A Data Sheet
Rev. A | Page 6 of 58
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Turn Off Time, Volume
Ramp Enabled
tSDR
Time from SPWDN = 1 to full power-down, DAC_HV = 0 and
DAC_MUTE_x = 0, VOL_x = 0x40
fS = 12 kHz tSDR = tSD + 15.83 ms 15.932 ms
fS = 24 kHz tSDR = tSD + 7.92 ms 8.016 ms
fS = 48 kHz tSDR = tSD + 15.83 ms 15.932 ms
fS = 96 kHz tSDR = tSD + 15.83 ms 15.932 ms
fS = 192 kHz tSDR = tSD + 15.83 ms 15.932 ms
Output Impedance ZOUT 100 kΩ
NOISE PERFORMANCE2 Stereo mode
Output Voltage Noise en f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 8 Ω 37.8 µV rms
f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 8 Ω 38.5 µV rms
f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 4 Ω 36.8 µV rms
f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 4 Ω 36.3 µV rms
Mono mode
f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V, 2 Ω 42 57 µV rms
f = 20 Hz to 20 kHz, A weighted, PVDD = 16 V, 2 Ω 48 82 µV rms
Signal-to-Noise Ratio SNR PO = 8.1 W, RL = 8 Ω, AV = 19 dB, PVDD = 12 V, A weighted 106.5 dB
PO = 14.4 W, RL = 8 Ω, AV = 21 dB, PVDD = 16 V, A weighted 108.9 dB
PO = 14.67 W, RL = 4 Ω, AV = 19 dB, PVDD = 12 V, A weighted 106.3 dB
PO = 25.58 W, RL = 4 Ω, AV = 21 dB, PVDD = 16 V, A weighted 108.9 dB
Mono mode
PO = 28.55 W, RL = 2 Ω, AV = 19 dB, PVDD = 12 V, A weighted 102.6 105.3 dB
PO = 49.69 W, RL = 2 Ω, AV = 21 dB, PVDD = 16 V, A weighted 101.1 106.5 dB
PVDD ADC PERFORMANCE
PVDD Sense Full-Scale
Range
PVDD with full-scale ADC output 3.8 16.2 V
PVDD Sense Absolute
Accuracy
PVDD = 15 V −8 +8 LSB
PVDD = 5 V −6 +6 LSB
Resolution Unsigned 8-bit output with 3.8 V offset 8 Bits
Temperature Sense ADC
Temperature Sense Range −60 +160 °C
Temperature Sense
Accuracy
±5 ±11 °C
DIE TEMPERATURE
Overtemperature Warning 104 117 °C
Overtemperature Protection 137 145 °C
UNDERVOLTAGE FAULT
AVDD Pin Supply AVDD 3.6 V
PVDD Pin Supply PVDD 3.6 V
1 Guaranteed by design.
2 Noise performance is based on the bench data for TA = −40°C to +85°C.
Data Sheet SSM3582A
Rev. A | Page 7 of 58
Software master power-down indicates that the clocks are turned off. Automatic power-down indicates that there is no dither or zero
input signal with clocks on. The device enters soft power-down after 2048 cycles of zero input values. Quiescent indicates triangular
dither with zero input signal. All specifications are typical, with a 48 kHz sample rate, in stereo mode, unless otherwise noted.
Table 2. Power Supply Current Consumption, No Load1
Edge Rate
Control
Mode
Internal
Regulator
IPVDD IDVDD IAVDD
Test Conditions PVDD = 5 V PVDD = 12 V PVDD = 16 V PVDD = 1.8 V PVDD = 5 V Unit
Normal Disabled Software master power-down 0.065 0.065 0.065 2.68 7.542 µA
Automatic power-down 0.065 0.065 0.065 43.72 7.542 µA
Quiescent 2.54 4.94 6.25 0.945 6.335 mA
Enabled Software master power-down 0.065 0.065 0.065 N/A N/A µA
Automatic power-down 209 286 329 N/A N/A µA
Quiescent
9.78
12.38
14.05
N/A
N/A
mA
Low EMI Disabled Software master power-down 0.065 0.065 0.065 2.68 7.542 µA
Automatic power-down 0.065 0.065 0.065 43.72 7.542 µA
Quiescent 2.56 5.01 6.31 0.945 6.171 mA
Enabled Software master power-down 0.065 0.065 0.065 N/A N/A µA
Automatic power-down 209 286 329 N/A N/A µA
Quiescent 9.69 12.09 13.74 N/A N/A mA
1 N/A means not applicable.
Table 3. Power Supply Current Consumption, 4 Ω + 15 µH1
Edge Rate
Control
Mode
Internal
Regulator
IPVDD IDVDD IAVDD
Test Conditions PVDD = 5 V PVDD = 12 V PVDD = 16 V PVDD = 1.8 V PVDD = 5 V Unit
Normal Disabled Software master power-down 0.065 0.065 0.065 2.68 7.542 µA
Automatic power-down 0.065 0.065 0.065 43.72 7.542 µA
Quiescent 2.6 4.93 6.25 0.945 6.477 mA
Enabled Software master power-down 0.065 0.065 0.065 N/A N/A µA
Automatic power-down 209 286 329 N/A N/A µA
Quiescent 9.83 12.34 13.58 N/A N/A mA
Low EMI Disabled Software master power-down 0.065 0.065 0.065 2.68 7.542 µA
Automatic power-down 0.065 0.065 0.065 43.72 7.542 µA
Quiescent 2.51 4.62 5.6 0.945 6.182 mA
Enabled Software master power-down 0.065 0.065 0.065 N/A N/A µA
Automatic power-down 209 286 329 N/A N/A µA
Quiescent 9.64 11.86 12.87 N/A N/A mA
1 N/A means not applicable.
SSM3582A Data Sheet
Rev. A | Page 8 of 58
Table 4. Power Supply Current Consumption, 8 Ω + 33 µH1
Edge Rate
Control
Mode
Internal
Regulator
IPVDD IDVDD IAVDD
Test Conditions PVDD = 5 V PVDD = 12 V PVDD = 16 V PVDD = 1.8 V PVDD = 5 V Unit
Normal Disabled Software master power-down 0.065 0.065 0.065 2.68 7.542 µA
Automatic power-down 0.065 0.065 0.065 43.72 7.542 µA
Quiescent 2.59 5.02 6.31 0.942 6.432 mA
Enabled Software master power-down 0.065 0.065 0.065 N/A N/A µA
Automatic power-down 209 286 329 N/A N/A µA
Quiescent 9.82 12.39 13.73 N/A N/A mA
Low EMI Disabled Software master power-down 0.065 0.065 0.065 2.68 7.542 µA
Automatic power-down 0.065 0.065 0.065 43.72 7.542 µA
Quiescent 2.57 4.86 6.02 0.942 6.232 mA
Enabled Software master power-down 0.065 0.065 0.065 N/A N/A µA
Automatic power-down 209 286 329 N/A N/A µA
Quiescent 9.65 12.02 13.18 N/A N/A mA
1 N/A means not applicable.
Table 5. Power-Down Current
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER-DOWN CURRENT External AVDD = 5 V and DVDD = 1.8 V, software
master power-down, no BCLK/FSYNC
IPVDD PVDD = 5 V 65 463 nA
PVDD = 12 V 65 744 nA
PVDD = 16 V 65 935 nA
IAVDD AVDD = 5 V external 7.542 22.64 μA
IDVDD DVDD = 1.8 V external 2.7 27.27 μA
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 6.
Parameter Min Typ Max Unit
INPUT VOLTAGE1
BCLK, FSYNC, SDATA, SCL, and SDA Pins
High (VIH) 0.7 × DVDD 5.5 V
Low (VIL) −0.3 +0.3 × DVDD V
INPUT LEAKAGE
BCLK, FSYNC, SDATA, ADDRx, SCL, and SDA Pins
High (IIH) 1 µA
Low (IIL) 1 µA
INPUT CAPACITANCE 5 pF
OUTPUT DRIVE STRENGTH1
SDA 3 5 mA
SAMPLE RATE (FSYNC FREQUENCY) 8 192 kHz
1 The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
Data Sheet SSM3582A
Rev. A | Page 9 of 58
DIGITAL TIMING SPECIFICATIONS
All timing specifications are given for the default setting (I2S mode) of the serial input port.
Table 7.
Limit
Parameter Min Max Unit Description
I
2
C PORT
fSCL
400
kHz
SCL frequency
tSCLH 0.26 µs SCL high
tSCLL 0.5 µs SCL low
tSCS 0.26 µs Setup time; relevant for repeated start condition
tSCH 0.26 µs Hold time; after this period, the first clock is generated
tDS 50 ns Data setup time
tDH
0.14
µs
Data hold time
tSCR 120 ns SCL rise time
tSCF 120 ns SCL fall time
tSDR 120 ns SDA rise time
t
SDF
120 ns SDA fall time
tBFT
0.5
µs
Bus free time (time between stop and start)
DIGITAL INPUT TIMING SPECIFICATIONS
Table 8.
Limit
Parameter Min Max Unit Description
SERIAL PORT
tBIL 10 ns BCLK low pulse width
tBIH 10 ns BCLK high pulse width
tSIS 4 ns SDATA setup; time to BCLK rising
tSIH 4 ns SDATA hold; time from BCLK rising
tLIS 5 ns FSYNC setup time to BCLK rising
tLIH 5 ns FSYNC hold time to BCLK rising
tBP 20 ns Minimum BCLK period
Digital Timing Diagrams
t
SCH
t
SCS
t
BFT
t
SCF
t
DS
t
SCLL
t
SCR
t
DH
t
SCLH
t
SCH
STOP
CONDITION
START
CONDITION
SDA
SCL
t
SDF
t
SDR
21861-002
Figure 2. I2C Port Timing
SSM3582A Data Sheet
Rev. A | Page 10 of 58
tSIS
tSIH
tSIS
tSIH
tLIH
tBP
tBIH
BCLK
FSYNC
SDATA
LEFT-JUSTIFIED
MODE
SDATA
I2C-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
tBIL
tLIS
tSIS
tSIH
tSIS
tSIH
MSB
MSB
MSB LSB
MSB – 1
21861-003
Figure 3. Serial Input Port Timing
PVDD
PVDD/2
tWU
I2C POWER-UP COMMAND
OUTPUT
0V
21861-104
Figure 4. Turn On Time, Hard Volume
t
SD
I2C POWER- DOW N COMM AND
OUTPUT
PVDD
0V
21861-105
Figure 5. Turn Off Time, Hard Volume
Data Sheet SSM3582A
Rev. A | Page 11 of 58
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 9.
Parameter Rating
PVDD Supply Voltage −0.3 V to +17 V
DVDD Supply Voltage −0.3 V to +1.98 V
AVDD Supply Voltage −0.3 V to +5.5 V
PGND and AGND Differential ±0.3 V
Digital Input Pins
FSYNC, BCLK, SDATA, SCL, SDA −0.3 V to +5.5 V
Analog Input Pins
ADDRx −0.3 V to +1.98 V
AVDD_EN −0.3 V to +17 V
DVDD_EN −0.3 V to +5.5 V
Electrostatic Discharge (ESD) Susceptibility
Human Body Model 2 kV
Charged Device Model 1 kV
Temperature Range
Storage −65°C to +150°C
Operating −40°C to +85°C
Junction −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the junction to air temperature, and θJC is the junction to
case temperature, and both are specified for the worst case
conditions, that is, a device soldered in a circuit board for
surface-mount packages.
Table 10. Thermal Resistance
Package Type θJA1 θJC1 Unit
CP-40-7 27 1.1 °C/W
1 θJA and θJC are determined according to JESD51-9 on a 4-layer (2s2p) PCB
with natural convection cooling.
ESD CAUTION
SSM3582A Data Sheet
Rev. A | Page 12 of 58
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1PGND 2PGND 3AVDD_EN
NOTES
1. USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD
TO THE GRO UND P LANE ON T HE P CB.
4SCL 5SDA 6FSYNC 7SDATA 8BCLK 9PGND 10PGND
23 DVDD_EN
24 AVDD
25 AGND
26 ADDR0
27 ADDR1
28 DVDD
29 PGND
30 PGND
22 PGND
21 PGND
11BSTR+ 12OUTR+ 13OUTR+
15PVDD
17PVDD 16PVDD
18OUTR– 19OUTR– 20BSTR–
14PVDD
33 OUTL–
34 PVDD
35 PVDD
36 PVDD
37 PVDD
38 OUTL+
39 OUTL+
40 BSTL+
32 OUTL–
31 BSTL–
SSM3582A
TOP VIEW
(No t t o Scal e)
21861-004
Figure 6. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 PGND PWR Left Channel Power Stage Ground.
2 PGND PWR Left Channel Power Stage Ground.
3 AVDD_EN AIN 5 V AVDD Regulator Enable. Connect this pin to PVDD to enable the AVDD regulator or connect to AGND
to disable the regulator. When this pin is connected to PVDD, the regulator is enabled. When this pin is
connected to AGND, the regulator is disabled.
4 SCL DIN I2C Clock Input.
5 SDA DIO I2C Data.
6 FSYNC DIN I2S/TDM Frame Sync Input.
7 SDATA DIN I2S/TDM Serial Data Input.
8 BCLK DIN I2S/TDM Bit Clock Input.
9
PGND
PWR
Right Channel Power Stage Ground.
10 PGND PWR Right Channel Power Stage Ground.
11 BSTR+ AIN Bootstrap Input, Right Channel Noninverting.
12 OUTR+ AOUT Right Channel Noninverting Output.
13 OUTR+ AOUT Right Channel Noninverting Output.
14 PVDD PWR Right Channel Power Stage Supply.
15 PVDD PWR Right Channel Power Stage Supply.
16 PVDD PWR Right Channel Power Stage Supply.
17 PVDD PWR Right Channel Power Stage Supply.
18 OUTR− AOUT Right Channel Inverting Output.
19 OUTR− AOUT Right Channel Inverting Output.
20 BSTR− AIN Bootstrap Input, Right Channel Inverting.
21 PGND PWR Right Channel Power Stage Ground.
22 PGND PWR Right Channel Power Stage Ground.
23 DVDD_EN AIN 1.8 V DVDD Regulator Enable. Connect this pin to AVDD to enable the DVDD regulator or connect to
AGND to disable the regulator. When this pin is connected to AVDD, the regulator is enabled. When this
pin is connected to AGND, the regulator is disabled.
24 AVDD PWR Analog Supply 5 V Regulator Output/External 5 V Input.
25 AGND PWR Analog Ground.
26 ADDR0 AIN Address Select 0 (See Table 14).
27 ADDR1 AIN Address Select 1 (See Table 14).
Data Sheet SSM3582A
Rev. A | Page 13 of 58
Pin No. Mnemonic Type1 Description
28 DVDD PWR Digital Supply 1.8 V Regulator Output/External 1.8 V Input.
29 PGND PWR Left Channel Power Stage Ground.
30 PGND PWR Left Channel Power Stage Ground.
31 BSTL− AIN Bootstrap Input, Left Channel Inverting.
32 OUTL− AOUT Left Channel Inverting Output.
33 OUTL− AOUT Left Channel Inverting Output.
34 PVDD PWR Left Channel Power Stage Supply.
35 PVDD PWR Left Channel Power Stage Supply.
36 PVDD PWR Left Channel Power Stage Supply.
37 PVDD PWR Left Channel Power Stage Supply.
38 OUTL+ AOUT Left Channel Noninverting Output.
39 OUTL+ AOUT Left Channel Noninverting Output.
40 BSTL+ AIN Bootstrap Input, Left Channel Noninverting.
EPAD Exposed Pad. Use multiple vias to connect the exposed pad to the ground plane on the PCB.
1 PWR is power supply or ground pin, AIN is analog input, DIN is digital input, DIO is digital input/output, and AOUT is analog output.
SSM3582A Data Sheet
Rev. A | Page 14 of 58
TYPICAL PERFORMANCE CHARACTERISTICS
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
60dBFS I NP UT
ANALOG GAI N = 6.3V peak
R
L
= 4Ω (LOW EMI)
21861-005
Figure 7. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 6.3 V peak
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
60dBFS I NP UT
ANALOG GAI N = 8.9V peak
R
L
= 4Ω (LOW EMI)
21861-006
Figure 8. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 8.9 V peak
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
60dBFS I NP UT
ANALOG GAI N = 12.6V peak
R
L
= 4Ω (LOW EMI)
21861-007
Figure 9. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 12.6 V peak
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
60dBFS I NP UT
ANALOG GAI N = 16V peak
R
L
= 4Ω (LOW EMI)
21861-008
Figure 10. Amplitude vs. Frequency, 60 dBFS Input, Analog Gain = 16 V peak
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
NO SIG NAL
ANALOG GAI N = 6.3V peak
R
L
= 4Ω (LOW EMI)
21861-009
Figure 11. Amplitude vs. Frequency, No Signal, Analog Gain = 6.3 V peak
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
NO SIG NAL
ANALOG GAI N = 8.9V peak
R
L
= 4Ω (LOW EMI)
21861-010
Figure 12. Amplitude vs. Frequency, No Signal, Analog Gain = 8.9 V peak
Data Sheet SSM3582A
Rev. A | Page 15 of 58
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
NO SIG NAL
ANALOG GAI N = 12.6V peak
R
L
= 4Ω (LOW EMI)
21861-011
Figure 13. Amplitude vs. Frequency, No Signal, Analog Gain = 12.6 V peak
20
10
–180
20
30
50
100
200
300
500
1k
2k
3k
5k
10k
20k
AMPLITUDE (dBV)
FRE Q UE NCY ( Hz )
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
NO SIG NAL
ANALOG GAI N = 16V peak
R
L
= 4Ω (LOW EMI)
21861-012
Figure 14. Amplitude vs. Frequency, No Signal, Analog Gain = 16 V peak
0.001
1.000
0.002
0.005
0.010
0.020
0.050
THD + N ( %)
0.100
0.200
0.500
20 20k50 100 200 500
FREQUENCY (Hz)
1k 2k 5k 10k
100mW
1W
R
L
= 4Ω
PV
DD
= 4.5V
21861-013
Figure 15. THD + N vs. Frequency, RL = 4 Ω, PVDD = 4.5 V
0.001
1.000
0.002
0.005
0.010
0.020
0.050
THD + N ( %)
0.100
0.200
0.500
20 20k50 100 200 500
FRE QUENCY ( Hz )
1k 2k 5k 10k
R
L
= 4Ω
PV
DD
= 12V
5W
1W
100mW
21861-014
Figure 16. THD + N vs. Frequency, RL = 4 Ω, PVDD = 12 V
0.001
1.000
0.002
0.005
0.010
0.020
0.050
THD + N ( %)
0.100
0.200
0.500
20 20k50 100 200 500
FREQUENCY (Hz)
1k 2k 5k 10k
R
L
= 4Ω
PV
DD
= 16V
10W
1W
100mW
21861-015
Figure 17. THD + N vs. Frequency, RL = 4 Ω, PVDD = 16 V
0.001
1.000
0.002
0.005
0.010
0.020
0.050
THD + N ( %)
0.100
0.200
0.500
20 20k50 100 200 500
FREQUENCY (Hz)
1k 2k 5k 10k
R
L
= 8Ω
PV
DD
= 4.5V
100mW
500mW
21861-016
Figure 18. THD + N vs. Frequency, RL = 8 Ω, PVDD = 4.5 V
SSM3582A Data Sheet
Rev. A | Page 16 of 58
0.001
1.000
0.002
0.005
0.010
0.020
0.050
THD + N ( %)
0.100
0.200
0.500
20 20k50 100 200 500
FREQUENCY (Hz)
1k 2k 5k 10k
R
L
= 8Ω
PV
DD
= 12V
5W
1W
100mW
21861-017
Figure 19. THD + N vs. Frequency, RL = 8 Ω, PVDD = 12 V
0.001
1.000
0.002
0.005
0.010
0.020
0.050
THD + N ( %)
0.100
0.200
0.500
20 20k50 100 200 500
FREQUENCY (Hz)
1k 2k 5k 10k
R
L
= 8Ω
PV
DD
= 16V
5W
1W
100mW
21861-018
Figure 20. THD + N vs. Frequency, RL = 8 Ω, PVDD = 16 V
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
10µ
50
20µ
50µ
100µ
200µ
500µ
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
7.0V
16.0V
RL = 4Ω
ANALOG GAI N = 6.3V peak
21861-019
Figure 21. THD + N vs. Power, RL = 4 Ω, Analog Gain = 6.3 V peak
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
50
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
R
L
= 4Ω
ANALOG GAI N = 8.9V peak
10µ
20µ
50µ
100µ
200µ
500µ
4.5V
12.0V
16.0V ( 3dB G AI N ADDED)
21861-020
Figure 22. THD + N vs. Power, RL = 4 Ω, Analog Gain = 8.9 V peak
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
50
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
12.0V
16.0V
R
L
= 4Ω
ANALOG GAI N = 12.6V peak
10µ
20µ
50µ
100µ
200µ
500µ
21861-021
Figure 23. THD + N vs. Power, RL = 4 Ω, Analog Gain = 12.6 V peak
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
50
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
12.0V
16.0V
R
L
= 4Ω
ANALOG GAI N = 16V peak
10µ
20µ
50µ
100µ
200µ
500µ
21861-022
Figure 24. THD + N vs. Power, RL = 4 Ω, Analog Gain = 16 V peak
Data Sheet SSM3582A
Rev. A | Page 17 of 58
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
50
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
7.0V
16.0V
R
L
= 8Ω
ANALOG GAI N = 6.3V peak
10µ
20µ
50µ
100µ
200µ
500µ
21861-023
Figure 25. THD + N vs. Power, RL = 8 Ω, Analog Gain = 6.3 V peak
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
50
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
12.0V
16.0V
RL = 8Ω
ANALOG GAI N = 8.9V peak
10µ
20µ
50µ
100µ
200µ
500µ
21861-024
Figure 26. THD + N vs. Power, RL = 8 Ω, Analog Gain = 8.9 V peak
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
50
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
12.0V
16.0V
RL = 8Ω
ANALOG GAI N = 12.6V peak
10µ
20µ
50µ
100µ
200µ
500µ
21861-025
Figure 27. THD + N vs. Power, RL = 8 Ω, Analog Gain = 12. 6 V peak
0.001
10
0.002
0.005
0.010
0.020
0.050
0.100
0.200
THD + N ( %)
0.500
1.000
2
5
10u
50
20u
50u
100u
200u
500u
1m
2m
5m
10m
20m
POWER (W)
50m
100m
200m
500m
1
2
5
10
20
4.5V
12.0V
16.0V
R
L
= 8Ω
ANALOG GAI N = 16V peak
21861-026
Figure 28. THD + N vs. Power, RL = 8 Ω, Analog Gain = 16 V peak
0
1
2
3
4
5
6
7
56 7 8 9 10 11 12
POWER (W)
PV
DD
(V)
ANALOG GAI N = 6.3V peak
R
L
= 4Ω P
OUT
= 10%
P
OUT
= 1%
21861-028
Figure 29. Power vs. PVDD, RL = 4 Ω, Analog Gain = 6.3 V peak
(POUT Means Output Power)
0
2
4
6
8
10
12
14
POWER (W)
PV
DD
(V)
P
OUT
= 10%
P
OUT
= 1%
ANALO G G AIN = 8.9V peak
R
L
= 4Ω
7 8 9 10 11 12
21861-027
Figure 30. Power vs. PVDD, RL = 4 Ω, Analog Gain = 8.9 V peak
SSM3582A Data Sheet
Rev. A | Page 18 of 58
POWER (W)
PV
DD
(V)
0
5
10
15
20
25
30
791113 15 17
ANALO G G AIN = 12.6V peak
R
L
= 4Ω P
OUT
= 10%
P
OUT
= 1%
21861-029
Figure 31. Power vs. PVDD, RL = 4 Ω, Analog Gain = 12.6 V peak
POWER (W)
PV
DD
(V)
0
5
10
15
20
25
30
35
7911 13 15
P
OUT
= 10%
P
OUT
= 1%
ANALO G G AIN = 16V peak
R
L
= 4Ω
21861-030
Figure 32. Power vs. PVDD, RL = 4 Ω, Analog Gain = 16 V peak
EFFICIENCY (%)
POUT (W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 6.3V peak
RL = 4Ω
PVDD = 5V
0
10
20
30
40
50
60
70
80
90
100
00.5 1.0 1.5 2.0 2.5 3.0 3.5
NORMAL EMI
LOW EMI
21861-031
Figure 33. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 4 Ω, PVDD = 5 V
EFFICIENCY (%)
POUT (W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 8.9V peak
RL = 4Ω
PVDD = 7V
0
10
20
30
40
50
60
70
80
90
100
012345 6 7
NORMAL EMI
LOW EMI
21861-032
Figure 34. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 4 Ω, PVDD = 7 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak
R
L
= 4Ω
PV
DD
= 12V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
02.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
21861-033
Figure 35. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 4 Ω, PVDD = 12 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 16V peak
R
L
= 4Ω
PV
DD
= 16V
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35
NORMAL EMI
LOW EMI
21861-034
Figure 36. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 4 Ω, PVDD = 16 V
Data Sheet SSM3582A
Rev. A | Page 19 of 58
P
OUT
(W)
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 6.3V peak
R
L
= 4Ω
PV
DD
= 5V
0
10
20
30
40
50
60
70
80
90
100
00.5 1.0 1.5 2.0 2.5 3.0 3.5
NORMAL EMI
LOW EMI
21861-035
Figure 37. Efficiency vs. POUT with Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 4 Ω, PVDD = 5 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 8.9V peak
R
L
= 4Ω
PV
DD
= 7V
0
10
20
30
40
50
60
70
80
90
100
01234567
NORMAL EMI
LOW EMI
21861-036
Figure 38. Efficiency vs. POUT with Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 4 Ω, PVDD = 7 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12V peak
R
L
= 4Ω
PV
DD
= 12V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
0510 15 20
21861-037
Figure 39. Efficiency vs. POUT with Ferrite Bead, Analog Gain = 12 V peak,
RL = 4 Ω, PVDD = 12 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 16V peak
R
L
= 4Ω
PV
DD
= 16V
0
10
20
30
40
50
60
70
80
90
100
0 5 10 15 20 25 30 35
NORMAL EMI
LOW EMI
21861-038
Figure 40. Efficiency vs. POUT with Ferrite Bead, Analog Gain = 16 V peak,
RL = 4 Ω, PVDD = 16 V
0
0.002
0.004
0.006
0.008
0.010
5 7 9 11 13 15
PV
DD
(V)
I
PVDD
(A)
NORMAL EMI LOW EMI
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak
R
L
= 4Ω
21861-039
Figure 41. IPVDD vs. PVDD, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 4 Ω
0
0.002
0.004
0.006
0.008
0.010
5 7 9 11 13 15
PV
DD
(V)
I
PVDD
(A)
NORMAL EMI
LOW EMI
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak
R
L
= 4Ω
21861-040
Figure 42. IPVDD vs. PVDD, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 4 Ω
SSM3582A Data Sheet
Rev. A | Page 20 of 58
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
5 6 78910 11 12
POWER (W)
PV
DD
(V)
ANALO G G AIN = 6.3V peak
R
L
= 8Ω P
OUT
= 10%
P
OUT
= 1%
21861-041
Figure 43. Power vs. PVDD, Analog Gain = 6.3 V peak, RL = 8 Ω
0
1
2
3
4
5
6
7
78 9 10 11 12
POWER (W)
PV
DD
(V)
ANALO G G AIN = 8.9V peak
R
L
= 8Ω P
OUT
= 10%
P
OUT
= 1%
21861-042
Figure 44. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 8 Ω
0
2
4
6
8
10
12
14
78910 11 12 13 14 15 16
PV
DD
(V)
POWER (W)
P
OUT
= 10%
P
OUT
= 1%
ANALO G G AIN = 12.6V peak
R
L
= 8Ω
21861-043
Figure 45. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 8 Ω
78910 1112 13 14 15 16
PV
DD
(V)
POWER (W)
P
OUT
= 10%
P
OUT
= 1%
0
2
4
6
8
10
12
14
16
18
20
ANALO G G AIN = 16V peak
R
L
= 8Ω
21861-044
Figure 46. Power vs. PVDD, Analog Gain = 16 V peak, RL = 8 Ω
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 6.3V peak
R
L
= 8Ω
PV
DD
= 5V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
00.5 1.0 1.5 2.0
21861-045
Figure 47. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 8 Ω, PVDD = 5 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 8.9V peak
R
L
= 8Ω
PV
DD
= 7V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
21861-046
Figure 48. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 8 Ω, PVDD = 7 V
Data Sheet SSM3582A
Rev. A | Page 21 of 58
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak
R
L
= 8Ω
PV
DD
= 12V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
0 2 4 6 8 1210
21861-047
Figure 49. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 8 Ω, PVDD = 12 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 16V peak
R
L
= 8Ω
PV
DD
= 16V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
0 5 10 15 20
21861-048
Figure 50. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 8 Ω, PVDD = 16 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 6.3V peak
R
L
= 8Ω
PV
DD
= 5V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
00.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
21861-049
Figure 51. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 8 Ω, PVDD = 5 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 8.9V peak
R
L
= 8Ω
PV
DD
= 7V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
21861-050
Figure 52. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 8 Ω, PVDD = 7 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak
R
L
= 8Ω
PV
DD
= 12V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
02.5 5.0 7.5 10.0 12.5
21861-051
Figure 53. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 8 Ω, PVDD = 12 V
EFFICIENCY (%)
P
OUT
(W)
FERRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 16V peak
R
L
= 8Ω
PV
DD
= 16V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
02.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0
21861-052
Figure 54. Efficiency vs. POUT, with Ferrite Bead, Analog Gain = 16 V peak,
RL = 8 Ω, PVDD = 16 V
SSM3582A Data Sheet
Rev. A | Page 22 of 58
EFFICIENCY (%)
POUT (W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 6.3V peak (M ONO )
RL = 2Ω
PVDD = 5V
0
10
20
30
40
50
60
70
80
90
100
0 1 234567
NORMAL EMI
LOW EMI
21861-053
Figure 55. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 2 Ω, PVDD = 5 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 8.9V peak (M ONO )
R
L
= 2Ω
PV
DD
= 7V
0
10
20
30
40
50
60
70
80
90
100
024 6 8 10 12 14
NORMAL EMI
LOW EMI
21861-054
Figure 56. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 2 Ω, PVDD = 7 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak (M ONO )
R
L
= 2Ω
PV
DD
= 12.6V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
0 5 10 15 20 25 30 35 40
21861-055
Figure 57. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 2 Ω, PVDD = 12.6 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 16V peak (M ONO )
R
L
= 2Ω
PV
DD
= 16V
0
10
20
30
40
50
60
70
80
90
100
010 20 30 40 50 60 70
NORMAL EMI
LOW EMI
21861-056
Figure 58. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 2 Ω, PVDD = 16 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 6.3V peak (M ONO )
R
L
= 3Ω
PV
DD
= 5V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
21861-057
Figure 59. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 6.3 V peak,
RL = 3 Ω, PVDD = 5 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 8.9V peak (M ONO )
R
L
= 3Ω
PV
DD
= 7V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
012345678910
21861-058
Figure 60. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 8.9 V peak,
RL = 3 Ω, PVDD = 7 V
Data Sheet SSM3582A
Rev. A | Page 23 of 58
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 12.6V peak (M ONO )
R
L
= 3Ω
PV
DD
= 12V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
0 5 10 15 20 25 30
21861-059
Figure 61. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 12.6 V peak,
RL = 3 Ω, PVDD = 12 V
EFFICIENCY (%)
P
OUT
(W)
NO F E RRIT E BE AD, 220p F CAPACIT OR
ANALO G G AIN = 16V peak (M ONO )
R
L
= 3Ω
PV
DD
= 16V
0
10
20
30
40
50
60
70
80
90
100
NORMAL EMI
LOW EMI
0 5 10 15 20 25 30 35 40 45 50
21861-060
Figure 62. Efficiency vs. POUT, No Ferrite Bead, Analog Gain = 16 V peak,
RL = 3 Ω, PVDD = 16 V
0
2
4
6
8
10
12
14
5 6 7 8 9 10 11 12
POWER (W)
PV
DD
(V)
P
OUT
= 10%
P
OUT
= 1%
ANALO G G AIN = 8.9V peak (M ONO )
R
L
= 4Ω
21861-061
Figure 63. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 4 Ω
POWER (W)
PV
DD
(V)
0
5
10
15
20
25
30
78910 1112
ANALO G G AIN = 8.9V peak (M ONO )
R
L
= 2Ω
P
OUT
= 10%
P
OUT
= 1%
21861-062
Figure 64. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 2 Ω
78910 11 12 13 14 15 16
POWER (W)
PV
DD
(V)
0
10
20
30
40
50
60
P
OUT
= 10%
P
OUT
= 1%
ANALO G G AIN = 12.6V peak (M ONO )
R
L
= 2Ω
21861-063
Figure 65. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 2 Ω
78910 11 12 13 14 15 16
PV
DD
(V)
POWER (W)
P
OUT
= 10%
P
OUT
= 1%
0
10
20
30
40
50
60
70
ANALO G G AIN = 16V peak MONO )
R
L
= 2Ω
21861-064
Figure 66. Power vs. PVDD, Analog Gain = 16 V peak, RL = 2 Ω
SSM3582A Data Sheet
Rev. A | Page 24 of 58
5678 9 10 11 12
POWER (W)
PV
DD
(V)
P
OUT
= 10%
P
OUT
= 1%
0
1
2
3
4
5
6
7
8
9
ANALO G G AIN = 6.3V peak (M ONO )
R
L
= 4Ω
21861-065
Figure 67. Power vs. PVDD, Analog Gain = 6.3 V peak, RL = 4 Ω
78910 11 12
POWER (W)
PV
DD
(V)
0
2
4
6
8
10
12
14
16
18
P
OUT
= 10%
P
OUT
= 1%
ANALO G G AIN = 8.9V peak (M ONO )
R
L
= 3Ω
21861-066
Figure 68. Power vs. PVDD, Analog Gain = 8.9 V peak, RL = 3 Ω
78910 11 12 13 14 15 16
PV
DD
(V)
POWER (W)
P
OUT
= 10% P
OUT
= 1%
ANALO G G AIN = 12.6V peak (M ONO )
R
L
= 3Ω
0
5
10
15
20
25
30
35
21861-067
Figure 69. Power vs. PVDD, Analog Gain = 12.6 V peak, RL = 3 Ω
78910 11 12 13 14 15 16
PV
DD
(V)
POWER (W)
P
OUT
= 10%
P
OUT
= 1%
0
5
10
15
20
25
30
35
40
45
50
ANALO G G AIN = 16V peak (M ONO )
R
L
= 3Ω
21861-068
Figure 70. Power vs. PVDD, Analog Gain = 16 V peak, RL = 3 Ω
Data Sheet SSM3582A
Rev. A | Page 25 of 58
THEORY OF OPERATION
OVERVIEW
The SSM3582A is a stereo, Class-D audio amplifier with a filterless
modulation scheme that greatly reduces external component
count, conserving board space and reducing system cost. The
SSM3582A does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to recover the audio
component of the square wave output. Most Class-D amplifiers
use some variation of pulse-width modulation (PWM) to
generate the output switching pattern, whereas the SSM3582A
uses Σ-Δ modulation, resulting in important benefits. Σ-Δ
modulators do not produce a sharp peak with many harmonics
in the AM broadcast band, as pulse-width modulators often do.
Σ-Δ modulation reduces the amplitude of spectral components at
high frequencies, reducing EMI emission that may otherwise
radiate from speakers and long cable traces. Due to the inherent
spread spectrum nature of Σ-Δ modulation, the need for
oscillator synchronization is eliminated for designs incorporating
multiple SSM3582A amplifiers. The SSM3582A uses less power in
quiescent conditions, which helps conserve the power drawn
from the battery or power supply.
The SSM3582A integrates overcurrent and temperature protection
and a thermal warning with optional programmable automatic
gain reduction.
POWER SUPPLIES
PVDD
PVDD supplies the output power stages, as well as the low
dropout (LDO) regulator for AVDD and DVDD.
AVDD
AVDD is the analog supply used for the modulator, power
stage driver, and other analog blocks.
When the AVDD_EN pin = PVDD, the internal regulator
generates 5 V and the AVDD pin is used for decoupling only.
When the AVDD_EN pin = AGND, 5 V must be provided to
the AVDD pin from an external system source, minimizing
power losses.
DVDD
DVDD supplies the digital circuitry. The current in this node is
very low, below 1 mA.
When the DVDD_EN pin = AVDD, the internal regulator
generates 1.8 V and the DVDD pin is used for decoupling only.
When the DVDD_EN pin = AGND, 1.8 V must be provided to
the DVDD pin from an external system source, minimizing
power losses.
Table 12 summarizes the power dissipation in various supply
configurations, operating modes, and load characteristics.
Table 12. Typical Power Supply Current Consumption for fS = 48 kHz1
AVDD_
EN Pin Load
Test
Conditions
PVDD
5 V
12 V
16 V
AVDD
Pin
IAVDD
(mA)
IDVDD
(mA) IPVDD (mA)
Total Power
(mW) IPVDD (mA)
Total
Power
(mW) IPVDD (mA)
Total
Power
(mW)
Low No load SPWDN = 1 External 0.007542 0.00268 0.000065 0.042859 0.000065 0.043314 0.000065 0.043574
Automatic
power-down
External 0.007542 0.04372 0.000065 0.116731 0.000065 0.117186 0.000065 0.117446
Dither input External 6.335 0.945 2.54 46.076 4.94 92.656 6.25 133.376
PVDD No load SPWDN = 1 Internal N/A N/A 0.000065 0.000325 0.000065 0.00078 0.000065 0.00104
Automatic
power-down
Internal N/A N/A 0.209 1.045 0.286 3.432 0.329 5.264
Dither input Internal N/A N/A 9.78 48.9 12.38 148.56 14.05 224.8
Low 8 Ω + 33 µH SPWDN = 1 External 0.007542 0.00268 0.000065 0.042859 0.000065 0.043314 0.000065 0.043574
Automatic
power-down
External 0.007542 0.04372 0.000065 0.116731 0.000065 0.117186 0.000065 0.117446
Dither input External 6.432 0.942 2.59 46.8056 5.02 94.0956 6.31 134.8156
PVDD 8 Ω + 33 µH SPWDN = 1 Internal N/A N/A 0.000065 0.000325 0.000065 0.00078 0.000065 0.00104
Automatic
power-down
Internal N/A N/A 0.209 1.045 0.286 3.432 0.329 5.264
Dither input Internal N/A N/A 9.82 49.1 12.39 148.68 13.73 219.68
1 N/A means not applicable.
SSM3582A Data Sheet
Rev. A | Page 26 of 58
POWER-UP SEQUENCE
Using Only PVDD as a Source
When SSM3582A is used in single-supply mode, all internal rails
are generated from PVDD. The internal AVDD (5 V) and
DVDD (1.8 V) regulators can be enabled by pulling the
AVDD_EN and DVDD_EN pins high. AVDD_EN is pulled to
PVDD, and DVDD_EN is pulled to AVDD. The amplifier is
operational and responds to I2C writes 10 ms after applying
PVDD ≥ 5 V.
Using PVDD and External AVDD
Take care when an external 5 V is supplied to AVDD. The internal
5 V LDO regulator must be disabled by pulling the AVDD_EN pin
low. In this case, DVDD (1.8 V) is generated from PVDD. It is
important to maintain PVDD > AVDD to prevent the back
powering of PVDD.
Using PVDD and External AVDD and DVDD
If using an external AVDD and DVDD source, both the
AVDD_EN and DVDD_EN pins must be pulled low. It is
important to maintain PVDD > AVDD or DVDD to prevent
back powering PVDD.
DVDD must be present for the device to respond to I2C
commands. The device becomes operational ~10 ms after
DVDD is present. PVDD must be at least 5 V for the output
stage to turn on, and must be 6 V for optimal performance.
POWER-DOWN OPERATION
The SSM3582A offers several power-down options via the I2C.
Register 0x04 provides multiple options for setting the various
power-down modes.
When set to 1, the SPWDN bit fully powers down the device. In
this case, only the I2C and 1.8 V regulator blocks, if enabled via
the DVDD_EN pin, are kept active.
The SSM3582A monitors both the BCLK and FSYNC pins for
clock presence. When no BCLK is present, the device automa-
tically powers down all internal circuitry to its lowest power
state. When BCLK returns, the device automatically powers up
following its usual power sequence. To guarantee click and pop
free shutdown, power down the device via the SPDWN control
before clock removal.
If enabled, the APWDN_EN bit activates a low power state
after 2048 consecutive zero input samples are received. Only
the I2C and digital audio input blocks are kept active.
Individual channels can be powered down using Bits[3:2] in
Register 0x04.
The temperature sense ADC can be powered down using Bit 5
in Register 0x04.
CLOCKING
A BCLK signal must be provided to the SSM3582A for proper
operation. The BCLK signal must have a minimum frequency
of 2.048 MHz. The BCLK rate is autodetected, but the sampling
frequency must be indicated. The BCLK rates supported at
32 kHz to 48 kHz are 50, 64, 100, 128, 192, 200, 256, 384, 400,
512, 768, 800, and 1024 times the sample rate.
DIGITAL AUDIO SERIAL INTERFACE
The SSM3582A includes a standard serial audio interface that is
slave only. The interface is capable of receiving I2S, left justified,
PCM, or TDM formatted data.
The serial interfaces have three main operating modes. The stereo
modes, typically I2S or left justified, are used when there is a
single chip on the interface bus. TDM mode is more flexible
and offers the ability to have multiple chips on the bus.
Stereo Operating Modes—I2S, Left Justified
Stereo modes use both edges of FSYNC to determine the
placement of data. Stereo mode is enabled when SAI_MODE = 0,
and the I2S or left justified format is determined by the SDATA_
FMT register setting.
The I2S or left justified interface formats supports various BCLK/
FSYNC ratios (see Table 13). Sample rates from 8 kHz to 192 kHz
are accepted.
TDM Operating Mode
The TDM operating mode allows multiple chips to connect to a
single serial interface.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame. For
proper operation, this signal must be one BCLK cycle wide, trans-
itioning on a falling BCLK edge. The MSB of data is present on the
SDATA signal one BCLK cycle later. The SDATA signal is
latched on a rising edge of BCLK.
Each chip on the TDM bus can occupy 16, 24, 32, 48, or 64 BCLK
cycles, set via the TDM_BCLKS control bits. The maximum
number of devices connected to a single TDM bus depends on
the sample rate and number of bits per channel. The supported
combinations of sample rates and bit depths are described in
Table 13.
The maximum bit clock frequency is 49.152 MHz. Using the
TDM16 format, up to eight devices (16 channels) can be connected
to a single TDM interface, and can operate at up to a 96 kHz
sample rate and at 32 bits per channel. See Table 13 for the
supported options at the 48 kHz, 96 kHz, and 192 kHz sample
rates. Note that the interface is slave only, with the bit clock,
frame sync, and data provided to the device.
ADDRx pin settings dictate the default TDM slots for each device,
and can be modified using the TDM_SLOT_x control register.
Data Sheet SSM3582A
Rev. A | Page 27 of 58
Table 13. Supported BCLK Rates in MHz1
Sample
Rate (kHz)
BCLK (MHz)/FSYNC Ratio2
50 64 100 128 192 200 256 384 512 768 800 1024 2048 4096
8 to 12 N/A N/A N/A N/A N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes
16 to 24 N/A N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A
32 to 48 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A N/A
64 to 96 Yes Yes Yes Yes Yes Yes Yes Yes Yes N/A N/A N/A N/A N/A
128 to 192 Yes Yes Yes Yes Yes Yes Yes N/A N/A N/A N/A N/A N/A N/A
1 Yes means that the specified rate is supported and N/A means not applicable.
2 BCLK = (BCLK/FSYNC ratio) × sample rate.
I2C Control
The SSM3582A supports an I2C-compatible, 2-wire serial bus,
shared across multiple peripherals. Two signals, serial data
(SDA) and serial clock (SCL), carry information between the
SSM3582A and the system I2C master controller. The SSM3582A
is always a slave on the bus, and cannot initiate a data transfer.
Each slave device is identified by a unique address. The address
byte format is shown in Table 14. The address resides in the
first seven bits of the I2C write. The LSB of this byte sets either a
read or write operation. Logic Level 1 corresponds to a read
operation and Logic Level 0 corresponds to a write operation.
For device address settings, see Table 16.
Table 14. I2C Device Address Byte Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 Bit 0
0 0 1 Bit 3 Bit 2 ADDR0 ADDR1 R/W
Both SDA and SCL are open drain, and require pull-up resistors to
the input/output voltage. The SSM3582A operates within the I2C
voltage range of 1.6 V to 3.6 V.
Addressing
Initially, each device on the I2C bus is in an idle state, monitoring
the SDA and SCL lines for a start condition and the proper
address. The I2C master initiates a data transfer by establishing
a start condition, defined by a high to low transition on SDA while
SCL remains high. This start condition indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus
the R/W bit), MSB first. The device that recognizes the
transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition. The device address
for the SSM3582A is determined by the state of the ADDRx pins.
See the Device Address Setting section for more details.
The R/W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means the master writes information to the
peripheral, whereas a Logic 1 means the master reads information
from the peripheral after writing the subaddress and repeating the
start address. A data transfer takes place until a stop condition is
encountered. A stop condition occurs when SDA transitions
from low to high while SCL is held high. The timing for the I2C
port is shown in Figure 71.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, the SSM3582A immediately
jumps to the idle condition. During a given SCL high period, issue
only one start condition, one stop condition, or a single stop
condition followed by a single start condition. If using an invalid
subaddress, the SSM3582A does not issue an acknowledge and
returns to the idle condition. If the user exceeds the highest
subaddress while in automatic increment mode, one of two
actions is taken.
In read mode, the SSM3582A outputs the highest subaddress
register contents until the master device issues a no acknowledge,
indicating the end of a read. A no acknowledge condition is a
condition in which the SDA line is not pulled low on the ninth
clock pulse on SCL. If the highest subaddress location is reached
while in write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by the
SSM3582A, and the device returns to the idle condition.
Device Address Setting
The device can be set at 16 different I2C addresses using the
ADDR1 and ADDR0 pins, as well as 16 hardware modes.
ADDR1 and ADDR0 are sampled during the start-up procedure.
These pins set the appropriate operating mode, the I2C address,
and the default TDM slots. The ADDRx pins can be set to five
different voltage levels, as defined in Table 15. The ADDRx pins are
referenced to the DVDD rail of the device. Connect pull-up resistors
to the internally generated DVDD rail if the regulator is used.
Table 15. ADDRx Pin Input Level Mapping
ADDRx State
Level (V)
Connected to Ground 0
Connected to Ground Using a 47 kΩ Resistor 0.45
Left Floating 0.9
Connected to DVDD Using a 47 kΩ Resistor 1.35
Connected to DVDD 1.8
SSM3582A Data Sheet
Rev. A | Page 28 of 58
Table 16. ADDRx Pins to I2C Device Address and TDM Slot Mapping
ADDRx Pin State1
Device Address
Default TDM Slot
ADDR0 ADDR1 MONO = 0 MONO = 1
0 0 0x10 1, 2 1
0 1 0x11 3, 4 2
1 0 0x12 5, 6 3
1 1 0x13 7, 8 4
0 Pull-down 0x14 9, 10 5
0 Pull-up 0x15 11, 12 6
1 Pull-down 0x16 13, 14 7
1 Pull-up 0x17 15, 16 8
Pull-down 0 0x18 17, 18 9
Pull-down 1 0x19 19, 20 10
Pull-up 0 0x1A 21, 22 11
Pull-up 1 0x1B 23, 24 12
Pull-down Pull-down 0x1C 25, 26 13
Pull-down Pull-up 0x1D 27, 28 14
Pull-up Pull-down 0x1E 29, 30 15
Pull-up Pull-up 0x1F 31, 32 16
1 0 = connect to ground, 1 = connect to DVDD. In the case of a pull-down state, connect to ground via a 47 kΩ resistor. In the case of a pull-up state, connect to DVDD
via a 47 kΩ resistor.
Data Sheet SSM3582A
Rev. A | Page 29 of 58
I2C Read and Write Operations
Figure 72 shows the timing of a single-word write operation.
Every ninth clock, the SSM3582A issues an acknowledge by
pulling SDA low.
Figure 73 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The SSM3582A knows to increment its
subaddress register every byte because the requested subaddress
corresponds to a register or memory area with a byte word
length.
The timing of a single-word read operation is shown in Figure 74.
Note that the first R/W bit is 0, indicating a write operation,
because the subaddress must still be written to set up the internal
address. After the SSM3582A acknowledges the receipt of the
subaddress, the master must issue a repeated start command,
followed by the chip address byte with the R/W set to 1 (read).
This repeated command causes the SSM3582A SDA to reverse
and to begin driving data back to the master. The master then
responds every ninth pulse with an acknowledge pulse to the
SSM3582A. Refer to Table 17 for a list of abbreviations in Figure 72
through Figure 75.
Table 17. Abbreviations for Figure 72 Through Figure 75
Symbol Meaning
S Start bit
P Stop bit
AM Acknowledge (ACK used in Figure 72 through Figure 75) by master
AS Acknowledge (ACK used in Figure 72 through Figure 75) by slave
R/W
SCL
SDA
SDA
(CONTINUED)
SCL
(CONTINUED)
START BY
MASTER FRAME1
CHIP ADDRE S S BY TE FRAM E 2
SUBADDRESS BY TE
FRAM E 3
DATA BYTE 1 FRAM E 4
DATA BYTE 2
STOP BY
MASTER
ACK ACK
ACK ACK
21861-069
Figure 71. I2C Read/Write Timing
START
BIT STOP
BIT
R/W
= 0 ACK BY
SLAVE ACK BY
SLAVE
IC ADDRES S
(7 BITS) SUBADDRESS
(8 BITS) DATA BY TE 1
(8 BITS)
21861-070
Figure 72. Single-Word I2C Write Format
S CHIP ADDRESS,
R/W = 0 A
S
A
S
A
S
A
S
SUBADDRESS DATA-
WORD 1 DATA-
WORD 2 … P
21861-071
Figure 73. Burst Mode I2C Write Format
SCHIP
ADDRESS,
R/W = 0
CHIP
ADDRESS,
R/W = 1
A
S
A
S
A
S
A
M
SUBADDRESS DATA
BYTE 1 PDATA
BYTE N
S
21861-072
Figure 74. Single-Word I2C Read Format
SCHIP
ADDRESS,
R/W = 0
CHIP
ADDRESS,
R/W = 1
A
S
A
S
A
S
A
M
SUBADDRESS DATA-
WO RD 1 P
...
S
21861-073
Figure 75. Burst Mode I2C Read Format
SSM3582A Data Sheet
Rev. A | Page 30 of 58
STANDALONE OPERATION
The SSM3582A can be operated in a standalone hardware
control mode without any I2C control. The same ADDRx pins
used to set the I2C device address are used to set the
functionality of the device. In standalone mode, the I2C pins
(SCL and SDA) are inputs and are shorted to DVDD or AGND
to set the TDM slot/sample rate of the device (see Table 18). In
this case, the ANA_GAIN bits are set to 11 and SPWDN is set
to 0 by default.
In standalone mode, TDM slot selection, mono mode operation,
and sample rate are selected via different pin settings. The
device monitors the FSYNC signal and, if it is a 50% duty cycle,
uses I2S settings. If the FYSNC signal is a pulse, the device uses
TDM settings.
Table 18. Standalone Mode Pin Settings and Functionality
Sample Rate
Pin States
TDM Slot(s) MONO Bit ADDR0 ADDR1 SDA SCL
32 kHz to 48 kHz 0 Open 0 0 1, 2 0
1
Open
0
0
3, 4
0
Pull-down Open 0 0 5, 6 0
Pull-up Open 0 0 7, 8 0
Open 0 0 0 9, 10 0
Open 1 0 0 11, 12 0
Open Pull-down 0 0 13, 14 0
Open Pull-up 0 0 15, 16 0
8 kHz to 12 kHz Open Open 0 0 1, 2 0
32 kHz to 48 kHz 0 Open 0 1 1 1
1 Open 0 1 2 1
Pull-down Open 0 1 3 1
Pull-up Open 0 1 4 1
Open 0 0 1 5 1
Open 1 0 1 6 1
Open Pull-down 0 1 7 1
Open Pull-up 0 1 8 1
8 kHz to 12 kHz Open Open 0 1 1, 2 1
64 kHz to 96 kHz 0 Open 1 0 1, 2 0
1 Open 1 0 3, 4 0
Pull-down Open 1 0 5, 6 0
Pull-up Open 1 0 7, 8 0
Open 0 1 0 9, 10 0
Open 1 1 0 11, 12 0
Open Pull-down 1 0 13, 14 0
Open Pull-up 1 0 15, 16 0
16 kHz to 24 kHz Open Open 1 0 1, 2 0
64 kHz to 96 kHz 0 Open 1 1 1 1
1 Open 1 1 2 1
Pull-down Open 1 1 3 1
Pull-up Open 1 1 4 1
Open 0 1 1 5 1
Open 1 1 1 6 1
Open Pull-down 1 1 7 1
Open Pull-up 1 1 8 1
128 kHz to 192 kHz Open Open 1 1 1, 2 0
Data Sheet SSM3582A
Rev. A | Page 31 of 58
MONO MODE
The SSM3582A can be operated in mono mode for driving low
impedance loads. In mono mode, the left and right power stages
can be connected in parallel, as shown in Figure 87. Use caution
when setting up mono mode. For proper operation, any hardware
changes are required along with setting the register. For mono
mode operation, set the MONO bit (Register 0x04, Bit 4) to 1. By
default, this bit is set to 0 for stereo mode. After the bit is set for
mono mode, only the left channel modulator is active and it feeds
both the left and right channel power stages. The OUTL+ and
OUTR+ pins are in phase. The OUTL− and OUTR− pins are
also in phase. For mono mode, OUTL+ must be shorted to
OUTR+. Similarly, OUTL− must be shorted to OUTR−. Note
that the resistance of the short must be <10 mΩ. If the short
resistance is higher than 10 mΩ, the THD + N performance
degrades. Refer to the EVAL-SSM3582Z user guide for more
information.
In standalone mode, the ADDR0, ADDR1, SCL, and SDA pins
determine the TDM slot. See the Table 18 for the possible TDM
slot configurations in mono mode.
ANALOG AND DIGITAL GAIN
Four different gain settings are available to optimize the dynamic
range of the amplifier in relation to the PVDD supply voltage.
In software mode, the initial 19 dB gain setting can be updated
through the control interface. In standalone mode, the I2C
interface pins set the gain of the device. Table 19 summarizes
the gain settings and load drive characteristics of the amplifier.
The amplifier analog gain is set prior to enabling the device
outputs and must not be changed during operation. A proper
mute/unmute sequence is required to prevent audible transients
between gain settings.
Finer level control is available in the digital domain, with a very
flexible −70 dB to +24 dB, 0.375 dB/step ramp volume control
and selectable nonaliasing clipping point. The digital volume
control also includes a playback level limiter that can be set in
tandem with the battery voltage monitor to prevent the amplifier
from browning out the system when battery level is critically low.
POP AND CLICK SUPPRESSION
Pops and clicks are undesirable audible transients generated by
the amplifier system that do not come from the system input
signal. Voltage transients as small as 10 mV can be heard as an
audible pop in the speaker. Voltage transients at the output of
audio amplifiers often occur when shutdown is activated or
deactivated. The SSM3582A has a pop and click suppression
architecture that reduces these output transients, resulting in
noiseless activation and deactivation. Set either mute or power-
down before BCLK is removed to ensure a pop free experience.
TEMPERATURE SENSOR
The SSM3582A contains an 8-bit ADC that measures the die
temperature of the device and is enabled via the TEMP_PWDN bit
in Register 0x04. After the sensor is enabled, the temperature
can be read via the I2C in the TEMP register, Register 0x1B. The
temperature information is stored in Register 0x1B in an 8-bit,
unsigned format. The ADC input range is fixed internally from
−60°C to +195°C. To convert the hexadecimal value to the
temperature (Celsius) value, use the following steps:
1. Convert the hexadecimal value to decimal and then
subtract 60. For example, if the hexadecimal value is 0x54,
the decimal value is 84.
2. Calculate the temperature using the following equation:
Temperature = Decimal Value − 60
With a decimal value of 84,
Temperature = 84 − 60 = 24°C
Table 19. Analog Gain Settings and Drive Characteristics
ANA_GAIN
Gain (dB)
Output Voltage (VOUT)
Bit 1 Bit 0 RMS (V rms) Peak (V)
0 0 13 4.38 6.2
0 1 16 6.18 8.75
1 0 19 8.83 12.5
1 1 21 11.22 15.5
SSM3582A Data Sheet
Rev. A | Page 32 of 58
Table 20. Fault Reporting Registers
Fault Type Flag Set Condition Status Reported Register
PVDD Undervoltage PVDD below <3.6 V Register 0x18, Bit 7, UVLO_PVDD
5 V Regulator Undervoltage 5 V regulator voltage at AVDD < 3.6 V Register 0x18, Bit 6, UVLO_VREG
Limiter/Gain Reduction Engage Left channel limiter engaged Register 0x19, Bit 3, LIM_EG_L
Right channel limiter engaged Register 0x19, Bit 7, LIM_EG_R
Clipping, Left Channel Left channel DAC clipping Register 0x19, Bit 2, CLIP_L
Clipping, Right Channel Right channel DAC clipping Register 0x19, Bit 6, CLIP_R
Output Overcurrent Left channel output current > 6 A peak Register 0x19, Bit 1, AMP_OC_L
Right channel output current > 6 A peak Register 0x19, Bit 5, AMP_OC_R
Die Overtemperature Die temperature > 145°C Register 0x18, Bit 1, OTF
Die Overtemperature Warning Die temperature > 117°C Register 0x18, Bit 0, OTW
Battery Voltage > VBAT_INF_x Battery voltage PVDD > VBAT_INF_L Register 0x19, Bit 0, BAT_WARN_L
Battery voltage PVDD > VBAT_INF_R Register 0x19, Bit 4, BAT_WARN_R
Table 21. Register 0x16, Register 0x17, Fault Recovery
Fault Type Flag Set Condition Status Reported Register
Overtemperature
Warning
The amount of gain reduction applied if there is an overtemperature warning
for the left channel
Register 0x16, Bits[1:0],
OTW_GAIN_L
The amount of gain reduction applied if there is an overtemperature warning
for the right channel
Register 0x16, Bits[5:4],
OTW_GAIN_R
Manual Recovery Use to attempt manual recovery in case of a fault event Register 0x17, Bit 7, MRCV
Autorecovery Attempts When autorecovery from faults is used, set the number of attempts using this bit Register 0x17, Bits[5:4], MAX_AR
Undervoltage Recovery can be automatic or manual Register 0x17, Bit 2, ARCV_UV
Die Overtemperature Recovery can be automatic or manual Register 0x17, Bit 1, ARCV_OT
Overcurrent Recovery can be automatic or manual Register 0x17, Bit 0, ARCV_OC
FAULTS AND LIMITER STATUS REPORTING
The SSM3582A offers comprehensive protections against the
faults at the outputs and reporting to help with system design.
The faults listed in Table 20 are reported using the status registers.
The faults listed in Table 20 are reported in Register 0x18 and
Register 0x19 and can be read via I2C by the microcontroller in
the system.
In the event of a fault occurrence, use Register 0x17 to control
how the device reacts to the faults.
When the automatic recovery mode is set, the device attempts
to recover itself after the fault event and, in case the fault
persists, then the device sets the fault again. This process
repeats until the fault is resolved.
When the manual recovery mode is used, the device shuts
down and the recovery must be attempted using the system
microcontroller.
VBAT (PVDD) SENSING
The SSM3582A contains an 8-bit ADC that measures the
voltage of the battery voltage (VBAT) or PVDD supply. The battery
voltage information is stored in Register 0x1A as an 8-bit unsigned
format. The ADC input range is fixed internally at 3.8 V to 16.2 V.
To convert the hexadecimal value to the voltage value, use the
following steps:
1. Convert the hexadecimal value to decimal. For example, if
the hexadecimal value is 0xA9, the decimal value is 169.
2. Calculate the voltage using the following equation:
Voltage = 3.8 V + 12.4 V × Decimal Value/255
With a decimal value of 169,
Voltage = 3.8 V + 12.4 V × 169/255 = 12.02 V
LIMITER AND BATTERY TRACKING THRESHOLD
CONTROL
The SSM3582A contains an output limiter that can be used to
limit the peak output voltage of the amplifier. The limiter works
on the rms and peak value of the signal. The limiter threshold,
slope, attack rate, and release rate are programmable using
Register 0x0E, Register 0x0F, and Register 0x10 for the left channel
and Register 0x11, Register 0x12, Register 0x13 for the right
channel. The limiter can be enabled or disabled using LIM_EN_L,
Bits[1:0] in Register 0x0E for the left channel and the
LIM_EN_R bits, Bits[1:0] in Register 0x11, for the right channel.
Data Sheet SSM3582A
Rev. A | Page 33 of 58
The threshold at which the output is limited is determined by
the LIM_THRES_L bits setting, Bits[7:3] in Register 0x0F for
the left channel, and the LIM_THRES_R bits setting, Bits[7:3]
in Register 0x12 for the right channel. When the ouput signal
level exceeds the set threshold level, the limiter activates and
limits the signal level to the set limit. Below the set threshold,
the output level is not affected.
The limiter threshold can be set above the maximum output
voltage of the amplifier. In this case, the limiter allows maximum
peak output. In other words, the output may clip depending on
the power supply voltage and not the limiter.
The limiter threshold can be set as fixed or to vary with the
battery voltage via the VBAT_TRACK_L bit (Register 0x0E, Bit 2)
for the left channel and VBAT_TRACK_R bit (Register 0x11,
Bit 2) for right channel. When set to fixed, the limiter threshold
is fixed and does not vary with battery voltage. The threshold
can be set from 2 V peak to 16 V peak using the LIM_THRES_x
bit (see Figure 76).
VBAT
LIM_THRES_x
LIMITER THRESHOLD
LIMITER THRESHOLD FIXED AT SET VALUE
AND DOES NOT TRACK VBAT
21861-077
Figure 76. Limiter Fixed (LIM_EN_x = 01, VBAT_TRACK_x = 0)
When set to a variable threshold, the SSM3582A monitors the
VBAT supply and automatically adjusts the limiter threshold
based on the VBAT supply voltage.
The VBAT supply voltage at which the limiter begins to decrease
the output level is determined by the VBAT inflection point
(the VBAT_INF _L bits (Register 0x10, Bits[7:0]) for the left
channel and VBAT_INF_R bits (Register 0x13, Bits[7:0]) for
the right channel).
The VBAT_INF_x point is defined as the battery voltage at
which the limiter either activates or deactivates depending on
the LIM_EN_x mode (see Table 22). When the battery voltage
is greater than VBAT_INF_x, the limiter is not active. When
the battery voltage is less than VBAT_INF_X, the limiter is
activated. The VBAT_INF_x bits can be set from 3.8 V to 16.2 V.
To calculate the 8-bit value for the voltage, use the following
equation:
Voltage = 3.8 + 12.4 × Decimal Value/255
Convert the decimal value to an 8-bit hexadecimal value and
use it to set the VBAT_INF_x bits.
The slope bits (Register 0x0F and Register 0x12, Bits[1:0])
determine the rate at which the limiter threshold is lowered
relative to the amount of change in VBAT below the
VBAT_INF_x point.
The slope is the ratio of the limiter threshold reduction to the
VBAT voltage reduction.
Slope = ∆Limiter Threshold/∆VBAT
The slope ratio can be set from 1:1 to 4:1. This function is
useful to prevent early shutdown under low battery conditions.
As the VBAT voltage falls, the limiter threshold is lowered. This
lower threshold results in the lower output level and therefore
helps to reduce the current drawn from the battery and in turn
helps prevent early shutdown due to low VBAT.
The limiter offers various active modes that can be set using the
LIM_EN_x bits (Register 0x0E and Register 0x11, Bits[1:0]) and
the VBAT_TRACK_x bit, as shown in Table 22.
When LIM_EN_x = 01, the limiter is enabled. When LIM_EN_x =
10, the limiter mutes the output if VBAT falls below VBAT_INF_x.
When LIM_EN_x = 11, the limiter engages only when the battery
voltage is lower than VBAT_INF_x. When VBAT is greater
than VBAT_INF_x, no limiting occurs. Note that there is
hysteresis on VBAT_INF_x for the limiter disengaging.
The limiter, when active, reduces the gain of the amplifier. The
rate of gain reduction or attack rate is determined by the
LIM_ATR_x bits (Register 0x0E and Register 0x11, Bits[5:4]).
Similarly, when the signal level drops below the limiter threshold,
the gain is restored. The gain release rate is determined by the
LIM_RRT_x bits (Register 0x0E and Register 0x11, Bits[7:6]).
INPUT LEVEL
PEAK OUTPUT LEVEL
AMPLIFIER CLIPPING LEVEL
LIM_EN_x = 00
VBAT _TRACK_x = 0 O R 1
21861-076
Figure 77. Limiter Example (LIM_EN_x = 00, VBAT_TRACK_x = 0 or 1)
SSM3582A Data Sheet
Rev. A | Page 34 of 58
Table 22. Limiter Modes
LIM_EN_x VBAT_TRACK_x Limiter VBAT < VBAT_INF_x VBAT > VBAT_INF_x Comments
00 0 or 1 No Not applicable Not applicable See Figure 77
01 0 Fixed Use the set threshold Use the set threshold See Figure 76
01 1 Variable Lowers the threshold Use the set threshold See Figure 78 and Figure 79
10 0 or 1 Fixed Mutes the output Use the set threshold Not shown
11 0 Fixed Use the set threshold No limiting See Figure 80 and Figure 81
11 1 Variable Lowers the threshold No limiting See Figure 82 and Figure 83
INPUT LEVEL
LIMITER THRESHOLD SETTING
PEAK OUTPUT LEVEL
VBAT > V BAT_I NF_x L IMITE R
LI M IT E R THRES HOL D CHANGE F OR VBAT < V BAT_I NF_x
CHANGE IN L IM THRES HOLD = N × ( V BAT_I NF_x – VBAT)
WHERE N = 1 TO 4, SE T USI NG SLO P E BIT S IN REG 0x0F, RE G 0x12
LI M _E N_x = 01
VBAT_TRACK_x = 1
21861-078
Figure 78. Limiter Fixed (LIM_EN_x = 01, VBAT_TRACK_x = 1)
VBAT
VBAT_INF_x
LIM_THRES_x
SLOPE LIMITER THRESHOLD LOWERS
FO R V BAT < V BAT_I NF_x
LIMITER THRESHOLD STAYS AT
THE S E T VALUE FOR V BAT > V BAT_I NF_x
LIMITER THRESHOLD
21861-079
Figure 79. Limiter Threshold vs. VBAT in Limiter Tracking Mode
(LIM_EN_x = 01, VBAT_TRACK_x = 1)
INPUT LEVEL
LIMITER THRESHOLD SETTING
PEAK OUTPUT LEVEL
NO CHANG E IN L IM THRES HOL D P E R V BAT
AMPLIFIER CLIPPING LEVEL
LI M_EN_x = 11
VBAT_TRACK_x = 0
21861-080
Figure 80. Limiter Example (LIM_EN_x = 11, VBAT_TRACK_x = 0)
VBAT
LIM_THRES_x
LIMITER THRESHOLD
LIMITER THRESHOLD FIXED AT SET VALUE
AND DOES NOT TRACK VBAT
21861-081
Figure 81. Limiter Fixed (LIM_EN_x = 11, VBAT_TRACK_x = 0)
INPUT LEVEL
LIMITER THRESHOLD SETTING
PEAK OUTPUT LEVEL
VBAT > VBAT_INF_x LIMITER IS NOT ACTIVE
LI M IT E R THRES HOL D CHANGE FO R V BAT < VBAT_I NF
CHANGE IN L IM THRES HOL D = N × ( V BAT_INF_x – VBAT)
WHERE N = 1 TO 4, SE T USING S LOP E BIT IN REG 0x0F , REG 0x12
AMPLIFIER CLIPPING LEVEL
LI M _E N_x = 11
VBAT_TRACK_x = 1
21861-082
Figure 82. Limiter Example (LIM_EN_x = 11, VBAT_TRACK_x = 1)
VBAT
VBAT_INF_x
SET LIM_THRES_x
SLOPE LIMITER THRESHOLD LOWERS
FOR VBAT < VBAT_INF_x
LIMITER THRESHOLD INACTIVE FOR VBAT > VBAT_INF_x
LIMITER THRESHOLD
Figure 83. Limiter Threshold vs. VBAT in Limiter Tracking Mode
(LIM_EN_x = 11, VBAT_TRACK_x = 1)
Data Sheet SSM3582A
Rev. A | Page 35 of 58
HIGH FREQUENCY CLIPPER
The high frequency clipper can be controlled via the
DAC_CLIP_L bits (Register 0x14, Bits[7:0]) and the
DACL_CLIP_R bits (Register 0x15, Bits[7:0]).
These bits determine the clipper threshold, relative to full scale.
When enabled, the clipper digitally clips the signal after the
DAC interpolation.
EMI NOISE
The SSM3582A uses a proprietary modulation and spread
spectrum technology to minimize EMI emissions from the
device. The SSM3582A passes FCC Class-B emissions testing
with an unshielded 20 inch cable using ferrite bead-based
filtering. For applications that have difficulty passing FCC
Class-B emission tests, the SSM3582A includes an ultralow
EMI emissions mode that significantly reduces the radiated
emissions at the Class-D outputs, particularly above 100 MHz.
Note that reducing the supply voltage greatly reduces radiated
emissions.
OUTPUT MODULATION DESCRIPTION
The SSM3582A uses three-level, Σ-Δ output modulation. Each
output can swing from ground to PVDD, and vice versa. Ideally,
when no input signal is present, the output differential voltage
is 0 V because there is no need to generate a pulse. In a real-
world situation, noise sources are always present.
Due to this constant presence of noise, a differential pulse is
occasionally generated in response to this stimulus. A small
amount of current flows into the inductive load when the
differential pulse is generated. However, typically, the output
differential voltage is 0 V. This feature ensures that the current
flowing through the inductive load is small.
When the user sends an input signal, an output pulse is generated
to follow the input voltage. The differential pulse density is
increased by raising the input signal level. Figure 84 depicts
three-level, Σ-Δ output modulation with and without input
stimulus.
OUT P UT > 0V +5V
0V
OUTx+
+5V
0V
OUTx–
+5V
0V
VOUT
OUT P UT < 0V
+5V
0V
OUTx+ +5V
0V
OUTx–
0V
–5V
VOUT
OUT P UT = 0V
OUTx+ +5V
0V
+5V
0V
OUTx–
+5V
–5V
0V
VOUT
21861-074
Figure 84. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
SSM3582A Data Sheet
Rev. A | Page 36 of 58
BOOTSTRAP CAPACITORS
The output stage of the SSM3582A uses a high-side NMOS
driver, rather than a PMOS driver. To generate the gate drive
voltage for the high-side NMOS, a bootstrap capacitor for each
output terminal acts as a floating power supply for the switching
cycle. Use 0.22 μF capacitors to connect the appropriate output pin
(OUTx±) to the bootstrap pin (BSTx±). For example, connect a
0.22 μF capacitor between OUTL+ (a left channel, noninverting
output) and BSTL+ for bootstrapping the left channel. Similarly,
connect another 0.22 μF capacitor between the OUTL− and
BSTL− pins for the left channel inverting output.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low THD, and high PSRR, proper
power supply decoupling is necessary. Noise transients on the
power supply lines are short duration voltage spikes. These spikes
can contain frequency components that extend into the hundreds
of megahertz. The power supply input must be decoupled with
a good quality, low ESL, low ESR bulk capacitor larger than 220 µF.
This capacitor bypasses low frequency noise to the ground
plane. For high frequency decoupling, place 1 µF capacitors as
close as possible to the PVDD pins of the device.
OUTPUT EMI FILTERING
Additional EMI filtering may be required when the speaker
traces and cables are long and present a significant capacitive
load that can create additional draw from the amplifier. Typical
power ferrites present a significant magnetic hysteresis cycle
that affects THD performance and are not recommended for
high performance designs. The NFZ filter series from Murata,
designed in close collaboration with Analog Devices, Inc.,
provides a closed hysteresis loop similar to an air coil with
minimum impact on performance. Products are available at
upwards of 4 A rms, well suited to this application. A small
capacitor can be added between the output of the filter and
ground to further attenuate very high frequencies. Take care
to ensure the capacitor is properly sized to avoid affecting idle
power consumption or efficiency.
PCB PLACEMENT
Component selection and placement influence greatly on
system performance, both measured and subjective. Proper
PVDD layout and decoupling is necessary to reach the specified
level of performance, particularly at the highest power levels.
The placement shown in Figure 85 ensures proper output stage
decoupling for each channel, for minimum supply noise and
maximum separation between channels. Additional bulk
decoupling is necessary to reduce current ripple at low
frequencies, and can be shared between several amplifiers
in a multichannel solution.
BSTL+
0.22µ F CAPACIT OR PVDD DECOUPLI NG
0.1µ F CAPACIT OR BSTL–
0.22µ F CAPACIT OR
DVDD DECO UP LI NG
0.1µ F CAPACIT OR
AVDD DECO UP LI NG
0.1µ F CAPACIT OR
BSTR+
0.22µ F CAPACIT OR BSTR–
0.22µ F CAPACIT OR
PVDD DECOUPLI NG
0.1µ F CAPACIT OR
21861-075
Figure 85. Recommended Component Placement
Data Sheet SSM3582A
Rev. A | Page 37 of 58
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A poor layout increases voltage drops, consequently
decreasing efficiency. A good practice is to use short, wide PCB
tracks to decrease voltage drops and minimize inductance. For
the lowest dc resistance (DCR) and minimum inductance,
ensure that track widths for the outputs are at least 200 mil for
every inch of length and use 1 oz. or 2 oz. copper.
To maintain high output swing and high peak output power,
and to maintain minimal trace resistances, the PCB traces that
connect the output pins to the load and supply pins must be as
wide as possible. In addition, good PCB layout isolates critical
analog paths from sources of high interference. Separate high
frequency circuits (analog and digital) from low frequency circuits.
PVDD and PGND carry most of the device current, and must
be properly decoupled with multiple capacitors at the device
pins. To minimize ground bounce, use independent large traces
to carry PVDD and PGND to the power supply, thus reducing
the amount of noise the amplifier bridges inject in the circuit,
particularly if common ground impedance is significant. Proper
grounding guidelines help improve audio performance, minimize
crosstalk between channels, and prevent switching noise from
coupling into the audio signal.
Properly designed multilayer PCBs can reduce EMI emission
and increase immunity to the RF field by a factor of 10 or more,
compared with double sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double sided board is often disrupted by
signal crossover.
If the system has separate analog and digital ground and power
planes, the analog ground plane must be directly beneath the
analog power plane, and, similarly, the digital ground plane must
be directly beneath the digital power plane. There must be no
overlap between the analog and digital ground planes or between
the analog and digital power planes.
SSM3582A Data Sheet
Rev. A | Page 38 of 58
REGISTER SUMMARY
Table 23. Register Summary
Reg
Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00
VENDOR_ID [7:0] VENDOR 0x41 R
0x01
DEVICE_ID1 [7:0] DEVICE1 0x35 R
0x02
DEVICE_ID2 [7:0] DEVICE2 0x82 R
0x03
REVISION [7:0] REV 0x01 R
0x04
POWER_CTRL [7:0] APWDN_EN RESERVED TEMP_PWDN MONO R_PWDN L_PWDN RESERVED SPWDN 0xA1 R/W
0x05
AMP_DAC_CTRL [7:0] DAC_LPM RESERVED DAC_POL_R DAC_POL_L EDGE RESERVED ANA_GAIN 0x8A R/W
0x06
DAC_CTRL [7:0] DAC_HV DAC_MUTE_R DAC_MUTE_L DAC_HPF RESERVED DAC_FS 0x02 R/W
0x07
VOL_LEFT_CTRL [7:0] VOL_L 0x40 R/W
0x08
VOL_RIGHT_CTRL [7:0] VOL_R 0x40 R/W
0x09
SAI_CTRL1 [7:0] RESERVED BCLK_POL TDM_BCLKS FSYNC_MODE SDATA_FMT SAI_MODE 0x11 R/W
0x0A
SAI_CTRL2 [7:0] SDATA_EDGE RESERVED DATA_WIDTH VOL_ZC_ONLY CLIP_LINK VOL_LINK AUTO_SLOT 0x07 R/W
0x0B
SLOT_LEFT_CTRL [7:0] RESERVED TDM_SLOT_L 0x00 R/W
0x0C
SLOT_RIGHT_CTRL [7:0] RESERVED TDM_SLOT_R 0x01 R/W
0x0E
LIM_LEFT_CTRL1 [7:0] LIM_RRT_L LIM_ATR_L RESERVED VBAT_TRACK_L LIM_EN_L 0xA0 R/W
0x0F
LIM_LEFT_CTRL2
[7:0]
LIM_THRES_L
RESERVED
SLOPE_L
0x51
R/W
0x10
LIM_LEFT_CTRL3 [7:0] VBAT_INF_L 0x22 R/W
0x11
LIM_RIGHT_CTRL1 [7:0] LIM_RRT_R LIM_ATR_R LIM_LINK VBAT_TRACK_R LIM_EN_R 0xA8 R/W
0x12
LIM_RIGHT_CTRL2 [7:0] LIM_THRES_R RESERVED SLOPE_R 0x51 R/W
0x13
LIM_RIGHT_CTRL3 [7:0] VBAT_INF_R 0x22 R/W
0x14
CLIP_LEFT_CTRL [7:0] DAC_CLIP_L 0xFF R/W
0x15
CLIP_RIGHT_CTRL [7:0] DAC_CLIP_R 0xFF R/W
0x16
FAULT_CTRL1 [7:0] RESERVED OTW_GAIN_R RESERVED OTW_GAIN_L 0x00 R/W
0x17
FAULT_CTRL2 [7:0] MRCV RESERVED MAX_AR RESERVED ARCV_UV ARCV_OT ARCV_OC 0x30 R/W
0x18
STATUS1 [7:0] UVLO_PVDD UVLO_VREG RESERVED OTF OTW 0x00 R
0x19
STATUS2 [7:0] LIM_EG_R CLIP_R AMP_OC_R BAT_WARN_R LIM_EG_L CLIP_L AMP_OC_L BAT_WARN_L 0x00 R
0x1A
VBAT [7:0] VBAT 0x00 R
0x1B
TEMP [7:0] TEMP 0x00 R
0x1C
SOFT_RESET [7:0] RESERVED S_RST 0x00 R/W
Data Sheet SSM3582A
Rev. A | Page 39 of 58
REGISTER DETAILS
Address: 0x00, Reset: 0x41, Name: VENDOR_ID
Vendor ID
0
1
1
0
2
0
3
0
4
0
5
0
6
1
7
0
[7: 0] VENDOR (R)
Table 24. Bit Descriptions for VENDOR_ID
Bits Bit Name Settings Description Reset Access
[7:0] VENDOR Vendor ID 0x41 R
Address: 0x01, Reset: 0x35, Name: DEVICE_ID1
Device ID 1
0
1
1
0
2
1
3
0
4
1
5
1
6
0
7
0
[7: 0] DEVICE1 (R)
Table 25. Bit Descriptions for DEVICE_ID1
Bits Bit Name Settings Description Reset Access
[7:0] DEVICE1 Device ID 1 0x35 R
Address: 0x02, Reset: 0x82, Name: DEVICE_ID2
Device ID 2
0
0
1
1
2
0
3
0
4
0
5
0
6
0
7
1
[7: 0] DEVICE2 (R)
Table 26. Bit Descriptions for DEVICE_ID2
Bits Bit Name Settings Description Reset Access
[7:0] DEVICE2 Device ID 2 0x82 R
Address: 0x03, Reset: 0x01, Name: REVISION
Revision Code
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] REV (R)
Table 27. Bit Descriptions for REVISION
Bits Bit Name Settings Description Reset Access
[7:0] REV Revision Code 0x1 R
SSM3582A Data Sheet
Rev. A | Page 40 of 58
Address: 0x04, Reset: 0xA1, Name: POWER_CTRL
Aut omati c Power-Down Enable.
1: Aut omati c power-down f eature enabled.
0: Aut omati c power-down f eature disabled. Software Mast er Power-Down.
1: Software mast er power- down.
0: Normal oper ation.
T emperature S ensor Power-Down.
1: T emperature sensor powered down.
0: T emperature sensor on. Left Channel Power- Down.
1: Left channel powered down.
0: Left channel powered on.
Mono Mode Select ion.
1: Stereo mode enabled.
0: Mono mode enabled. Right Channel Power -Down.
1: Right channel powered down.
0: Right channel powered on.
0
1
1
0
2
0
3
0
4
0
5
1
6
0
7
1
[7] APWDN_EN (R/W) [0] SPWDN (R/W)
[6] RESERVED [1] RESERVED
[5] TEMP_PWDN (R/W) [2] L_PWDN (R/W)
[4] MONO (R/W) [3] R_PWDN (R/W)
Table 28. Bit Descriptions for POWER_CTRL
Bits Bit Name Settings Description Reset Access
7 APWDN_EN Automatic Power-Down Enable. 0x1 R/W
0 Automatic power-down feature disabled.
1 Automatic power-down feature enabled.
6 RESERVED Reserved. 0x0 R
5 TEMP_PWDN Temperature Sensor Power-Down. 0x1 R/W
0 Temperature sensor on.
1 Temperature sensor powered down.
4 MONO Mono Mode Selection. 0x0 R/W
0 Stereo mode enabled.
1 Mono mode enabled.
3 R_PWDN Right Channel Power-Down. 0x0 R/W
0 Right channel powered on.
1 Right channel powered down.
2 L_PWDN Left Channel Power-Down. 0x0 R/W
0 Left channel powered on.
1 Left channel powered down.
1 RESERVED Reserved. 0x0 R
0 SPWDN Software Master Power-Down 0x1 R/W
0 Normal operation.
1 Software master power-down.
Data Sheet SSM3582A
Rev. A | Page 41 of 58
Address: 0x05, Reset: 0x8A, Name: AMP_DAC_CTRL
DAC Low Power Mode.
1: DAC low power mode enabled.
0: DAC low power mode disabled. Amplifier Analog Gai n S el ec t.
11: 21 dB (16 V peak).
10: 19 dB (12. 6 V peak).
1: 16 dB (8. 9 V peak).
0: 13 dB (6. 3 V peak).
Right Channel DAC O utput Polarity
Control.
1: Invert t he DAC output .
0: Normal behavior . Edge Rate Control.
1: Low EMI mode operation.
0: Normal oper ation.
Left Channel DAC Output Polar i ty
Control.
1: Invert t he DAC output .
0: Normal behavior .
0
0
1
1
2
0
3
1
4
0
5
0
6
0
7
1
[7] DAC_LPM (R/W) [1: 0] ANA_GAIN (R/W)
[6] RESERVED
[2] RESERVED
[5] DAC_POL_R (R/W)
[3] EDGE (R/W)
[4] DAC_POL_L (R/W)
Table 29. Bit Descriptions for AMP_DAC_CTRL
Bits Bit Name Settings Description Reset Access
7 DAC_LPM DAC Low Power Mode. 0x1 R/W
0 DAC low power mode disabled.
1 DAC low power mode enabled.
6 RESERVED Reserved. 0x0 R
5 DAC_POL_R Right Channel DAC Output Polarity Control. 0x0 R/W
0 Normal behavior.
1 Invert the DAC output.
4 DAC_POL_L Left Channel DAC Output Polarity Control. 0x0 R/W
0 Normal behavior.
1 Invert the DAC output.
3 EDGE Edge Rate Control. 0x1 R/W
0 Normal operation.
1 Low EMI mode operation.
2 RESERVED Reserved. 0x0 R
[1:0] ANA_GAIN Amplifier Analog Gain Select. 0x2 R/W
0 13 dB (6.3 V peak).
1 16 dB (8.9 V peak).
10 19 dB (12.6 V peak).
11 21 dB (16 V peak).
SSM3582A Data Sheet
Rev. A | Page 42 of 58
Address: 0x06, Reset: 0x02, Name: DAC_CTRL
Hard Volume Control.
1: No volume r amping.
0: Soft volume r amping. DAC Sample Rate Select .
101: 48 kHz to 72 kHz.
100: 128 kHz to 192 kHz.
11: 64 kHz to 96 kHz.
10: 32 kHz to 48 kHz.
1: 16 kHz to 24 kHz.
0: 8 kHz to 12 kHz.
DAC Right Channel Mute.
1: Right channel muted.
0: Right channel unmuted.
DAC Left Channel Mute.
1: Left channel muted.
0: Left channel unmuted. DAC High- P ass Filter.
1: DAC high-pass f i lter enabled.
0: DAC high-pass f i lter disabled.
0
0
1
1
2
0
3
0
4
0
5
0
6
0
7
0
[7] DAC_HV (R/W) [2:0] DAC_F S (R/W)
[6] DAC_MUTE_R (R/W)
[3] RESERVED
[5] DAC_MUTE_L (R/W) [4] DAC_HPF (R/W)
Table 30. Bit Descriptions for DAC_CTRL
Bits Bit Name Settings Description Reset Access
7 DAC_HV Hard Volume Control. 0x0 R/W
0 Soft volume ramping.
1 No volume ramping.
6 DAC_MUTE_R DAC Right Channel Mute. 0x0 R/W
0 Right channel unmuted.
1 Right channel muted.
5 DAC_MUTE_L DAC Left Channel Mute. 0x0 R/W
0
Left channel unmuted.
1 Left channel muted.
4 DAC_HPF DAC High-Pass Filter. 0x0 R/W
0 DAC high-pass filter disabled.
1 DAC high-pass filter enabled.
3 RESERVED Reserved. 0x0 R
[2:0] DAC_FS DAC Sample Rate Select. 0x2 R/W
0 8 kHz to 12 kHz.
1 16 kHz to 24 kHz.
10 32 kHz to 48 kHz.
11 64 kHz to 96 kHz.
100 128 kHz to 192 kHz.
101 48 kHz to 72 kHz.
Data Sheet SSM3582A
Rev. A | Page 43 of 58
Address: 0x07, Reset: 0x40, Name: VOL_LEFT_CTRL
Left Channel Volume.
0xFF: Mute.
0xFE: –71.25 dB.
0xFD: –70.875 dB.
...
0x02: ...
0x01: +23.625 dB.
0x00: +24 dB .
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
0
[7: 0] VOL_L (R/W)
Table 31. Bit Descriptions for VOL_LEFT_CTRL
Bits Bit Name Settings Description Reset Access
[7:0] VOL_L Left Channel Volume. 0x40 R/W
0x00 +24 dB.
0x01 +23.625 dB.
0x02 …
0x3F +0.375 dB.
0x40 0 dB.
0x41 −0.375 dB.
0x42 …
0xFD −70.875 dB.
0xFE −71.25 dB.
0xFF Mute.
Address: 0x08, Reset: 0x40, Name: VOL_RIGHT_CTRL
Right Channel Volume.
0xFF: Mute.
0xFE: –71.25 dB.
0xFD: –70.875 dB.
...
0x02: ...
0x01: +23.625 dB.
0x00: +24 dB .
0
0
1
0
2
0
3
0
4
0
5
0
6
1
7
0
[7: 0] VOL_R (R/W)
Table 32. Bit Descriptions for VOL_RIGHT_CTRL
Bits Bit Name Settings Description Reset Access
[7:0] VOL_R Right Channel Volume. 0x40 R/W
0x00 +24 dB.
0x01 +23.625 dB.
0x02 …
0x3F +0.375 dB.
0x40 0 dB
0x41 −0.375 dB.
0x42 …
0xFD −70.875 dB.
0xFE −71.25 dB.
0xFF Mute.
SSM3582A Data Sheet
Rev. A | Page 44 of 58
Address: 0x09, Reset: 0x11, Name: SAI_CTRL1
Serial Int erf ac e Mode Selec t.
1: T DM modes.
0: Stereo modes.
BCLK P ol arit y Cont rol.
1: Use f all i ng edge to capture SDATA.
0: Use rising edge t o capt ure SDATA.
Serial Data Format.
1: Left j usti fied f ormat.
0: S (delay by 1) format .
2
I
T DM Slot Width Selec t.
100: 64 bits.
11: 48 bits.
10: 32 bits.
1: 24 bits.
0: 16 bits.
F SYNC Mode.
1: T DM: frame start on rising edge.
Stereo: high F S YNC is left channel;
0: T DM: frame start on fal l ing edge.
Stereo: low F S YNC is left channel;
0
1
1
0
2
0
3
0
4
1
5
0
6
0
7
0
[7] RESERVED [0] SAI_MODE (R/W)
[6] BCLK_POL (R/W)
[1] SDATA_F MT (R/W)
[5: 3] TDM_BCLKS (R/W)
[2] FSYNC_MODE (R/W)
Table 33. Bit Descriptions for SAI_CTRL1
Bits Bit Name Settings Description Reset Access
7 RESERVED Reserved. 0x0 R
6 BCLK_POL BCLK Polarity Control. 0x0 R/W
0 Use rising edge to capture SDATA.
1 Use falling edge to capture SDATA.
[5:3] TDM_BCLKS TDM Slot Width Select. 0x2 R/W
0 16 bits.
1 24 bits.
10 32 bits.
11 48 bits.
100 64 bits.
2 FSYNC_MODE FSYNC Mode. 0x0 R/W
0 Stereo: low FSYNC is left channel; TDM: frame start on falling edge.
1 Stereo: high FSYNC is left channel; TDM: frame start on rising edge.
1 SDATA_FMT Serial Data Format. 0x0 R/W
0
I
2
S (delay by 1) format.
1 Left justified format.
0 SAI_MODE Serial Interface Mode Select. 0x1 R/W
0 Stereo modes.
1 TDM modes.
Data Sheet SSM3582A
Rev. A | Page 45 of 58
Address: 0x0A, Reset: 0x07, Name: SAI_CTRL2
SDAT A Edge Delay Mode.
1: Half cycle delay of SDAT A.
0: Normal oper ation. Aut omatic TDM Slot Selection.
1: ADDRx pin set tings.
Set TDM slot s aut omaticall y using
0: bits.
Set TDM slot s using TDM_SLOTx
Channel Volume Link.
1: Link both channels to VO L_L c ontrol.
0: controls.
Use independent VOL_L and VOL_R
Audio Input Data W idth.
1: 16 bits.
0: 24 bits.
High Frequenc y Clipper Link.
1: bits.
Link both channels to DAC_CLIP_L
0: bits.
Use independent l eft and right DAC_CLIP_x
Volume Control Zero-Crossing Det ec tion.
1: is detected (may be diff erent per channel).
O nl y change volume when zero-cr ossing
0: Allow volume to change at al l times.
0
1
1
1
2
1
3
0
4
0
5
0
6
0
7
0
[7] SDATA_EDGE (R/W) [0] AUTO_SLOT (R/W)
[6:5] RESERVED
[1] VOL_LINK (R/W)
[4] DATA_WIDTH (R/W)
[2] CLIP_LINK (R/W)
[3] VOL_ZC_ONLY (R/W)
Table 34. Bit Descriptions for SAI_CTRL2
Bits Bit Name Settings Description Reset Access
7 SDATA_EDGE SDATA Edge Delay Mode. 0x0 R/W
0 Normal operation.
1 Half cycle delay of SDATA.
[6:5] RESERVED Reserved. 0x0 R
4 DATA_WIDTH Audio Input Data Width. 0x0 R/W
0 24 bits.
1 16 bits.
3 VOL_ZC_ONLY Volume Control Zero-Crossing Detection. 0x0 R/W
0 Allow volume to change at all times.
1 Only change volume when zero-crossing is detected (may be different per channel).
2 CLIP_LINK High Frequency Clipper Link. 0x1 R/W
0 Use independent left and right DAC_CLIP_x bits.
1 Link both channels to DAC_CLIP_L bits.
1 VOL_LINK Channel Volume Link. 0x1 R/W
0 Use independent VOL_L and VOL_R controls.
1 Link both channels to VOL_L control.
0 AUTO_SLOT Automatic TDM Slot Selection. 0x1 R/W
0 Set TDM slots using TDM_SLOT_x bits.
1 Set TDM slots automatically using the ADDRx pin settings.
Address: 0x0B, Reset: 0x00, Name: SLOT_LEFT_CTRL
Left Channel Slot S el ect ion.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [4:0] TDM_SLOT_L (R/W)
Table 35. Bit Descriptions for SLOT_LEFT_CTRL
Bits Bit Name Settings Description Reset Access
[7:5] RESERVED Reserved. 0x0 R
[4:0] TDM_SLOT_L Left Channel Slot Selection. 0x0 R/W
SSM3582A Data Sheet
Rev. A | Page 46 of 58
Address: 0x0C, Reset: 0x01, Name: SLOT_RIGHT_CTRL
Right Channel Slot Sel ec tion.
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:5] RESERVED [4:0] TD M _SLOT_R (R/W)
Table 36. Bit Descriptions for SLOT_RIGHT_CTRL
Bits Bit Name Settings Description Reset Access
[7:5] RESERVED Reserved. 0x0 R
[4:0] TDM_SLOT_R Right Channel Slot Selection. 0x1 R/W
Address: 0x0E, Reset: 0xA0, Name: LIM_LEFT_CTRL1
Left Li miter Release Rate.
11: 800 ms/dB.
10: 1200 ms/dB.
1: 1600 ms/dB.
0: 3200 ms/dB. Left Li miter Mode.
11: Limiter on only if VBAT<VBAT _INF_L.
10: Mut e output if VBAT< VBAT_INF _L.
1: Limiter on.
0: Limiter off.
Left Li miter Attack Rate.
11: 20 µs/dB.
10: 30 µs/dB.
1: 60 µs/dB.
0: 120 µs/dB. Left Threshold Battery T rack ing.
1:
bits in Regist er 0x0F.
VBAT < VBAT_INF_L using SLO P E_L
Ramp down limiter threshold when
0: Bits in Regist er0x0F .
F i xed limit er t hreshold set by LI M_T HRE S _L
0
0
1
0
2
0
3
0
4
0
5
1
6
0
7
1
[7:6] LIM_RRT_L (R/ W) [1:0] L IM_EN _L (R/ W)
[5:4] LIM_ATR_L (R /W) [2] VBAT_TRACK_L (R/W)
[3] RESERVED
Table 37. Bit Descriptions for LIM_LEFT_CTRL1
Bits Bit Name Settings Description Reset Access
[7:6] LIM_RRT_L Left Limiter Release Rate. 0x2 R/W
0 3200 ms/dB.
1 1600 ms/dB.
10 1200 ms/dB.
11 800 ms/dB.
[5:4] LIM_ATR_L Left Limiter Attack Rate. 0x2 R/W
0 120 µs/dB.
1 60 µs/dB.
10 30 µs/dB.
11 20 µs/dB.
3 RESERVED Reserved. 0x0 R
2 VBAT_TRACK_L Left Threshold Battery Tracking. 0x0 R/W
0 Fixed limiter threshold Set by LIM_THRES Bits in Register 0x0F.
1 Ramp down limiter threshold when VBAT < VBAT_INF_L using SLOPE_L bits
in Register 0x0F.
[1:0] LIM_EN_L Left Limiter Mode. 0x0 R/W
0 Limiter off.
1 Limiter on.
10 Mute output if VBAT < VBAT_INF_L.
11 Limiter on only if VBAT < VBAT_INF_L.
Data Sheet SSM3582A
Rev. A | Page 47 of 58
Address: 0x0F, Reset: 0x51, Name: LIM_LEFT_CTRL2
Left Li miter Threshold.
31: 2 V peak.
30: 2.5 V peak.
29: 3 V peak.
...
2: 15 V peak.
1: 15.5 V peak.
0: 16 V peak. Left Li miter Threshold Reduction
Slope.
11: 4:1 t hreshold:VBAT reduction.
10: 3:1 t hreshold:VBAT reduction.
1: 2:1 t hreshold:VBAT reduction.
0: 1:1 t hreshold:VBAT reduction.
0
1
1
0
2
0
3
0
4
1
5
0
6
1
7
0
[7:3] LIM_T HRES_L (R/W) [1: 0] SLOPE_L (R /W)
[2] RESERVED
Table 38. Bit Descriptions for LIM_LEFT_CTRL2
Bits Bit Name Settings Description Reset Access
[7:3] LIM_THRES_L Left Limiter Threshold. 0xA R/W
0 16 V peak.
1 15.5 V peak.
2 15 V peak.
3 14.5 V peak.
4 14 V peak.
5 13.5 V peak.
6 13 V peak.
7 12.5 V peak.
8 12 V peak.
9 11.5 V peak.
10 11 V peak.
11 10.5 V peak.
12 10 V peak.
13 9.5 V peak.
14 9.25 V peak.
15 9 V peak.
16 8.75 V peak.
17 8.5 V peak.
18 8.25 V peak.
19 8 V peak.
20 7.5 V peak.
21 7 V peak.
22 6.5 V peak.
23 6 V peak.
24 5.5 V peak.
25 5 V peak.
26 4.5 V peak.
27 4 V peak.
28 3.5 V peak.
29 3 V peak.
30 2.5 V peak.
31 2 V peak.
2 RESERVED Reserved. 0x0 R
[1:0] SLOPE_L Left Limiter Threshold Reduction Slope. 0x1 R/W
0 1:1 threshold: VBAT reduction.
1 2:1 threshold: VBAT reduction.
10 3:1 threshold: VBAT reduction.
11 4:1 threshold: VBAT reduction.
SSM3582A Data Sheet
Rev. A | Page 48 of 58
Address: 0x10, Reset: 0x22, Name: LIM_LEFT_CTRL3
Left Li miter B att ery Voltage I nflection
Point.
0
0
1
1
2
0
3
0
4
0
5
1
6
0
7
0
[7: 0] VBAT_INF _L (R/W)
Table 39. Bit Descriptions for LIM_LEFT_CTRL3
Bits Bit Name Settings Description Reset Access
[7:0] VBAT_INF_L Left Limiter Battery Voltage Inflection Point. 0x22 R/W
Address: 0x11, Reset: 0xA8, Name: LIM_RIGHT_CTRL1
Right Limit er Release Rate.
11: 800 ms/dB.
10: 1200 ms/dB.
1: 1600 ms/dB.
0: 3200 ms/dB. Right Limiter Mode.
11: Limiter on only if VBAT<VBAT_INF _R.
10: Mut e output i f VBAT <VBAT _INF_R.
1: Limiter on.
0: Limiter off.
Right Limit er Att ack Rate.
11: 20 µs/dB.
10: 30 µs/dB.
1: 60 µs/dB.
0: 120 µs/dB. Right T hreshold B attery Tracki ng.
1:
bits in Regist er 0x12.
VBAT < VBAT_INF_R using SLOPE _R
Ramp down limiter threshold when
0: bits in Regist er 0x12.
F i xed limit er t hreshold set by LI M_THRES _R
Channel Limiter Link.
1: (use left li miter cont rols).
Link both channels to one limit er
0: limiters.
Use independent l eft and right channel
0
0
1
0
2
0
3
1
4
0
5
1
6
0
7
1
[7: 6] LIM_RRT_R (R/W) [1:0] LI M _EN _R (R/ W)
[5: 4] LIM_ATR_R (R/W) [2] VBAT_TRACK_R (R/W)
[3] LIM_LINK (R/W)
Table 40. Bit Descriptions for LIM_RIGHT_CTRL1
Bits Bit Name Settings Description Reset Access
[7:6] LIM_RRT_R Right Limiter Release Rate. 0x2 R/W
0 3200 ms/dB.
1 1600 ms/dB.
10 1200 ms/dB.
11 800 ms/dB.
[5:4] LIM_ATR_R Right Limiter Attack Rate. 0x2 R/W
0 120 µs/dB.
1 60 µs/dB.
10 30 µs/dB.
11 20 µs/dB.
3 LIM_LINK Channel Limiter Link. 0x1 R/W
0 Use independent left and right channel limiters.
1 Link both channels to one limiter (use left limiter controls).
2 VBAT_TRACK_R Right Threshold Battery Tracking. 0x0 R/W
0 Fixed limiter threshold set by LIM_THRES_R Bits in Register 0x12.
1 Ramp down limiter threshold when VBAT < VBAT_INF_R using SLOPE_R Bits
in Register 0x12.
[1:0] LIM_EN_R Right Limiter Mode. 0x0 R/W
0 Limiter off.
1 Limiter on.
10 Mute output if VBAT < VBAT_INF_R.
11 Limiter on only if VBAT < VBAT_INF_R.
Data Sheet SSM3582A
Rev. A | Page 49 of 58
Address: 0x12, Reset: 0x51, Name: LIM_RIGHT_CTRL2
Right Limit er Threshold.
31: 2 V peak.
30: 2.5 V peak.
29: 3 V peak.
...
2: 15 V peak.
1: 15.5 V peak.
0: 16 V peak. Right Limit er Threshold Reduction
Slope.
11: 4:1 t hreshold:VBAT reduction.
10: 3:1 t hreshold:VBAT reduction.
1: 2:1 t hreshold:VBAT reduction.
0: 1:1 t hreshold:VBAT reduction.
0
1
1
0
2
0
3
0
4
1
5
0
6
1
7
0
[7: 3] LIM_THRES_R (R/W) [1:0] SLOPE_R (R /W)
[2] RESERVED
Table 41. Bit Descriptions for LIM_RIGHT_CTRL2
Bits Bit Name Settings Description Reset Access
[7:3] LIM_THRES_R Right Limiter Threshold. 0xA R/W
0 16 V peak.
1 15.5 V peak.
2 15 V peak.
3 14.5 V peak.
4 14 V peak.
5 13.5 V peak.
6 13 V peak.
7 12.5 V peak.
8 12 V peak.
9 11.5 V peak.
10 11 V peak.
11 10.5 V peak.
12 10 V peak.
13 9.5 V peak.
14 9.25 V peak.
15 9 V peak.
16 8.75 V peak.
17 8.5 V peak.
18 8.25 V peak.
19 8 V peak.
20 7.5 V peak.
21 7 V peak.
22 6.5 V peak.
23 6 V peak.
24 5.5 V peak.
25 5 V peak.
26 4.5 V peak.
27 4 V peak.
28 3.5 V peak.
29 3 V peak.
30 2.5 V peak.
31 2 V peak.
2 RESERVED Reserved. 0x0 R
[1:0] SLOPE_R Right Limiter Threshold Reduction Slope. 0x1 R/W
0 1:1 threshold: VBAT reduction.
1 2:1 threshold: VBAT reduction.
10 3:1 threshold: VBAT reduction.
11 4:1 threshold: VBAT reduction.
SSM3582A Data Sheet
Rev. A | Page 50 of 58
Address: 0x13, Reset: 0x22, Name: LIM_RIGHT_CTRL3
Right Limit er Batt ery Voltage Inf l ec tion
Point.
0
0
1
1
2
0
3
0
4
0
5
1
6
0
7
0
[7: 0] VBAT_INF _R (R/W)
Table 42. Bit Descriptions for LIM_RIGHT_CTRL3
Bits Bit Name Settings Description Reset Access
[7:0] VBAT_INF_R Right Limiter Battery Voltage Inflection Point. 0x22 R/W
Address: 0x14, Reset: 0xFF, Name: CLIP_LEFT_CTRL
Left DAC High F requency Clip Value.
0x00: Clip to 1/ 256.
0xFC: ...
0xFD: Clip to 254/256.
0xFE: Clip to 255/256.
0xFF: Clip to 0 dB.
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
[7: 0] DAC_CLIP_L (R/W)
Table 43. Bit Descriptions for CLIP_LEFT_CTRL
Bits Bit Name Settings Description Reset Access
[7:0] DAC_CLIP_L Left DAC High Frequency Clip Value. 0xFF R/W
0xFF Clip to 0 dB.
0xFE Clip to 255/256.
0xFD Clip to 254/256.
0xFC …
0x00 Clip to 1/256.
Address: 0x15, Reset: 0xFF, Name: CLIP_RIGHT_CTRL
Right DAC High F requency Clip Value.
0x00: Clip to 1/ 256.
0xFC: ...
0xFD: Clip to 254/256.
0xFE: Clip to 255/256.
0xFF: Clip to 256/256.
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
[7: 0] DAC_CLIP_R (R/W)
Table 44. Bit Descriptions for CLIP_RIGHT_CTRL
Bits Bit Name Settings Description Reset Access
[7:0]
DAC_CLIP_R
Right DAC High Frequency Clip Value.
0xFF
R/W
0xFF Clip to 256/256.
0xFE Clip to 255/256.
0xFD Clip to 254/256.
0xFC …
0x00 Clip to 1/256.
Data Sheet SSM3582A
Rev. A | Page 51 of 58
Address: 0x16, Reset: 0x00, Name: FAULT_CTRL1
Left Channel Overtemperature Warning
G ai n Reduc tion.
11: 5.625 dB gain r educt i on.
10: 3 dB gain reduction.
1: 1.5 dB gain r educt i on.
0: No gain r educ tion.
Right Channel O vertemper ature W arning
G ai n Reduc tion.
11: 5.625 dB gain r educt i on.
10: 3 dB gain reduction.
1: 1.5 dB gain r educt i on.
0: No gain r educ tion.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [1:0] OT W_GAI N_L (R /W)
[5: 4] OTW_G AIN_R (R/W)
[3:2] RESERVED
Table 45. Bit Descriptions for FAULT_CTRL1
Bits Bit Name Settings Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:4] OTW_GAIN_R Right Channel Overtemperature Warning Gain Reduction. 0x0 R/W
0 No gain reduction.
1 1.5 dB gain reduction.
10 3 dB gain reduction.
11 5.625 dB gain reduction.
[3:2] RESERVED Reserved. 0x0 R
[1:0] OTW_GAIN_L Left Channel Overtemperature Warning Gain Reduction. 0x0 R/W
0 No gain reduction.
1 1.5 dB gain reduction.
10 3 dB gain reduction.
11 5.625 dB gain reduction.
SSM3582A Data Sheet
Rev. A | Page 52 of 58
Address: 0x17, Reset: 0x30, Name: FAULT_CTRL2
Engage Manual Fault Recovery At tempt.
1: is set to Manual Recovery Mode.
O ne manual r ecover y attempt if faul t
0: No action taken. Over Current Fault Aut omatic Rec overy
Control.
1: Manual rec overy using MRCV bit.
0: Aut omatic recovery enabled.
O ver Temper atur e Fault Automatic
Recovery Cont rol.
1: Manual rec overy using MRCV bit.
0: Aut omatic recovery enabled.
Maximum Aut omati c Recovery Attempts.
11: Unlimited at tempts.
10: 7 att empts.
1: 3 att empts.
0: 1 att empt.
Undervoltage Fault Automatic Rec overy
Control.
1: Manual rec overy using MRCV bit.
0: Aut omatic recovery enabled.
0
0
1
0
2
0
3
0
4
1
5
1
6
0
7
0
[7] MRCV (W1) [0] ARCV_OC (R/W)
[6] RESERVED [1] ARCV_OT (R/W)
[5: 4] MAX_AR (R/W)
[2] ARCV_UV (R/W)
[3] RESERVED
Table 46. Bit Descriptions for FAULT_CTRL2
Bits Bit Name Settings Description Reset Access
7 MRCV Engage Manual Fault Recovery Attempt. 0x0 W1
0 No action taken.
1 One manual recovery attempt if fault is set to Manual Recovery Mode.
6 RESERVED Reserved. 0x0 R
[5:4] MAX_AR Maximum Automatic Recovery Attempts. 0x3 R/W
0 1 attempt.
1 3 attempts.
10 7 attempts.
11 Unlimited attempts.
3 RESERVED Reserved. 0x0 R
Data Sheet SSM3582A
Rev. A | Page 53 of 58
Address: 0x18, Reset: 0x00, Name: STATUS1
PVDD Undervolt age Fault Condition.
1: PVDD undervolt age fault condit i on.
0: PVDD ≥ 3.6 V. Overtemperature W arning Condition.
1: O vertemperature war ni ng.
0: No overtemperature war ni ng.
Regulator Under voltage Fault Condit i on.
1: Undervoltage faul t for AVDD regulator.
0: No undervolt age fault for AVDD regul ator. Overtemper ature F aul t Condition.
1: O vertemperature fault.
0: No overtemperature fault.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] UVLO_PVDD (R) [0] OTW (R )
[6] UVLO_VREG (R) [1] OTF (R)
[5:2] RESERVED
Table 47. Bit Descriptions for STATUS1
Bits Bit Name Settings Description Reset Access
7 UVLO_PVDD PVDD Undervoltage Fault Condition. 0x0 R
0 PVDD ≥ 3.6 V.
1 PVDD undervoltage fault condition.
6 UVLO_VREG Regulator Undervoltage Fault Condition. 0x0 R
0 No undervoltage fault for AVDD regulator.
1 Undervoltage fault for AVDD regulator.
[5:2] RESERVED Reserved. 0x0 R
1 OTF Overtemperature Fault Condition. 0x0 R
0 No overtemperature fault.
1 Overtemperature fault.
0 OTW Overtemperature Warning Condition. 0x0 R
0 No overtemperature warning.
1 Overtemperature warning.
SSM3582A Data Sheet
Rev. A | Page 54 of 58
Address: 0x19, Reset: 0x00, Name: STATUS2
Right Limit er Gai n Reduc tion Engaged.
1: Limiter gain reduction ri ght on.
0: Limiter gain reduction ri ght off. Battery Voltage Warning for Left Channel
(VBAT < VBAT_INF_x).
1: VBAT < VBAT _INF _L l eft channel.
0: VBAT > VBAT _INF _L l eft channel.
Right Channel DAC Clipping Detected.
1: Clipping right channel.
0: No cli ppi ng right channel. Left Channel Amplifier Overc urrent
Condition.
1: O verc urrent left channel.
0: No overc urrent left channel.
Right Channel Amplifier Overc urrent
Condition.
1: O verc urrent ri ght channel.
0: No overc urrent ri ght channel. Left Channel DAC Clipping Detected.
1: Clipping l eft channel.
0: No cli ppi ng left channel.
Battery Voltage Warning for Right
Channel ( VBAT < VBAT _INF_x).
1: VBAT < VBAT _INF _R right channel.
0: VBAT > VBAT _INF _R right channel. Left Limit er Gai n Reduc tion Engaged.
1: Limiter gain reduction left on.
0: Limiter gain reduction left of f.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] LIM_EG_R (R) [0] BAT_WARN_L (R)
[6] CLIP_R (R) [1] AMP_OC_L (R)
[5] AMP_OC_R (R)
[2] CLI P_L (R )
[4] BAT_WARN_R (R) [3] LIM_EG_L (R )
Table 48. Bit Descriptions for STATUS2
Bits Bit Name Settings Description Reset Access
7 LIM_EG_R Right Limiter Gain Reduction Engaged. 0x0 R
0 Limiter gain reduction right off.
1 Limiter gain reduction right on.
6 CLIP_R Right Channel DAC Clipping Detected. 0x0 R
0 No clipping right channel.
1 Clipping right channel.
5 AMP_OC_R Right Channel Amplifier Overcurrent Condition. 0x0 R
0 No overcurrent right channel.
1 Overcurrent right channel.
4 BAT_WARN_R Battery Voltage Warning for Right Channel (VBAT < VBAT_INF_x). 0x0 R
0 VBAT > VBAT_INF_R right channel.
1 VBAT < VBAT_INF_R right channel.
3 LIM_EG_L Left Limiter Gain Reduction Engaged. 0x0 R
0 Limiter gain reduction left off.
1 Limiter gain reduction left on.
2 CLIP_L Left Channel DAC Clipping Detected. 0x0 R
0 No clipping left channel.
1 Clipping left channel.
1 AMP_OC_L Left Channel Amplifier Overcurrent Condition. 0x0 R
0 No overcurrent left channel.
1 Overcurrent left channel.
0 BAT_WARN_L Battery Voltage Warning for Left Channel (VBAT < VBAT_INF_x). 0x0 R
0 VBAT > VBAT_INF_L left channel.
1 VBAT < VBAT_INF_L left channel.
Address: 0x1A, Reset: 0x00, Name: VBAT
Battery Voltage Readback.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] VBAT (R)
Table 49. Bit Descriptions for VBAT
Bits Bit Name Settings Description Reset Access
[7:0] VBAT Battery Voltage Readback. 0x0 R
Data Sheet SSM3582A
Rev. A | Page 55 of 58
Address: 0x1B, Reset: 0x00, Name: TEMP
T emperature S ensor Readout
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] TEMP (R)
Table 50. Bit Descriptions for TEMP
Bits Bit Name Settings Description Reset Access
[7:0] TEMP Temperature Sensor Readout. The actual temperature in degrees Celsius is TEMP −
60 decimal.
0x0 R
Address: 0x1C, Reset: 0x00, Name: SOFT_RESET
F ul l S oftware Reset.
1: reset of devic e.
W rit e value of 1 t o perf orm full sof tware
0: No action taken.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:1] RESERVED [0] S_RST (W1)
Table 51. Bit Descriptions for SOFT_RESET
Bits Bit Name Settings Description Reset Access
[7:1] RESERVED Reserved. 0x0 R
0 S_RST Full Software Reset. 0x0 W1
0 No action taken.
1 Write value of 1 to perform full software reset of device.
SSM3582A Data Sheet
Rev. A | Page 56 of 58
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
Figure 86 shows a typical application circuit for a stereo output. Figure 87 shows a typical application circuit for a mono output.
VOLUME DAC Σ-Δ
CLASS-D
MODULATOR
VOLUME DAC Σ-Δ
CLASS-D
MODULATOR
BCLK
FSYNC
SDATA
OUTL+
OUTL–
ADDR0
SEE DEVICE ADDRESS
SETTING SECTION
ADDR1
DVDD
DVDD_EN
AGND
PVDD
PVDD
PGND
SCL
SDA I
2
C
I
2
C
TDM
I
2
S
INPUT
FULL
BRIDGE
POWER
STAGE
BSTL–
BSTR–
BSTL+
SSM3582A
+1.8V
+1.8V
(DVDD)
I
2
S/TDM
PVDD
R1
2.2kΩ R2
2.2kΩ
47kΩ
47kΩ
C3
10µF
C2
10µF
C10
0.22µF
C11
0.22µF
C15
220pF
C14
220pF
+4.5V TO + 16.5V
PVDD
4Ω/8Ω
4Ω/8Ω
FB1
FB2
OPTIONAL
FB1/F B2: M URATA F E RRIT E BE AD NFZ 2M S M 181
OPTIONAL
FB3/F B3: M URATA F E RRIT E BE AD NFZ 2M S M 181
C9
470µF
C5
10µF
C4
0.1µF
REG
DVDD REG
AVDD
C7
10µF
C6
0.1µF C8
470µF
OUTR+
OUTR–
OPEN ADDRx
ADDRx
ADDRx
ADDRx
ADDRx
ADDRx PI N SE TUP OPTI ONS DVDD_EN P IN SE TUP OPTI ONS
GND
DVDD DVDD
DVDD
47kΩ TO GND
47kΩ TO DVDD
FULL
BRIDGE
POWER
STAGE
BSTR+ C12
0.22µF
C13
0.22µF
C16
220pF C17
220pF
FB3
FB4
C1
0.1uF
AVDD
AVDD_EN
DVDD_EN
DVDD_EN
AVDD
AVDD_EN PIN SE TUP OPTI ONS
AVDD_EN
AVDD_EN
PVDD
21861-084
Figure 86. Typical Application Circuit for Stereo Output
Data Sheet SSM3582A
Rev. A | Page 57 of 58
ADDR0
SEE DEVICE ADDRESS
SETTING SECTION
ADDR1
DVDD
DVDD_EN
PVDD
I
2
C
+1.8V
(DVDD)
PVDD
C3
10µF
C2
10µF
+4.5V TO + 16.5V
PVDD
C9
470µF
C5
10µF
C4
0.1µF
REG
DVDD REG
AVDD
C7
10µF
C6
0.1µF C8
470µF
C1
0.1uF
AVDD
AVDD_EN
BCLK
FSYNC
SDATA
AGND
PVDD
PGND
SCL
SDA
I
2
C
TDM
I
2
S
INPUT VOLUME DAC FULL
BRIDGE
POWER
STAGE
Σ-Δ
CLASS-D
MODULATOR
BSTL–
BSTR–
BSTL+
SSM3582A
+1.8V
I
2
S/TDM
R1
2.2kΩ R2
2.2kΩ
C10
0.22µF
C11
0.22µF
C15
220pF
C14
220pF
2Ω/3Ω
FB1
FB2
OPTIONAL
FB1/F B2: M URATA F E RRITE BE AD NFZ 2M S M 181
VOLUME DAC FULL
BRIDGE
POWER
STAGE
Σ-Δ
CLASS-D
MODULATOR
BSTR+ C12
0.22µF
C13
0.22µF
OUTL+
OUTL–
OUTR+
OUTR–
ADDRx PIN S E TUP OPTI ONS
AVDD
PVDD
DVDD_EN PIN SE TUP OPTI ONS
DVDD_EN
DVDD_EN
AVDD_EN PIN SE TUP OPTI ONS
AVDD_EN
AVDD_EN
47kΩ
47kΩ
OPEN ADDRx
ADDRx
ADDRx
ADDRx
ADDRx
GND
DVDD DVDD
DVDD
47kΩ TO GND
47kΩ TO DVDD
21861-085
Figure 87. Typical Application Circuit for Mono Output
SSM3582A Data Sheet
Rev. A | Page 58 of 58
OUTLINE DIMENSIONS
10-08-2018-A
0.50
BSC
BOTTOM VIEW
TOP VIEW
0.05 M AX
0.02 NO M
0.203 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.20 M IN
4.70
4.60 SQ
4.50
COM P LIANT T O JEDE C S TANDARDS M O-220-WJJD-5
40 1
1110
20
21
3031
END VIEW
EXPOSED
PAD
PKG-005131
PIN 1
INDICATORAR EAOPTION S
(SEEDETAILA)
DETAIL A
(JEDEC 95)
SEATING
PLANE
PIN 1
INDICATOR
AREA
Figure 88. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
SSM3582ACPZ −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7
SSM3582ACPZ-RL −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7
SSM3582ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7
EVAL-SSM3582Z Evaluation Board
1 Z = RoHS Compliant Part.
2 The SSM3582A uses the EVAL-SSM3582Z evaluation board.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2019–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21861-8/20(A)
